www.ti.com
SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
D
Switching
Non-Blocking Architecture Allows Each
Output to be Connected to Any Input
Total Jitter < 50ps
D
D 330 mW When Operating at 1.5 Gbps
D Compatible With ANSI TIA/EIA-644-A LVDS
D
D
D
D
D
D
D
D
Standard
Available Packaging: 38-pin TSSOP
25 mV of Input Voltage Threshold Hysteresis
Propagation Delay Times, 1 ns Maximum
Inputs Electrically Compatible With LVPECL,
CML and LVDS Signal Levels
Inputs and Outputs High Impedance on
Power Down
Receiver Input and Driver Output ESD
Exceeds 8 kV
Operates From a Single 3.3-V Supply
Integrated 110-Ω Line Termination Resistors
Available With SN65LVDT125
APPLICATIONS
D TBD
DESCRIPTION
The SN65LVDS125 and SN65LVDT125 are 4x4 nonblocking
crosspoint switches. Low-voltage differential signaling (LVDS)
is used to achieve signaling rates of 1.5 Gbps per channel.
Each output driver includes a 4:1 multiplexer to allow any input
to be routed to any output. Internal signal paths are fully
differential to achieve the high signaling speeds while
maintaining low signal skews. The SN65LVDT125
incorporates 110-Ω termination resistors for those
applications where board space is a premium.
Designed to support signaling rates up to 1.5 Gbps for OC-12
clocks (622 MHz). The 1.5-Gbps signaling rate allows use in
HDTV systems, including SMPTE 292 video applications
requiring signaling rates of 1.485 Gbps. (Note: The ultimate
rate and distance of data transfer is dependent upon the
attenuation characteristics of the media, the noise coupling
to the environment, and other application specific
characteristics).
The SN65LVDS125 and SN65LVDT125 are characterized for
operation from –40°C to 85°C.
SN65LVDS125DBT ( Marked as LVDS125)
SN65LVDT125DBT ( Marked as LVDT125)
(TOP VIEW)
S10
S11
1A
1B
S20
S21
2A
2B
GND
VCC
GND
3A
3B
S30
S31
4A
4B
S40
S41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VCC
GND
1Y
1Z
1DE
2Y
2Z
2DE
GND
VCC
GND
3Y
3Z
3DE
4Y
4Z
4DE
GND
VCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
!"# $$% &'$# #(% !"#)% &%*
("% &%)%+!%# (" "$#% #$ &"#" "& #(% %$$"# " % &%*
*"+ %" # '!%# %% )% #(% *(# # $("*% &$#'% #(%%
&'$# ,#('# #$%
Copyright 2002–2003, Texas Instruments Incorporated
PRODUCT PREVIEW
FEATURES
D Signaling Rates1 >1.5 Gbps per Channel
D Supports Telecom/Datacom and HDTV Video
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM
S10 – S41
8
1DE
1A
1Y
1Z
1B
2A
2Y
2Z
2B
MUX
PRODUCT PREVIEW
3A
3B
4A
2DE
3DE
3Y
3Z
4Y
4Z
4B
4DE
Integrated 110- Termination on LVDT Only
2
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT LVDS125
A
B
ESD
VCC
VCC
VCC
VCC
PRODUCT PREVIEW
VCC
ESD
VCC
300 kΩ
400 Ω
400 Ω
S10, S41
DE
300 kΩ
7V
7V
OUTPUT LVDS125
VCC
VCC
VCC
Y
7V
Z
7V
3
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
CROSSPOINT LOGIC TABLES
S10
S11
1Y/1Z
S20
S21
2Y/2Z
S30
S31
3Y/3Z
S40
S41
4Y/4Z
0
0
1A/1B
0
0
1A/1B
0
0
1A/1B
0
0
1A/1B
0
1
2A/2B
0
1
2A/2B
0
1
2A/2B
0
1
2A/2B
1
0
3A/3B
1
0
3A/3B
1
0
3A/3B
1
0
3A/3B
1
1
4A/4B
1
1
4A/4B
1
1
4A/4B
1
1
4A/4B
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C POWER
RATING
DBT
1071 mW
DERATING FACTOR(1)
ABOVE TA = 25°C
8.5 mW/°C
TA = 85°C POWER
RATING
556 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounded and with no air flow.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
PRODUCT PREVIEW
Supply voltage range, vcc
Voltage range
Elostrostatic discharge
–0.5 V to 4 V
S, DE
–0.5 V to VCC + 2 V
(A, B)
–0.7 V to 4 V
|VA – VB| (LVDT only)
(Y, Z)
–0.5 V to 4 V
Human body model(3)
Charged-device model(4)
Continuous power dissipation
1V
±8 kV
A, B, Y, Z, and GND
All pins
±2 kV
All pins
±500 V
See Dissipation Rating Table
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC
High-level input voltage, VIH
S10–S41, 1DE–4DE
Low-level input voltage, VIL
S10–S41, 1DE–4DE
M it d off differential
Magnitude
diff
ti l input
i t voltage
lt
|VID|
MIN
NOM
3
3.3
MAX UNIT
3.6
2
V
V
0.8
V
LVDS
0.05
LVDT
0.05
0.8
V
0
3.3
V
–40
85
°C
Input voltage (any combination of common–mode or input signals)
Operating free-air temperature, TA
V
TIMING SPECIFICATIONS
PARAMETER
tSET
tHOLD
NOM
MAX UNIT
0.5
ns
Input to select hold time
0.5
ns
tSWITCH Select to switch output
4
MIN
Input to select setup time
See Figure 6
TBD
1.6
ns
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
TEST CONDITIONS
VIT+
Positive-going differential input voltage
threshold
See Figure 1 and Table 1
VIT–
Negative-going differential input voltage
threshold
See Figure 1 and Table 1
VID(HYS) Differential input voltage hysteresis
1DE–4De
IIH
High level input current
High-level
S10–S41
IIL
Low level input current
Low-level
1DE–4DE
S10–S41
Input current (A or B inputs ’LVDS)
II
Input current (A or B inputs ’LVDT)
Input current (A or B inputs ’LVDS)
II(OFF)
Input current (A or B inputs ’LVDT)
IIO
RT
CT
Input offset current (|IIA – IIB|)
(’LVDS)
Termination resistance (’LVDT)
Termination resistance(’LVDT with power-off)
Differential input
in ut capacitance(’LVDT
ca acitance( LVDT with
power-off)
MIN TYP(1)
MAX
50
–50
20
–10
VIL = 0.8
08V
VCC = 1.5 V; VI = 2.4 V or 3.3 V,
Second input at 1.2 V
VI = 0 V or 2.4 V, Other input open
VI = 2.4 V or 3.3 V, Other input open
VCC = 1.5 V; VI = 0 V or 2.4 V,
Other input open
VCC = 1.5 V; VI = 2.4 V or 3.3 V,
Other input open
mV
–10
VIH = 2 V
VCC = 1.5 V; VI = 0 V or 2.4V,
Second input at 1.2 V
20
µA
µA
–20
20
0
33
–40
40
µA
0
66
µA
–20
20
0
33
–40
40
µA
0
66
µA
6
µA
VIA = VIB, 0≤ VIA ≤ 3.3 V
VID = 300 mV, VIC= 0 V to 3.3 V
–6
90
111
132
VID = 300 mV, VIC= 0 V to 3.3 V, VCC = 1.5 V
VI = 0.4 sin (4E6πt) + 0.5 V
90
111
132
Powered down
mV
mV
25
VI = 0 V or 2.4 V, Second input at 1.2 V
VI = 2.4 V or 3.3 V, Second input at 1.2 V
UNIT
3
3
µA
PRODUCT PREVIEW
PARAMETER
µA
Ω
pF
(1) All typical values are at 25°C and with a 3.3 V supply.
5
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
350
454
mV
mV
VOD
Differential output voltage magnitude
See Figure 2
247
∆VOD
Change in differential output voltage magnitude between logic
states
VID = ±100 mV
–50
50
VOC(SS)
Steady-state common-mode output voltage
1.125
1.375
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
–50
50
mV
VOC(PP)
Peak-to-peak common-mode output voltage
50
150
mV
70
85
20
25
See Figure 3
CL = 1 pF
V
ICC
Supply current
RL=100Ω,
Disabled
IOS
Short-circuit output current
VOY or VOZ = 0 V
–26
26
mA
IOSD
Differential short circuit output current
VOD = 0 V
–12
12
mA
IOZ
High-impedance output current
VO = 0 V or VCC
±1
µA
CO
Differential output capacitance
VI = 0.4 sin(4E6πt) + 0.5 V
3
mA
pF
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high-level output
tr
tf
Differential output signal rise time (20%–80%)
tsk(p)
tsk(o)
TEST CONDITIONS
Propagation delay time, high-to-low-level output
Differential output signal fall time (20%–80%)
Pulse skew (|tPHL – tPLH|)(1)
MAX
1000
250
1000
220
UNIT
ps
220
0
750 MHz clock input(5)
750 MHz clock input(6)
tjit(pp) Peak-to-peak jitter(4)
tjit(det) Deterministic jitter, peak-to-peak(4)
1.5 Gbps 223–1 PRBS input(7)
1.5 Gbps 27–1 PRBS input(8)
Propagation delay, high-level-to–high-impedance output
TYP
250
See Figure 4
Channel-to-channel output skew(2)
tsk(pp) Part-to-part skew(3)
tjit(per) Period jitter, rms (1 standard deviation)(4)
tjit(cc) Cycle-to-cycle jitter (peak)(4)
tPHZ
tPLZ
MIN
50
ps
50
ps
120
ps
1
3.7
ps
6
23
ps
28
65
ps
17
48
ps
5
Propagation delay, low-level-to-high-impedance output
5
See Figure 5
ns
tPZH Propagation delay, high-impedance -to-high-level output
20
tPZL
Propagation delay, high-impedance-to-low-level output
20
(1) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
(2) tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(5) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%), measured over 1000 samples.
(6) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%).
(7) Input voltage = VID = 200 mV, 223–1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples.
(8) Input voltage = VID = 200 mV, 27–1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%).
6
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
IIA
VIA+VIB
2
Y
B
Z
VID
VIA
VIC
A
VIB
VOD
VOY
VOY+VOZ
2
VOZ
IIB
Figure 1. Voltage and Current Definitions
3.75 kΩ
VOD
Z
+
_
100 Ω
0 V ≤ V(test) ≤ 2.4 V
3.75 kΩ
Figure 2. Differential Output Voltage (VOD) Test Circuit
A
Y
A
≈1.4 V
B
≈1 V
49.9 Ω ±1%
VID
VOC(PP)
B
Z
1 pF
49.9 Ω ±1%
VOC
VOC(SS)
VOC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ±10 ns; RL = 100W; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.;the measurement of
VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions fot the Driver Common-Mode Output Voltage
A
VIA
VID
B
VIB
Y
1 pF
VOY
Z
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
–0.4 V
100 Ω
VOZ
tPHL
tPLH
0V
Differential
80%
VOY – VOZ
20%
tf
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ .25 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Timing Test Circuit and Waveforms
7
PRODUCT PREVIEW
Y
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
49.9 Ω ±1%
Y
1 V or 1.4 V
1 pF
1.2 V
VOY
49.9 Ω ±1%
Z
DE
1.2 V
VOZ
3V
1.5 V
0V
DE
1.4 V
1.25 V
1.5 V
VOY or VOZ
tPZH
PRODUCT PREVIEW
VOZ or VOY
tPHZ
1.2 V
1.15 V
1V
tPZL
tPLZ
:
NOTE A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
8
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
A/B
A/B
S
tSET
tHOLD
OUT
Y/Z
Y/Z
tSWITCH
PRODUCT PREVIEW
DE
A/B
A/B
S
tSET
OUT
tHOLD
Y/Z
Y/Z
tSWITCH
DE
NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 6. Input to Select for Both Rising and Falling Edge Setup and Hold Times
9
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SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
CONFIGURATION EXAMPLES
PRODUCT PREVIEW
S10
0
S30
1
S11
0
S31
0
S20
0
S40
1
S21
1
S41
1
S10
0
S30
0
S20
0
S40
0
S21
0
S41
0
1A
1Y
1A
1Y
1B
1Z
1B
1Z
2A
2Y
2Y
2B
2Z
2Z
3A
3Y
3Y
3B
3Z
3Z
4A
4Y
4Y
4B
4Z
4Z
S10
0
S30
1
S11
0
S31
0
S20
0
S40
1
S21
0
S41
0
S10
1
S30
0
S11
1
S31
0
S20
1
S40
0
S21
1
S41
0
1A
1Y
1A
1Y
1B
1Z
1B
1Z
2Y
2Y
2Z
2Z
10
S11
0
S31
0
3A
3Y
3Y
3B
3Z
3Z
4Y
4A
4Y
4Z
4B
4Z
MECHANICAL DATA
MPDS019D – FEBRUARY 1996 – REVISED FEBRUARY 2002
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–ā8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
20
24
28
30
38
44
50
A MAX
5,10
6,60
7,90
7,90
9,80
11,10
12,60
A MIN
4.90
6,40
7,70
7,70
9,60
10,90
12,40
DIM
4073252/E 02/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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