APPLICATION NOTES A V A I L A B L E AN20 • AN42 • AN44–48 • AN50 • AN52 • AN53 • AN73 Advance X9221 TerminalInformation Voltage ±5V, 64 Taps X9221 Dual E2POT™ Nonvolatile Digital Potentiometer FEATURES DESCRIPTION • • • The X9221 integrates two nonvolatile E2POT™ digitally controlled potentiometers on a monolithic CMOS microcircuit. • • • • • • • E2POTs Two in One Package Two-Wire Serial Interface Register Oriented Format —Directly Write Wiper Position —Read Wiper Position —Store as Many as Four Positions per Pot Instruction Format —Quick Transfer of Register Contents to Resistor Array Low Power CMOS Direct Write Cell —Endurance - 100,000 Writes per Register —Register Data Retention - 100 years 8 Bytes of E2PROM memory 3 Resistor Array Values —2KΩ to 50KΩ Mask Programmable Resolution: 64 Taps each Pot 20-Lead Plastic DIP and 20-Lead SOIC Packages The X9221 contains two resistor arrays, each composed of 63 resistive elements. Between each element and at either end are tap points accessible to the wiper elements. The position of the wiper element on the array is controlled by the user through the two-wire serial bus interface. Each resistor array has associated with it a wiper counter register and four 8-bit data registers that can be directly written and read by the user. The contents of the wiper counter register control the position of the wiper on the resistor array. The data register may be read or written by the user. The contents of the data registers can be transferred to the wiper counter register to position the wiper. The current wiper position can be transferred to any one of its associated data registers. FUNCTIONAL DIAGRAM R0 R1 WIPER COUNTER REGISTER (WCR) R2 R3 SCL SDA A0 A1 A2 A3 INTERFACE AND CONTROL CIRCUITRY VH0 VL0 VW0 8 DATA R0 R1 R2 R3 VH1 WIPER COUNTER RESISTOR ARRAY REGISTER POT 1 (WCR) VL1 VW1 3079 ILL F07.1 © Xicor, Inc. 1994, 1995, 1996 Patents Pending. 3079-1.6 6/12/96 T1/C1/D0 NS 1 Characteristics subject to change without notice X9221 PIN DESCRIPTIONS PIN NAMES Symbol SCL SDA A0–A3 VH0–VH1, VL0–VL1 Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9221. Serial Data (SDA) VW0–VW1 SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. RES Description Serial Clock Serial Data Address Potentiometers (terminal equivalent) Potentiometers (wiper equivalent) Reserved (Do not connect) 3079 PGM T01 PRINCIPLES OF OPERATION The X9221 is a highly integrated microcircuit incorporating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the E2POT potentiometers. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9221 Serial Interface The X9221 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9221 will be considered a slave device in all applications. Potentiometer Pins VH (VH0 – VH1), VL (VL0 – VL1) The VH and VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW (VW0 – VW1) Clock and Data Conventions The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. PIN CONFIGURATION Start Condition DIP/SOIC VW0 1 20 VCC All commands to the X9221 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9221 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. VL0 2 19 RES VH0 3 18 RES A0 4 17 RES A2 5 16 A1 VW1 6 15 A3 Stop Condition VL1 7 14 SCL VH1 8 13 RES SDA 9 12 RES All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. VSS 10 11 RES X9221 3079 ILL F01.1 2 X9221 Acknowledge The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9221 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9221 to respond with an acknowledge. Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. See Figure 7. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms E2PROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9221 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9221 is still busy with the write operation no ACK will be returned. If the X9221 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. The X9221 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9221 will respond with a final acknowledge. Array Description The X9221 is comprised of two resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH and VL inputs). Flow 1. ACK Polling Sequence At both ends of each array and between each resistor segment is a FET switch connected to the wiper (VW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six least significant bits of the WCR are decoded to select, and enable, one of sixty-four switches. NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. ISSUE SLAVE ADDRESS ISSUE START ACK RETURNED? Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9221 this is fixed as 0101[B]. FURTHER OPERATION? 0 1 NO YES DEVICE TYPE IDENTIFIER 1 NO YES Figure 1. Slave Address 0 ISSUE STOP A3 A2 A1 A0 ISSUE INSTRUCTION ISSUE STOP PROCEED PROCEED DEVICE ADDRESS 3079 ILL F18 3079 ILL F08 3 X9221 Instruction Structure current wiper position to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between either potentiometer and their associated registers or it may occur between both of the potentiometers and one of their associated registers. The next byte sent to the X9221 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9221; either between the host and one of the data registers or directly between the host and the WCR. These instructions are: Read WCR, read the current wiper position of the selected pot; Write WCR, change current wiper position of the selected pot; Read Data Register, read the contents of the selected nonvolatile register; Write Data Register, write a new value to the selected data register. The sequence of operations is shown in Figure 4. Figure 2. Instruction Byte Format POTENTIOMETER SELECT I3 I2 I1 I0 0 P0 INSTRUCTIONS R1 R0 REGISTER SELECT 3079 ILL F09.1 The Increment/Decrement command is different from the other commands. Once the command is issued and the X9221 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. The four high order bits define the instruction. The sixth bit (P0) selects which one of the two potentiometers is to be affected by the instruction. The last two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM. The response of the wiper to this action will be delayed tSTPWV. A transfer from WCR’s Figure 3. Two-Byte Command Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 0 P0 R1 R0 A C K S T O P 3079 ILL F10 4 X9221 Figure 4. Three-Byte Command Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 0 P0 R1 R0 A C K 0 0 D5 D4 D3 D2 A C K D1 D0 S T O P 3079 ILL F11 Figure 5. Increment/Decrement Command Sequence SCL SDA X S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 0 P0 X R1 R0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P 3079 ILL F12 Figure 6. Increment/Decrement Timing Limits INC/DEC CMD ISSUED tCLWV SCL SDA VW VOLTAGE OUT 3079 ILL F13 5 X9221 Table 1. Instruction Set Instruction Read WCR I3 1 I2 0 Instruction Format I1 I0 0 P0 R1 Ro (7) 0 1 0 1/0 N/A N/A Write WCR 1 0 1 0 0 1/0 N/A N/A Read Data Register Write Data Register XFR Data Register to WCR 1 0 1 1 0 1/0 1/0 1/0 1 1 0 0 0 1/0 1/0 1/0 1 1 0 1 0 1/0 1/0 1/0 XFR WCR to Data Register 1 1 1 0 0 1/0 1/0 1/0 Global XFR Data Register to WCR 0 0 0 1 N/A N/A 1/0 1/0 Global XFR WCR to Data Register 1 0 0 0 N/A N/A 1/0 1/0 Increment/Decrement Wiper 0 0 1 0 0 1/0 N/A N/A Operation Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Register pointed to by P0 and R1–R0 Write new value to the Register pointed to by P0 and R1–R0 Transfer the contents of the Register pointed to by P0 and R1–R0 to its associated WCR Transfer the contents of the WCR pointed to by P0 to the Register pointed to by R1–R0 Transfer the contents of all four Data Registers pointed to by R1–R0 to their respective WCR Transfer the contents of all WCRs to their respective data Registers pointed to by R1–R0 Enable Increment/decrement of the WCR pointed to by P0 3079 PGM T11.1 Notes: (7) N/A = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical) Figure 7. Acknowledge Response from Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 3079 ILL F14 6 X9221 DETAILED OPERATION The WCR is a volatile register; that is, its contents are lost when the X9221 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Both E2POT potentiometers share the serial interface and share a common architecture. Each potentiometer is comprised of a resistor array, a wiper counter register and four data registers. A detailed discussion of the register organization and array operation follows. Data Registers Each potentiometer has four nonvolatile data registers. These can be read or written directly by the host and data can be transferred between any of the four data registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. Wiper Counter Register The X9221 contains two wiper counter registers (WCR), one for each E2POT potentiometer. The WCR can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write WCR instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction; finally, it is loaded with the contents of its data register zero (R0) upon power-up. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Figure 8. Detailed Potentiometer Block Diagram SERIAL DATA PATH VH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 REGISTER 1 8 REGISTER 2 6 REGISTER 3 PARALLEL BUS INPUT WIPER COUNTER REGISTER INC/DEC LOGIC IF WCR = 00[H] THEN VW = VL UP/DN IF WCR = 3F[H] THEN VW = VH MODIFIED SCL UP/DN CLK C O U N T E R D E C O D E VL VW 3079 ILL F15 7 X9221 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on SCK, SCL or any Address Input with Respect to VSS ................................... –1V to +7V Voltage on any VH or VL Referenced to VSS ......... ±8V ∆V = |VH–VL| ......................................................... 16V Lead Temperature (Soldering, 10 seconds)...... 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. Max. Supply Voltage Limits 0°C –40°C –55°C +70°C +85°C +125°C X9221 5V ±10% 3079 PGM T03.1 3079 PGM T02 ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter RTOTAL End to End Resistance Power Rating IW Wiper Current RW Wiper Resistance VTERM Voltage on any VH or or VL Pin Noise Resolution Absolute Linearity (1) Relative Linearity (2) Temperature Coefficient Min. –20 –1 –5 Limits Typ. Max. +20 50 +1 40 100 +5 ≤120 1.6 +1 +0.2 –1 –0.2 ±300 Units % mW mA Ω V dB/ % MI(3) MI(3) ppm/°C Test Conditions 25°C, each pot Wiper Current = ± 1mA Ref: 1V Vw(n)(actual) – Vw(n)(expected) Vw(n + 1) – [Vw(n) + MI] 3079 PGM T04.2 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter lCC Supply Current (Active) ISB ILI ILO VIH VIL VOL VCC Current (Standby) Input Leakage Current Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage Min. Limits Typ. Max. 3 200 500 10 10 VCC + 1 0.8 0.4 2 –1 Units mA µA µA µA V V V Test Conditions fSCL = 100KHz, SDA = Open, Other Inputs = VSS SCL=SDA=VCC, Addr.= VSS VIN = VSS to VCC VOUT = VSS to VCC IOL = 3mA 3079 PGM T05.3 Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH – VL)/63, single pot 8 X9221 ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum Endurance Data Retention 100,000 100 Data Changes per Register Years 3079 PGM T06.2 CAPACITANCE Symbol (5) CI/O CIN(5) Parameter Max. Units Test Conditions Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3 and SCL) 8 6 pF pF VI/O = 0V VIN = 0V 3079 PGM T07 POWER-UP TIMING Symbol Parameter Max. Units tPUR(6) tPUW(6) Power-up to Initiation of Read Operation Power-up to Initiation of Write Operation 1 5 ms ms 3079 PGM T08 A.C. CONDITIONS OF TEST Input Pulse Levels EQUIVALENT A.C. TEST CIRCUIT VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times Input and Output Timing Levels 5V 1533Ω 10ns SDA OUTPUT VCC x 0.5 3079 PGM T09 100pF Notes: (5) This parameter is periodically sampled and not 100% tested. (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 3079 ILL F02.1 Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance 120 RESISTANCE (KΩ) WAVEFORM RMIN = 100 80 VCC MAX RMAX = IOL MIN =1.8KΩ tR CBUS MAX. RESISTANCE 60 40 20 MIN. RESISTANCE 0 0 20 40 60 80 100 120 BUS CAPACITANCE (pF) 3079 ILL F17 9 X9221 A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated) Limits Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz tLOW Clock LOW Period 4700 ns tHIGH Clock HIGH Period 4000 ns tR SCL and SDA Rise Time 1000 ns tF SCL and SDA Fall Time 300 ns Ti Noise Suppression Time Constant 100 ns (Glitch Filter) tSU:STA Start Condition Setup Time (for a Repeated 4700 ns Start Condition) tHD:STA Start Condition Hold Time 4000 ns tSU:DAT Data in Setup Time 250 ns tHD:DAT Data in Hold Time 0 ns tAA SCL LOW to SDA Data Out Valid 300 3500 ns tDH Data Out Hold Time 300 ns tSU:STO Stop Condition Setup Time 4700 ns tBUF Bus Free Time Prior to New Transmission 4700 ns tWR Write Cycle Time (Nonvolatile Write Operation) 10 ms tSTPWV Wiper Response Time From Stop Generation 1000 µs tCLWV Wiper Response From SCL LOW 500 µs tR VCC VCC Power-up Rate 0.2 50 mV/µs Reference Figure 10 10 10 10 10 10 10 & 12 10 & 12 10 10 11 11 10 & 12 10 13 13 6 3079 PGM T10.3 Figure 10. Input Bus Timing tHIGH tLOW tF tR SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA (DATA IN) tBUF 3079 ILL F03 10 X9221 Figure 11. Output Bus Timing SCL tAA tDH SDA OUT (ACK) SDA SDA OUT SDA OUT 3079 ILL F04 Figure 12. Start Stop Timing START CONDITION STOP CONDITION SCL tSU:STA tHD:STA tSU:STO SDA DATA IN 3079 ILL F05 Figure 13. Write Cycle and Wiper Response Timing SCL CLOCK 8 CLOCK 9 START STOP tWR SDA SDAIN ACK tSTPWV WIPER OUTPUT 3079 ILL F06 11 X9221 PACKAGING INFORMATION 20-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.060 (26.92) 0.980 (24.89) 0.280 (7.11) 0.240 (6.096) PIN 1 INDEX PIN 1 — 0.005 (0.127) 0.900 (23.66) REF. 0.195 (4.95) 0.115 (2.92) SEATING PLANE –– 0.015 (0.38) (3.81) 0.150 (2.92) 0.1150 0.10 (BSC) (2.54) 0.022 (0.559) 0.014 (0.356) 0.070 (1.778) 0.045 (1.143) 0.300 (7.62) (BSC) 0° 15° 0.014 (0.356) 0.008 (0.2032) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F18.1 12 X9221 PACKAGING INFORMATION 20-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.50) 0.496 (12.60) 0.508 (12.90) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0° – 8° 0.420" 0.007 (0.18) 0.011 (0.28) 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 20 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F23 13 X9221 ORDERING INFORMATION X9221 Y P T V VCC Limits Blank = 5V ±10% Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 20-Lead Plastic DIP S = 20-Lead SOIC Potentiometer Organization Pot 0 Pot 1 Y = 2K 2K W = 10K 10K U = 50K 50K LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 14