TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 D D D D D D D D D D D 8-Bit Output For Use in Microprocessor-Based Systems Very High-Speed SNAP! Pulse Programming Power-Saving CMOS Technology 3-State Output Buffers 400-mV Minimum DC Noise Immunity With Standard TTL Loads Latchup Immunity of 250 mA on All Input and Output Pins No Pullup Resistors Required Low Power Dissipation (VCC = 5.5 V) – Active . . . 165 mW Worst Case – Standby . . . 0.55 mW Worst Case (CMOS-Input Levels) Temperature Range Options J PACKAGE ( TOP VIEW ) VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC PGM NC A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 FM PACKAGE ( TOP VIEW ) 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A16 VPP VCC PGM NC D Organization . . . 131 072 by 8 Bits Single 5-V Power Supply Operationally Compatible With Existing Megabit EPROMs Industry Standard 32-Pin Dual-In-line Package and 32-Lead Plastic Leaded Chip Carrier All Inputs / Outputs Fully TTL Compatible Maximum Access / Minimum Cycle Time VCC ± 10% ’27C/PC010A-10 100 ns ’27C/ PC010A-12 120 ns ’27C/ PC010A-15 150 ns ’27C/ PC010A-20 200 ns A12 A15 D D D 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 description 21 A14 A13 A8 A9 A11 G A10 E DQ7 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 14 15 16 17 18 19 20 The TMS27C010A series are 131 072 by 8-bit (1 048 576-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). The TMS27PC010A series are 131 072 by 8-bit (1 048 576-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs). PIN NOMENCLATURE A0 – A16 DQ0 – DQ7 E G GND NC PGM VCC VPP Address Inputs Inputs (programming) / Outputs Chip Enable Output Enable Ground No Internal Connection Program 5-V Power Supply 13-V Power Supply † † Only in program mode Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 description (continued) These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs ( including program data inputs) can be driven by Series 74 TTL circuits without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external resistors. The TMS27C010A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C010A is also offered with two choices of temperature ranges, 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1. The TMS27PC010A OTP PROM is offered in a 32-pin, plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing ( FM suffix). The TMS27PC010A is offered with two choices of temperature ranges, 0°C to 70°C ( FML suffix) and – 40°C to 85°C (FME suffix). See Table 1. Table 1. Temperature Range Suffixes EPROM AND OTP PROM SUFFIX FOR OPERATING FREEAIR TEMPERATURE RANGES 0°C to 70°C – 40°C to 85°C TMS27C010A-xxx JL JE TMS27PC010A-xxx FML FME These EPROMs and OTP PROMs operate from a single 5-V supply ( in the read mode), thus are ideal for use in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals are TTL level. These devices are programmable using the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a VPP of 13 V and a VCC of 6.5 V for a nominal programming time of thirteen seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be programmed singly, in blocks, or at random. operation The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for signature mode. Table 2. Operation Modes MODE† FUNCTION READ OUTPUT DISABLE STANDBY PROGRAMMING VERIFY PROGRAM INHIBIT SIGNATURE MODE G VIL VIL VIL VIH VIH X VIL VIH VIL VIL VIH X VIL VIL PGM X X X X VCC VCC VCC VCC VCC VCC VIH VPP X VPP VCC A9 VIL VPP X X VCC X VPP VCC X VCC VCC X VCC X A0 X X X X X X VH‡ VIL DQ0 – DQ7 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z MFG DEVICE 97 D6 E VH‡ VIH CODE † X can be VIL or VIH. ‡ VH = 12 V ± 0.5 V. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 read/ output disable When the outputs of two or more TMS27C010As or TMS27PC010As are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins. latchup immunity Latchup immunity on the TMS27C010A and TMS27PC010A is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices are interfaced to industry standard TTL or MOS logic devices. The input / output layout approach controls latchup without compromising performance or packing density. power down Active ICC supply current can be reduced from 30 mA to 500 µA by applying a high TTL input on E and to 100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state. erasure (TMS27C010A) Before programmig, the TMS27C010A EPROM is erased by exposing the chip through the transparent lid to a high intensity UV light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity × exposure time) is 15-W⋅s / cm2. A typical 12-mW / cm2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. Normal ambient light contains the correct wavelength for erasure, therefore, when using the TMS27C010A, the window must be covered with an opaque label. After erasure (all bits in logic high state), logic lows are programmed into the desired locations. A programmed low can be erased only by UV light. initializing (TMS27PC010A) The one-time programmable TMS27PC010A PROM is provided with all bits in the logic high state, then logic lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased. SNAP! Pulse programming The TMS27C010A and TMS27PC010A are programmed using the TI SNAP! Pulse programming algorithm illustrated by the flowchart in Figure 1, which programs in a nominal time of thirteen seconds. Actual programming time varies as a function of the programmer used. The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs pulses per byte are provided before a failure is recognized. The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, E = VIL, G = VIH. Data is presented in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, PGM is pulsed low. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = VPP = 5 V ± 10%. program inhibit Programming can be inhibited by maintaining a high level input on the E or PGM pins. program verify Programmed bits can be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = VIH. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 Start Address = First Location VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V Program Mode Program One Pulse = tw = 100 µs Last Address? Increment Address No Yes Address = First Location X=0 Program One Pulse = tw = 100 µs No Increment Address Verify One Byte Fail X=X+1 X = 10? Interactive Mode Pass No Last Address? Yes Yes VCC = VPP = 5 V ± 0.5 V Compare All Bytes to Original Data Device Failed Fail Final Verification Pass Device Passed Figure 1. SNAP! Pulse Programming Flowchart 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must be held low. The signature code for these devices is 97D6. A0 low selects the manufacturer’s code 97 ( Hex), and A0 high selects the device code D6 (Hex), as shown in Table 3. Table 3. Signature Mode PINS IDENTIFIER† A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VIL VIH 1 0 0 1 0 1 1 1 97 DEVICE CODE 1 1 0 1 † E = G = VIL, A1 – A8 = VIL, A9 = VH, A10 – A16 = VIL, VPP = VCC. 0 1 1 0 D6 MANUFACTURER CODE HEX logic symbol‡ EPROM 131 072 × 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 E 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 0 A 24 13 14 15 17 18 19 20 21 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 16 [PWR DOWN] & G 0 131 071 A∇ A∇ A∇ A∇ A∇ A∇ A∇ A∇ EN ‡ This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. J package illustrated. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input voltage range, All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V Output voltage range, with respect to VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V Operating free-air temperature range (’27C010A-_ _JL, ’27PC010A-_ _FML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Operating free-air temperature range (’27C010A-_ _JE, ’27PC010A-_ _FME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions ’27C010A/PC010A-10 ’27C010A / PC010A-12 ’27C010A / PC010A-15 ’27C010A / PC010A-20 Read mode (see Note 2) VCC Supply y voltage SNAP! Pulse programming algorithm VPP Supply y voltage SNAP! Pulse programming algorithm Read mode (see Note 3) MIN NOM 4.5 5 5.5 V 6.25 6.5 6.75 V VCC + 0.6 13.25 V VCC – 0.6 12.75 TTL UNIT 2 VCC 13 MAX VCC + 0.5 VCC + 0.5 V VIH High level dc input voltage High-level VIL Low level dc input voltage Low-level TA Operating free-air temperature ’27C010A-_ _JL ’27PC010A-_ _FML 0 70 °C TA Operating free-air temperature ’27C010A-_ _JE ’27PC010A-_ _FME – 40 85 °C CMOS TTL CMOS VCC – 0.2 – 0.5 – 0.5 0.8 GND + 0.2 V V NOTES: 2. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. 3. During programming, VPP must be maintained at 13 V ± 0.25 V. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High level dc output voltage High-level IOH = – 20 µA IOH = – 2.5 mA VOL Low level dc output voltage Low-level IOL = 2.1 mA IOL = 20 µA 0.4 II IO Input current (leakage) VI = 0 V to 5.5 V VO = 0 V to VCC ±1 µA Output current (leakage) ±1 µA IPP1 IPP2 VPP supply current VPP supply current (during program pulse) VPP = VCC = 5.5 V VPP = 13 V 10 µA 50 mA TTL-input level ICC1 VCC supply current (standby) ICC2 VCC supply current (active) (output open) V 0.1 VCC = 5.5 V, VCC = 5.5 V, CMOS-input level VCC – 0.2 3.5 E = VIH 500 E = VCC ± 0.2 V 100 E = VIL VCC = 5.5 V, tcycle = minimum cycle time†, y outputs open 30 V µA mA † Minimum cycle time = maximum access time. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz‡ PARAMETER CI TEST CONDITIONS Input capacitance MIN VI = 0 V, f = 1 MHz VO = 0 V, f = 1 MHz CO Output capacitance ‡ Capacitance measurements are made on sample basis only. § All typical values are at TA = 25°C and nominal voltages. TYP§ MAX 4 8 pF 6 10 pF UNIT switching characteristics over recommended ranges of operating conditions (see Notes 4 and 5) PARAMETER TEST CONDITIONS ’27C010A-10 ’27PC010A-10 MIN MAX ’27C010A-12 ’27PC010A-12 MIN MAX ’27C010A-15 ’27PC010A-15 MIN MAX ’27C010A-20 ’27PC010A-20 MIN UNIT MAX ta(A) ta(E) Access time from address 100 120 150 200 ns Access time from chip enable 100 120 150 200 ns ten(G) Output enable time from G 55 55 75 75 ns tdis Output disable time from G or E, whichever occurs first¶ 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first¶ CL = 100 pF, F 1 Series 74 TTL load, Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 0 50 0 50 0 0 0 60 0 0 ns ¶ Value calculated from 0.5-V delta to measured output level. NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (see Figure 2). 5. Common test conditions apply for tdis except during programming. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 4) PARAMETER tdis(G) ten(G) Disable time, output disable time from G MIN MAX UNIT 0 130 ns 150 ns Enable time, output enable time from G NOTE 4: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (see the ac testing waveform). timing requirements for programming NOM MAX UNIT 95 100 105 µs Pulse duration, program Setup time, address 2 µs tsu(E) tsu(G) Setup time, E 2 µs Setup time, G 2 µs tsu(D) tsu(VPP) Setup time, data 2 µs Setup time, VPP 2 µs tsu(VCC) th(A) Setup time, VCC 2 µs Hold time, address 0 µs th(D) Hold time, data 2 µs 8 SNAP! Pulse programming algorithm MIN tw(PGM) tsu(A) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION 2.08 V RL = 800 Ω Output Under Test 2.4 V 0.4 V CL = 100 pF (see Note A) 2V 0.8 V 2V 0.8 V NOTES: A. CL includes probe and fixture capacitance. B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs and outputs. Figure 2. The ac Test Output Load Circuit and Waveform VIH Address Valid A0 – A16 VIL ta(A) VIH E VIL ta(E) VIH G ten(G) VIL tdis tv(A) VIH DQ0 – DQ7 Hi-Z Output Valid Hi-Z VIL Figure 3. Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 PROGRAMMING INFORMATION Verify Program A0 – A16 Address N+1 Address Stable tsu(A) DQ0 – DQ7 VIH VIL th(A) VIH / VOH Data-Out Valid Data-In Stable VIL / VOL tdis(G)† tsu(D) VPP VPP VCC tsu(VPP) VCC‡ VCC VCC tsu(VCC) VIH E VIL th(D) tsu(E) VIH PGM VIL tsu(G) tw(PGM) ten(G)† VIH G VIL † tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer. ‡ 13-V VPP and 6.5-V VCC for SNAP! Pulse programming. Figure 4. Program-Cycle Timing (SNAP! Pulse Programming) 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER Seating Plane 0.004 (0,10) 0.140 (3,56) 0.132 (3,35) 0.495 (12,57) 4 0.485 (12,32) 0.129 (3,28) 0.123 (3,12) 0.453 (11,51) 0.447 (11,35) 0.049 (1,24) 0.043 (1,09) 1 0.008 (0,20) NOM 30 29 5 0.020 (0,51) 0.015 (0,38) 0.595 (15,11) 0.585 (14,86) 0.553 (14,05) 0.547 (13,89) 0.030 (0,76) TYP 21 13 14 20 0.050 (1,27) 4040201-4 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-016 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS27C010A 131 072 BY 8-BIT UV ERASABLE TMS27PC010A 131 072 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 24 PIN SHOWN B 13 24 C 12 1 Lens Protrusion 0.010 (0,25) MAX 0.065 (1,65) 0.045 (1,14) 0.090 (2,29) 0.060 (1,53) 0.018 (0,46) MIN 0.175 (4,45) 0.140 (3,56) A Seating Plane 0°– 10° 0.125 (3,18) MIN 0.022 (0,56) 0.014 (0,36) 0.100 (2,54) A B C 28 24 PINS** NARR DIM 0.012 (0,30) 0.008 (0,20) WIDE NARR 32 WIDE NARR 40 WIDE NARR WIDE MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53) MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61) MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 4040084 / B 04/95 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated