LMX2502/LMX2512
PLLatinum™ Frequency Synthesizer System with
Integrated VCO
General Description
Features
LMX2502 and LMX2512 are highly integrated, high performance, low power frequency synthesizer systems optimized
for Korean PCS and Korean Cellular CDMA (1xRTT, IS-95)
mobile handsets. Using a proprietary digital phase locked
loop technique, LMX2502 and LMX2512 generate very
stable, low noise local oscillator signals for up and down
conversion in wireless communications devices.
n Small Size
5.0 mm X 5.0 mm X 0.75 mm 28-Pin LLP Package
n RF Synthesizer System
Integrated RF VCO
Integrated Loop Filter
Low Spurious, Low Phase Noise Fractional-N RF PLL
Based on 11-Bit Delta Sigma Modulator
10 kHz Frequency Resolution
n IF Synthesizer System
Integer-N IF PLL
Programmable Charge Pump Current Levels
Programmable Frequency
n Supports Various Reference Frequencies
19.20/19.68 MHz
n Fast Lock Time: 500 µs
n Low Current Consumption
17 mA at 2.8 V
n 2.7 V to 3.3 V Operation
n Digital Filtered Lock Detect Output
n Hardware and Software Power Down Control
LMX2502 and LMX2512 include a voltage controlled oscillator (VCO), a loop filter, and a fractional-N RF PLL based on
a delta sigma modulator. In concert these blocks form a
closed loop RF synthesizer system. LMX2502 supports the
Korean PCS band and LMX2512 supports the Korean Cellular band.
LMX2502 and LMX2512 include an Integer-N IF PLL also.
For more flexible loop filter designs, the IF PLL includes a
4-level programmable charge pump. Together with an external VCO and loop filter, LMX2502 and LMX2512 make a
complete closed loop IF synthesizer system.
Serial data is transferred to the device via a three-wire
MICROWIRE interface (DATA, LE, CLK).
Operating supply voltage ranges from 2.7 V to 3.3 V.
LMX2502 and LMX2512 feature low current consumption:
17 mA at 2.8 V.
LMX2502 and LMX2512 are available in a 28-pin leadless
leadframe package (LLP).
Applications
n Korean PCS CDMA Systems
n Korean Cellular CDMA Systems
Functional Block Diagram
20068001
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS200680
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LMX2502/LMX2512 Frequency Synthesizer System with Integrated VCO
June 2003
LMX2502/LMX2512
Connection Diagram
28-Pin LLP (LQ) Package
20068002
NOTE: Analog ground connected through exposed die attached pad.
Pin Descriptions
Pin Number
Name
I/O
Description
1
CPout
O
IF PLL charge pump output
2
NC
–
Do not connect to any node on the printed circuit board.
3
NC
–
Do not connect to any node on the printed circuit board.
4
VDD
–
Supply voltage for IF analog circuitry
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5
LE
I
MICROWIRE Latch Enable
6
CLK
I
MICROWIRE Clock
7
DATA
I
MICROWIRE Data
8
VDD
–
Supply voltage for VCO
9
NC
–
Do not connect to any node on the printed circuit board.
10
NC
–
Do not connect to any node on the printed circuit board.
11
NC
–
Do not connect to any node on the printed circuit board.
12
NC
–
Do not connect to any node on the printed circuit board.
13
VDD
–
Supply voltage for VCO
14
VDD
–
Supply voltage for VCO output buffer
15
RFout
O
Buffered VCO output
16
VCC
–
Supply voltage for RF prescaler
17
VCC
–
Supply voltage for charge pump
18
VCC
–
Supply voltage for RF digital circuitry
19
LD
O
Lock Detect
20
CE
I
Chip Enable control pin
21
GND
–
Ground for digital circuitry
22
OSCin
I
Reference frequency input
23
VCC
–
Supply voltage for reference input buffer
24
GND
–
Ground for digital circuitry
25
VCC
–
Supply voltage for IF digital circuitry
26
Fin
I
IF buffer/prescaler input
27
VCC
–
Supply voltage for IF buffer/prescaler
28
NC
–
Do not connect to any node on the printed circuit board.
2
Part Number
RF Min.
(MHz)
RF Max.
(MHz)
IF
(MHz)
Package
Marking
Supplied As
1649.62
RF Center
(MHz)
~1635
LMX2502LQX1635
1619.62
440.76
25021635
4500 units on
tape and reel
LMX2502LQ1635
1619.62
1649.62
~1635
440.76
25021635
1000 units on
tape and reel
LMX2512LQX0967
954.42
979.35
~967
170.76
25120967
4500 units on
tape and reel
LMX2512LQ0967
954.42
979.35
~967
170.76
25120967
1000 units on
tape and reel
LMX2512LQX1065
1052.64
1077.57
~1065
367.20
25121065
4500 units on
tape and reel
LMX2512LQ1065
1052.64
1077.57
~1065
367.20
25121065
1000 units on
tape and reel
Part Number Description
20068003
3
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LMX2502/LMX2512
Ordering Information
LMX2502/LMX2512
Absolute Maximum Ratings
Recommended Operating
Conditions
(Notes 1,
2, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Parameter
Symbol
Supply Voltage
VCC, VDD -0.3 to 3.6
V
Voltage on any pin
to GND
VI
V
Storage Temperature TSTG
Range
Ratings
-0. 3 to VDD+0.3
V
-65 to 150
˚C
Symbol
Min Typ Max Units
Ambient Temperature
TA
-30 25
Supply Voltage (to GND) VCC, VDD 2.7
Units
-0. 3 to VCC+0.3
Parameter
85
˚C
3.3
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
rating < 2 kV and is ESD sensitive. Handling and assembly of this device
should be done at ESD protected work stations.
Note 3: GND = 0 V.
Electrical Characteristics
Symbol
(VCC = VDD = 2.8 V, TA = 25 ˚C; unless otherwise noted)
Parameter
Condition
Min
Typ
Max
Units
ICC PARAMETERS
ICC + IDD
Total Supply Current
OB_CRL [1:0] = 00
17
19
mA
(ICC +
IDD)RF
RF PLL Total Supply Current
OB_CRL [1:0] = 00
16
18
mA
IPD
Power Down Current (Note 4)
CE = LOW or
RF_EN = 0
IF_EN = 0
20
µA
19.68
MHz
VCC
Vp-p
REFERENCE OSCILLATOR PARAMETERS
fOSCin
Reference Oscillator Input Frequency
(Note 5)
VOSCin
Reference Oscillator Input Sensitivity
19.20 MHz and 19.68
MHz are supported
19.20
0.2
RF VCO
fRFout
PRFout
Frequency Range
(Note 6)
LMX2502LQ1635
1619.62
1649.62
MHz
LMX2512LQ0967
954.42
979.35
MHz
LMX2512LQ1065
1052.64
1077.57
MHz
RF Output Power
Lock Time
(Note 7)
RF VCO
OB_CRL [1:0] = 11
-2
1
4
dBm
OB_CRL [1:0] = 10
-5
-2
1
dBm
OB_CRL [1:0] = 01
-7
-4
-1
dBm
OB_CRL [1:0] = 00
-9
-6
-3
dBm
LMX2502LQ1635
30 MHz Band for RF
PLL
500
800
µs
LMX2512LQ0967
25 MHz Band for RF
PLL
500
800
µs
LMX2512LQ1065
25 MHz Band for RF
PLL
500
800
µs
RF PLL in all band
1.3
Reference Spurs
-75
RMS Phase Error
L(f)RFout
Phase Noise
LMX2502LQ1635
LMX2512LQ0967
LMX2512LQ1065
dBc
degrees
@ 100 kHz offset
-113
-112
dBc/Hz
@ 1.25 MHz offset
-138
-136
dBc/Hz
@ 100 kHz offset
-117
-115
dBc/Hz
@ 900 kHz offset
-139
-138
dBc/Hz
@ 100 kHz offset
-117
-115
dBc/Hz
@ 900 kHz offset
-139
-138
dBc/Hz
2nd Harmonic Suppression
-25
dBc
3rd Harmonic Suppression
-20
dBc
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4
Symbol
Min
(Continued)
Parameter
Condition
Typ
Max
Units
Operating Frequency LMX2502LQ1635
(Note 8)
IF_FREQ [1:0] = 10,
Default Value
440.76
MHz
LMX2512LQ0967
IF_FREQ [1:0] = 00,
Default Value
170.76
MHz
LMX2512LQ1065
IF_FREQ [1:0] = 01,
Default Value
367.20
MHz
IF PLL
fFin
PFin
IF Input Sensitivity
fΦIF
Phase Detector Frequency
ICPout
Charge Pump Current
-10
0
dBm
120
kHz
IF_CUR [1:0] = 00
100
µA
IF_CUR [1:0] = 01
200
µA
IF_CUR [1:0] = 10
300
µA
IF_CUR [1:0] = 11
800
µA
DIGITAL INTERFACE (DATA, CLK, LE, LD, CE)
VIH
VIL
High-Level Input Voltage
Low-Level Input Voltage
0.8 VDD
VDD
V
0.8 VCC
VCC
V
0
0.2 VDD
V
0
0.2 VCC
V
IIH
High-Level Input Current
-10
10
µA
IIL
Low-Level Input Current
-10
10
µA
Input Capacitance
VOH
VOL
3
High-Level Output Voltage
pF
0.9 VDD
V
0.9 VCC
V
Low-Level Output Voltage
0.1 VDD
V
0.1 VCC
V
5
pF
Output Capacitance
MICROWIRE INTERFACE TIMING
tCS
Data to Clock Set Up Time
50
-
-
ns
tCH
Data to Clock Hold Time
10
-
-
ns
tCWH
Clock Pulse Width HIGH
50
-
-
ns
tCWL
Clock Pulse Width LOW
50
-
-
ns
tES
Clock to Latch Enable Set Up Time
50
-
-
ns
tEW
Latch Enable Pulse Width
50
-
-
ns
Note 4: In power down mode, set DATA, CLK, and LE pins to 0 V (GND).
Note 5: The reference frequency must also be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact National
Semiconductor.
Note 6: For other frequency ranges, please contact National Semiconductor.
Note 7: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/- 1 kHz
of the final frequency.
Note 8: Frequencies other that the default value can be programmed using Words R4 and R5. See Programming Description for details.
5
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LMX2502/LMX2512
Electrical Characteristics (VCC = VDD = 2.8 V, TA = 25 ˚C; unless otherwise noted)
LMX2502/LMX2512
Microwire Interface Timing Diagram
20068004
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6
GENERAL DESCRIPTION
IF_R: Preset divide ratio of the binary 9-bit programmable
reference counter (2 ≤ IF_R ≤ 511)
From the above equation, the LMX2502/12 generates the
fixed IF frequencies as summarized in Table 1.
LMX2502/12 is a highly integrated frequency synthesizer
system that generates LO signals for PCS and Cellular
CDMA applications. These devices include all the functional
blocks of a PLL, RF VCO, prescaler, RF phase detector, and
loop filter. The need for external components is limited to a
few passive elements for matching the output impedance
and bypass elements for power line stabilization.
In addition to the RF circuitry, the IC also includes IF frequency dividers, and an IF phase detector to complete the IF
synthesis with the external VCO and the loop filter. Table 1
summarizes the counter values used to generate the default
IF frequencies.
TABLE 1. IF Frequencies
Using a low spurious fractional-N synthesizer based on a
delta sigma modulator, the circuit can support 10 kHz channel spacing for PCS and Cellular CDMA systems.
Device Type
FVCO
(MHz)
IF_B
IF_A
fOSC/IF_R
(kHz)
LMX2502LQ1635
440.76
LMX2512LQ0967
170.67
229
9
120
88
15
120
LMX2512LQ1065
367.20
191
4
120
VCO FREQUENCY TUNING
The center frequency of the RF VCO is determined by the
resonant frequency of the tank circuit. This tank circuit is
implemented on-chip and requires no external inductor. The
LMX2502/12 actively tunes the tank circuit to the required
frequency with the built-in tracking algorithm.
The fractional-N synthesizer enables faster lock time, which
reduces power consumption and system set-up time. Additionally, the loop filter occupies a smaller area as opposed to
the integer-N architecture. This allows the loop filter to be
embedded into the circuit, minimizing the external noise
coupling and total form factor. The delta sigma architecture
delivers very low spurious, which can be a significant problem for other PLL solutions.
BANDWIDTH CONTROL AND FREQUENCY LOCK
During the frequency acquisition period, the loop bandwidth
is significantly extended to achieve frequency lock. Once
frequency lock occurs, the PLL will return to a steady state
condition with the loop bandwidth set to its nominal value.
The transition between acquisition and lock modes occurs
seamlessly and extremely fast, thereby, meeting the stringent requirements associated with lock time and phase
noise. Several controls (BW_DUR, BW_CRL, and BW_EN)
are used to optimize the lock time performance.
The circuit also supports commonly used reference frequencies of 19.20 MHz and 19.68 MHz.
FREQUENCY GENERATION
RF-PLL Section
The divide ratio can be calculated using the following equation:
LMX2502 – PCS CDMA:
fVCO = {8 x RF_B + RF_A + (RF_FN / fOSC) x 104} x fOSC
where (RF_A < RF_B)
LMX2512 – Cellular CDMA:
fVCO = {6 x RF_B + RF_A + (RF_FN / fOSC) x 104} x fOSC
where (RF_A < RF_B)
where
fVCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤
RF_A ≤ 7 for LMX2502 or 0 ≤ RF_A ≤ 5 for LMX2512)
RF_FN: Preset numerator of binary 11-bit modulus counter
(0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz or 0 ≤ RF_FN <
1968 for fOSC = 19.68 MHz)
fOSC: Reference oscillator frequency
SPURIOUS REDUCTION
To improve the spurious performance of the device one of
two types of spurious reduction schemes can be selected:
• A continuous optimization scheme, which tracks the environmental and voltage variations, giving the best spurious performance over changing conditions
• A one time optimization scheme, which sets the internal
compensation values only when the PLL goes into a
locked state.
The spurious reduction can also be disabled, but it is recommended that the continuous optimization mode be used for
normal operation.
POWER DOWN MODE
The LMX2502 and LMX2512 include a power down mode to
reduce the power consumption. The LMX2502/12 enters into
the power down mode either by taking the CE pin LOW or by
setting the power down bits in Register R1. Table 2 summarizes the power down function. If CE is set LOW, the circuit is
powered down regardless of the register values. When CE is
HIGH, the IF and RF circuitry are individually powered down
by setting the register bits.
IF-PLL Section
fVCO = {16 x IF_B + IF_A} x fOSC / IF_R where (IF_A < IF_B)
where
fVCO: Output frequency of the voltage controlled oscillator
(VCO)
IF_B: Preset divide ratio of the binary 9-bit programmable
counter (1 ≤ IF_B ≤ 511)
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LMX2502/LMX2512
IF_A: Preset divide ratio of the binary 4-bit swallow counter
(0 ≤ IF_A ≤ 15)
fOSC: Reference oscillator frequency
Functional Description
LMX2502/LMX2512
Functional Description
LD pin remains LOW. After obtaining phase lock, the LD pin
will have a logical HIGH level. The output can also be
programmed to be ground at all times.
(Continued)
TABLE 2. Power Down Configuration
CE Pin
RF_EN
IF_EN
RF Circuitry
IF Circuitry
0
X
X
OFF
OFF
1
0
0
OFF
OFF
LD Bit
Mode
Disable (GND)
Enable
TABLE 3. Lock Detect Modes
1
0
1
OFF
ON
0
1
1
0
ON
OFF
1
1
1
1
ON
ON
TABLE 4. Lock Detect Logic
X = Don’t care.
LOCK DETECT
The LD output can be used to indicate the lock status of the
RF PLL. Bit 21 in Register R0 determines the signal that
appears on the LD pin. When the RF PLL is not locked, the
RF PLL Section
LD Output
Locked
HIGH
Not Locked
LOW
20068005
FIGURE 1. Lock Detect Timing Diagram Waveform (Notes 9, 10, 11, 12, 13)
Note 9: LD output becomes LOW when the phase error is larger than tW2.
Note 12: tW1 and tW2 are equal to 10 ns.
Note 10: LD output becomes HIGH when the phase error is less than tW1 for
four or more consecutive cycles.
Note 13: The lock detect comparison occurs with every 64th cycle of fR and
fN.
Note 11: Phase Error is measured on leading edge. Only errors greater than
tW1 and tW2 are labeled.
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8
LMX2502/LMX2512
Functional Description
(Continued)
20068006
FIGURE 2. Lock Detect Flow Diagram
edge of the clock (CLK). The last bits decode the internal
control register address. When the latch enable (LE) transitions from LOW to HIGH, data stored in the shift registers is
loaded into the corresponding control register.
MICROWIRE INTERFACE
The programmable register set is accessed via the
MICROWIRE serial interface. The interface comprises three
signal pins: CLK, DATA, and LE (Latch Enable). Serial data
(DATA) is clocked into the 24-bit shift register on the rising
9
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GENERAL PROGRAMMING INFORMATION
The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming data is loaded into the shift
register from MSB to LSB. The data is shifted at the rising edge of the clock signal. When the latch enable signal transitions from
LOW to HIGH, the data stored in the shift register is transferred to the proper register depending on the address bit settings. The
selection of the particular register is determined by the address bits equal to the binary representation of the number of the control
register.
At initial start-up, the MICROWIRE loading requires 4 default words (registers R3, loaded first, to R0, loaded last). After the device
has been initially programmed, the RF VCO frequency can be changed using a single register (R0). If an IF frequency other than
the default value for the device is desired the SPI_DEF bit should be set to 0, the desired values for IF_A, IF_B, and IF_R entered
and words R6 to R0 should be sent.
The control register content map describes how the bits within each control register are allocated to the specific control functions.
COMPLETE REGISTER MAP
Register
LMX2502/LMX2512
Programming Description
MSB
23
SHIFT REGISTER BIT LOCATION
22
21
R0
SPI_ RF_ RF_
(Default) DEF SEL LD
20 19
0
18 17 16 15 14 13 12
RF_B
[3:0]
11
LSB
10 9 8 7 6 5
RF_A
[2:0]
4
3
2
RF_FN
[10:0]
1 0
0 0
R1
IF_
(Default) FREQ
[1:0]
OSC_ 1
FREQ
0
0
0
0
0
0
0
SPUR_
RDT
[1:0]
0
0 1 0 1 OB_
CRL
[1:0]
RF_ IF_ 0 1
EN EN
R2
IF_
(Default) CUR[1:0]
0
1
0
0
1
1
1
0
1
1
0
1 0 1 0 0
0
1
R3
BW_
(Default) DUR
[1:0]
BW_
CRL
[1:0]
BW_ 1
EN
0
1
1
1
1
0
1
0
0 0 1 1 0
VCO_
CUR
[1:0]
0
R4
0
0
0
1
0
0
0
IF_A
[3:0]
R5
0
0
1
1
0
0
0
0
1
0
R6
1
0
0
0
0
0
0
0
0
0
NOTE: Bold numbers represent the address bits.
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10
IF_B
[8:0]
0
0
0
0
1 0
0
1 1
0
1
1 1
IF_R
[8:0]
0
1
1
1 1
0
1
1
1
1 1
0 0 0 0 0
(Continued)
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The SPI_DEF bit selects between using the default IF counter values and user programmable values. The use of the default
counter values requires that only words R0 to R3 (registers R3, loaded first, to R0, loaded last) be sent after initial power up.
The RF_LD bit activates the lock detect output of the LD pin (pin 19). The lock detect mode shows the lock status of the RF PLL.
The waveform of the lock detect mode is shown in Figure 1, in the Functional Description section on LOCK DETECT.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
11-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0 REGISTER
Register
MSB
23
R0
(Default)
SPI_
DEF
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
LSB
9
8
7
6
5
4
3
Data Field
RF_
SEL
RF_
LD
0
RF_B
[3:0]
RF_A
[2:0]
1
0
Address
Field
RF_FN
[10:0]
Name
Functions
SPI_DEF
Default Register Selection
0 = OFF (Use values set in R0 to R6)
1 = ON (Use default values set in R0 to R3)
RF_SEL
RF VCO Selection
0 = LMX2512
1 = LMX2502
RF_LD
RF Lock Detect
0 = Hard zero (GND)
1 = Lock detect
RF_B [3:0]
RF_B Counter
4-bit programmable counter
2 ≤ RF_B ≤ 15
RF_A [2:0]
RF_A Counter
3-bit swallow counter
0 ≤ RF_A ≤ 7 for LMX2502
0 ≤ RF_A ≤ 5 for LMX2512
RF_FN [10:0]
RF Fractional Numerator Counter
11-bit programmable counter
0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz
0 ≤ RF_FN < 1968 for fOSC = 19.68 MHz
11
2
0
0
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LMX2502/LMX2512
Programming Description
LMX2502/LMX2512
Programming Description
(Continued)
RF N Counter Setting:
Counter Name
Symbol
Function
Modulus Counter
RF_FN
Programmable
Counter
RF_B
RF N Divider
N = Prescaler x RF_B + RF_A + (RF_FN / fOSC) x 104
Swallow Counter
RF_A
Pulse Swallow Function:
fVCO = {Prescaler x RF_B + RF_A + (RF_FN / fOSC) x 104} x fOSC where (RF_A < RF_B)
where
fVCO: Output frequency of voltage controlled oscillator (VCO)
Prescaler Values:
Device Type
RF Prescaler
LMX2502
8
LMX2512
6
RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for LMX2502, 0 ≤ RF_A ≤ 5 for LMX2512)
RF_FN: Preset numerator of binary 11-bit modulus counter (0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz; 0 ≤ RF_FN < 1968 for fOSC
= 19.68 MHz).
fOSC: Reference oscillator frequency
NOTE: For the use of reference frequencies other than those specified, please contact National Semiconductor.
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12
(Continued)
R1 REGISTER
The R1 register address bits (R1 [1:0]) are “01”.
The IF_FREQ bits selects the default IF frequency applicable to the specific CDMA system. For the LMX2502 the default IF
frequency is 440.76 MHz, and for the LMX2512 the default IF frequencies are 367.20 MHz and 170.76 MHz, depending on
variant.
Reference Frequency Selection bit (OSC_FREQ) selects either 19.20 MHz or 19.68 MHz for the reference oscillator frequency.
The internal spurious reduction scheme is controlled by the SPUR_RDT [1:0] bits. There are two different spur reduction
schemes: a continuous tracking mode and a single optimization mode. The continuous tracking mode will adjust for variations in
voltage and temperature. The single optimization mode fixes the internal compensation parameters only when the PLL goes into
the locked state. The spur reduction can also be disabled, but it is recommended that the continuous mode be used for normal
operation.
The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level can be set according to the system
requirement.
The two bits, RF_EN and IF_EN, logically select the active state of the RF synthesizer system and the IF PLL, respectively. The
entire IC can be placed in a power down state by using the CE control pin (pin 20).
R1 REGISTER
Register
MSB
23
SHIFT REGISTER BIT LOCATION
22 21
20 19 18 17 16 15 14 13 12
11
10 9 8 7 6 5
LSB
4
3
2
Data Field
R1
IF_
(Default) FREQ
[1:0]
OSC_ 1
FREQ
0
0
0
0
0
0
0
0
Address
Field
SPUR_
RDT
[1:0]
0
0 1 0 1 OB_
CRL
[1:0]
RF_ IF_ 0
EN EN
Name
Functions
IF_FREQ [1:0]
IF Frequency Selection
00 = 170.76 MHz (LMX2512LQ0967)
01 = 367.20 MHz (LMX2512LQ1065)
10 = 440.76 MHz (LMX2502LQ1635)
OSC_FREQ
Reference Frequency Selection
0 = 19.20 MHz
1 = 19.68 MHz
SPUR_RDT [1:0]
Spur Reduction Scheme
00 = No spur reduction
01 = Not Used
10 = Continuous tracking of variation (Recommended)
11 = One time optimization
OB_CRL [1:0]
RF Output Power Control
00 = Minimum Output Power
01 =
10 =
11 = Maximum Output Power
RF_EN
RF Enable
0 = RF Off
1 = RF On
IF_EN
IF Enable
0 = IF Off
1 = IF On
13
1
1
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LMX2502/LMX2512
Programming Description
(Continued)
R2 REGISTER
The R2 Register address bits (R2 [1:0]) are “10”.
The IF_CUR [1:0] bits program the IF charge-pump current. Considering the external IF VCO and loop filter, the user can select
the amount of IF charge pump current to be 100 µA, 200 µA, 300 µA or 800 µA.
R2 REGISTER
MSB
SHIFT REGISTER BIT LOCATION
Register
LMX2502/LMX2512
Programming Description
23
R2
(Default)
IF_
CUR[1:0]
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22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
4
3
2
Data Field
0
0
1
0
0
1
1
1
0
0
Address
Field
1
1
0
1
0
1
0
0
0
Name
Functions
IF_CUR [1:0]
IF Charge Pump Current
00 = 100 µA
01 = 200 µA
10 = 300 µA
11 = 800 µA
14
1
1
0
1
0
(Continued)
R3 REGISTER
The R3 register address bits (R3 [2:0]) are “011”.
Register R3 contains the controls for the phase lock bandwidth controls (BW_DUR, BW_CRL, and BW_EN). The duration of the
digital controller portion of the bandwidth control is set by BW_DUR [1:0]. The minimum time set with 00 and increasing durations
to the maximum value set with 11. BW_CRL [1:0] sets the phase offset criterion for the bandwidth controller. Once the phase
offset between the reference clock and the divided VCO signal are within the set criterion, the bandwidth control stops. The
maximum phase offset is set with 00 and decreases to the minimum value set with 11. BW_EN enables the bandwidth control in
the locking state.
The VCO dynamic current is also controlled in register R3 with VCO_CUR [1:0]. The minimum value corresponds to 00 and
increases to a maximum value set at 11.
R3 REGISTER
Register
MSB
23
R3
(Default)
BW_
DUR
[1:0]
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
4
3
2
Data Field
BW_
CRL
[1:0]
BW_
EN
1
0
1
1
1
1
0
1
0
0
0
1
1
0
VCO_
CUR
[1:0]
Name
Functions
BW_DUR [1:0]
Bandwidth Duration
00 = Minimum value (Recommended)
01 =
10 =
11 = Maximum value
BW_CRL [1:0]
Bandwidth Control
00 = Maximum phase offset (Recommended)
01 =
10 =
11 = Minimum phase offset
BW_EN
Bandwidth Enable
0 = Disable
1 = Enable (Recommended)
VCO_CUR [1:0]
VCO Dynamic Current
00 = Minimum value
01 =
10 =
11 = Maximum value (Recommended)
15
1
0
Address
Field
0
1
1
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LMX2502/LMX2512
Programming Description
(Continued)
R4 REGISTER
The R4 register address bits (R3 [3:0]) are “0111”.
Register R4 is used to set the IF N counters if the default value is not desired. This register is only active if the SPI_DEF bit in
register R0 is 0.
R4 REGISTER
MSB
Register
LMX2502/LMX2512
Programming Description
23
R4
0
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
LSB
9
8
7
6
5
4
3
Data Field
0
0
1
0
0
0
1
0
Address
Field
IF_A
[3:0]
IF_B
[8:0]
Name
Functions
IF_A [3:0]
IF A Counter
4-bit swallow counter
0 ≤ IF_A ≤ 15
IF_B [8:0]
IF B Counter
9-bit programmable counter
1 ≤ IF_B ≤ 511
IF Frequency Setting:
fVCO = {16 x IF_B + IF_A} x fOSC / IF_R where (IF_A < IF_B)
where
fVCO: Output frequency of IF voltage controlled oscillator (IF VCO)
IF_B: Preset divide ratio of binary 9-bit programmable counter (1 ≤ IF_B ≤ 511)
IF_A: Preset divide ratio of binary 4-bit swallow counter (0 ≤ IF_A ≤ 15)
IF_R: Preset divide ratio of binary 9-bit programmable reference counter (2 ≤ IF_R ≤ 511)
fOSC: Reference oscillator frequency
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2
16
0
1
1
1
(Continued)
R5 REGISTER
The R5 register address bits (R5 [4:0]) are “01111”.
Register R5 is used to set the IF_R divider if the default value is not desired. This register is only active if the SPI_DEF bit in
register R0 is 0.
R5 REGISTER
Register
MSB
23
R5
0
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
4
3
Data Field
0
1
1
0
0
0
0
1
2
1
0
Address
Field
0
IF_R
[8:0]
0
Name
Functions
IF_R [8:0]
IF R Counter
9-bit programmable counter
2 ≤ IF_R ≤ 511
1
1
1
1
R6 REGISTER
The R6 register address bits (R6 [5:0]) are “011111”.
Register R6 is used for internal testing of the device and is not intended for customer use. This register is only active if the
SPI_DEF bit in register R0 is 0.
Register
R6 REGISTER
MSB
23
22
21
20
19
18
17
16
SHIFT REGISTER BIT LOCATION
R6
1
0
0
0
0
0
0
0
15
14
LSB
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
1
Data Field
0
0
3
2
1
0
Address Field
17
1
1
1
1
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LMX2502/LMX2512
Programming Description
LMX2502/LMX2512 Frequency Synthesizer System with Integrated VCO
Physical Dimensions
inches (millimeters) unless otherwise noted
Leadless Leadframe Package (LLP)
NS Package Number LQA28A
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