UC1638 UC2638 UC3638 Advanced PWM Motor Controller FEATURES DESCRIPTION • Single or Dual Supply Operation • Accurate High Speed Oscillator • Differential X5 Current Sense Amplifier • Bidirectional Pulse-by-Pulse Current Limiting The UC1638 family of integrated circuits are advanced pulse width modulators intended for a variety of PWM motor drive and amplifier applications requiring either uni-directional or bi-directional drive circuits. Similar in architecture to the UC1637, all necessary circuitry is included to generate an analog error signal and modulate two bi-directional pulse train outputs in proportion to the error signal magnitude and polarity. • Programmable Oscillator Amplitude and PWM Deadband • Dual 500mA Totem Pole Output Drivers • Dual 60V, 50mA Open Collector Drivers • Undervoltage Lockout Key features of the UC1638 include a programmable high speed triangle oscillator, a 5X differential current sensing amplifier, a high slew rate error amplifier, high speed PWM comparators, and two 50mA open collector as well as two ±500mA totem pole output stages. The individual circuit blocks are designed to provide practical operation to switching frequencies of 500kHz. Significant improvements in circuit speed, elimination of many external programming components, and the inclusion of a differential current sense amplifier, allow this controller to be specified for higher performance applications, yet maintain the flexibility of the UC1637. The current sense amplifier in conjunction with the error amplifier can be configured for average current feedback. The additional open collector outputs provide a drive signal continued BLOCK DIAGRAM UDG-95048-4 1/98 UC1638 UC2638 UC3638 DESCRIPTION (cont.) ABSOLUTE MAXIMUM RATINGS for the highside switches in a full bridge configuration. The programmable AREFIN pin allows for single or dual supply operation. Oscillator ramp amplitude and PWM deadband are programmable by tapping a voltage divider off the 5V reference to the appropriate programming input (PVSET or DB). Supply Voltage VCC (referenced to VEE) . . . . . . . . . . . . . 40V Output Drivers (AOUT2, BOUT2) Currents (continuous) . . . . . . . . . . . . . . . . . . . . . . . . ±0.25A Currents (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500mA REF Output Current . . . . . . . . . . . . . . . . . . . . Internally Limited PVSET, DB, RT, INV, REF, CSOUT . . . . . . . . . . . . . 0.3 to 10V CS+, CS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE–1V to VCC CT, AREF, AREFIN, COMP, SD . . . . . . . . . . . . . . . . VEE − 0.3 Output Voltage (AOUT1, BOUT1) . . . . . . . . . . . . . . . . . . . . 60V Storage temperature . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . +300°C Currents are positive into, negative out of the specified terminal. Consult packaging section of data book for thermal limitation considerations of packages. Additional features include a precision externally available 5V reference, undervoltage lockout, pulse-by-pulse peak current limiting, and a remote shutdown port. The UC1638 family is available in the 20 pin N, DW and J packages. Consult the factory for other packaging options. CONNECTION DIAGRAMS DIL-20 (Top View) N or J Package SOIC-20 (Top View) DW Package PLCC-20 (Top View) Q Package 2 UC1638 UC2638 UC3638 ELECTRICAL CHARACTERISTICS Unless otherwise specified; VCC = 15V, VEE =–15V, CT = 680pF, RT = 3k, VPVSET = 1.5V, VCOMP = 0V, VCSOUT = 0V, VDB = REF, VEXTREF = 0V, VSD = VCC – 3V, TA = −55°C to 125°C for the UC1638, −25°C to 85°C for the UC2638, 0°C to 70°C for the UC3638. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Overall Supply Current, Operating 15 23 mA UVLO Threshold Reference to VEE 9 10 V UVLO Hysteresis Reference to VEE 1 V Voltage Amplifier Input Offset Voltage COMP = 0V −15 COMP = −5V to +5V VSENSE Bias Current Open Loop Gain 0 15 mV 0 0.5 2 mA 75 100 dB CMRR VCM = −5V to +5V 70 100 dB PSRR VCM = 0V, VCC − VEE = 10V to 36V 70 90 dB VOUT High INV = −0.1V, RL = 10k 13 VOUT Low Slew Rate Rising and Falling INV = +0.1V, RL = 10k Overdrive = ±1V 12 V/µs Output Source Current COMP Shorted to VEE 5 15 mA Output Sink Current COMP Shorted to VCC 15 40 mA Gain Bandwidth Product FIN = 100kHz, 10mV p-p 1 5 MHz Output Voltage IREF = −1mA, TA = 25°C 4.925 5 5.075 V Output Voltage IREF = −1mA 4.875 5 5.125 V 13.6 −13.8 V –13 V 5V Reference Load Regulation IREF = −1mA to −10mA −15 2 15 mV Line Regulation VCC - VEE = 10V to 36V −15 2 15 mV Short Circuit Current VREF = 0V 15 70 Initial Accuracy TA = 0°C – 70°C 86 98 Voltage Stability VCC − VEE = 10V to 36V Total Variation Line, Temperature mA Oscillator 110 2 76 PVSET Input Bias Current kHz % 98 120 kHz 0.5 3 µA PVSET Input Voltage Range (Note 1) 0.5 VREF V Amplitude Limit (Note 1) VEE+3 VCC−3 V AOUT1, BOUT1 Output Drivers Output Low Voltage Leakage Current IOUT = 1mA, Ref. to PVE, PVE = 0V 0.9 1.3 V IOUT = 50mA 1.2 1.8 V Output Voltage = 50V 0.1 50 µA AOUT2, BOUT2 Output Drivers Output High Voltage IOUT = −20mA, Ref. to PVE, PVE = 0V 12.2 13.5 V IOUT = −100mA, Ref. to PVE, PVE = 0V 12 13.5 V Output High Clamp Level IOUT = −20mA, Ref. to PVE, PVE = VEE 14.4 16.5 V Output Low Voltage IOUT = 20mA, Ref. to PVE, PVE = 0V 0.4 1 V IOUT = 100mA, Ref. to PVE, PVE = 0V 0.6 2.2 V Output Rise Time COUT = 1nF 50 100 ns Output Fall Time COUT = 1nF 50 100 ns 3 UC1638 UC2638 UC3638 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified; VCC = 15V, VEE =–15V, CT = 680pF, RT = 3k, VPVSET = 1.5V, VCOMP = 0V, VCSOUT = 0V, VDB = REF, VEXTREF = 0V, VSD = VCC – 3V, TA = −55°C to 125°C for the UC1638, −25°C to 85°C for the UC2638, 0°C to 70°C for the UC3638. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.75 5 5.25 V/V 50 65 −3dB Bandwidth 300 400 kHz Slew Rate Rising .75 1.5 V/µs Slew Rate Falling .75 1.5 V/µs − 1.9 − 2.25 − 2.5 V −0.5 −10 µA X5 Amplifier Gain Common Mode Rejection VID = 100mV to 400mV VCS+, VCS− = AREF ±5V dB Shutdown Threshold Ref. to VCC Input Bias Current VSD = SD Threshold Current Limit Threshold Positive Measured Between CS+ and CS- 400 500 600 mV Threshold Negative Measured Between CS+ and CS- – 600 − 500 – 400 mV Propagation Delay to Outputs Overdrive = 200mV 150 250 ns Maximum Deadband VDB = 0V ±5 V Zero Deadband VDB = REF V Deadband Adjustment Gain VDB = 1V to 4V (Note 2) 0 ±1 ± 1.2 V/V Input Bias Current VDB = VREF 3 15 µA 0.5 0.51 V/V 30 100 mV Deadband Adjust ± 0.9 AREF Buffer Gain AREF / VCC − VEE Offset (Note 3) 0.49 Note 1: Oscillator triangle amplitude = 2.5 • PV ±AREF. Note 2: Deadband = ±(REF − DB), referenced to COMP. Note 3: Offset = AREFIN − AREF. PIN DESCRIPTIONS AOUT1, BOUT1: AOUT1 and BOUT1 are open collector output drivers capable of sinking 50mA. These outputs can be pulled up to 60V maximum. With a few external components, these outputs can drive the opposite high side switches in a full bridge arrangement. AOUT2, BOUT2: AOUT2 and BOUT2 are totem pole output drivers capable of driving external power MOSFETs directly. The peak current ratings are ±500mA. An integrated zener clamp limits the drive output amplitude to approximately 14V to prevent MOSFET gate oxide overstress. These outputs are configured to drive the opposite low side switches in a full bridge arrangement. AREF: The voltage on AREF is simply a buffered version of the voltage on AREFIN. In single supply applications, AREF should be bypassed to VEE with a 0.1µF ceramic capacitor to provide a stable reference level for the internal circuitry. AREFIN: The voltage on AREFIN is generated internally by a 50% voltage divider tied between VCC and VEE. As such, it provides the mid supply reference needed for the oscillator, voltage amplifier, current amplifier and current limit comparators when operating in single supply mode. A buffer amplifier is connected between AREFIN and AREF. In bipolar supply applications AREFIN is usually connected to VEE, which disables the buffer amplifier, and AREF is connected to 0V. COMP: This is the output of the high slew rate error amplifier. The level on COMP modulates the controller duty cycle via the PWM comparators and the oscillator ramp. Compensation and DC gain setting resistors are connected between COMP and INV. CS-: This is the inverting input to the X5 current sense amplifier. The common mode input range for this pin extends from VEE−1V to VCC−4V. A low value resistor in 4 UC1638 UC2638 UC3638 PIN DESCRIPTIONS (cont.) series with the source or emitter of the low side switch in the full bridge develops the signal that is applied to this pin. At differential inputs of ±500mV typical (referenced to CS+)the controller reaches the current limit level, which truncates the output pulse. CS+: This is the non-inverting input to the X5 current sense amplifier. The common mode input range for this pin extends from VEE−1V to VCC−4V. The characteristics for this pin are identical to CS-. CSOUT: This is the output of the X5 current sense amplifier. Voltage levels greater than ±2.5V referenced to AREF will cause the device to enter current limit. An internal 100 ohm resistor between the amplifier output and CSOUT is provided to create a high frequency noise filter with an external capacitor to VEE. When used for average current feedback, CSOUT is summed into INV. CT: A capacitor from CT to VEE will set the triangle oscillator frequency according to the following equation: F= 1 5 • RT • CT The waveform on CT is symmetrical about the voltage on AREF and is applied internally to the inputs of hte PWM comparators. Use a high quality ceramic capacitor with low ESL and ESR for best results. A minimum CT value of 200 pF insures good accuracy and less susceptibility to circuit layout parasitics. The oscilator and PWM are designed to provide practical operation to 500kHz. DB: This high impedance input programs output pulse train deadtime. A stable DC voltage between 0V and REF will set a bi-directional deadband centered about the level on COMP. The deadband level is equal to: 5V − VDB. That is, 1V on DB will program ±4V of deadband centered about the COMP pin level. A convenient method for generating the programming level is a voltage divider tap off of REF. INV: This is the inverting input to the Voltage amplifier. The common mode input range for this pin extends from VEE+2V to VCC−1V. It can be tied to a command signal generated by a rate feedback element or to a position control signal. In average current feedback applications, this input is tied to the output of the X5 current sensing amplifier (CSOUT). PVE: This is the high current ground for the IC. The external MOSFET driver transistors are referenced to this ground. Internal level shifting circuitry gives the option of tying this pin to VEE, or the system ground in split supply applications. PVSET: A DC voltage on PVSET programs the upper and lower thresholds for the oscillator by the following relationship: VPK − VVLY = 5 • VPVSET. The input voltage range on PVSET is 0.5V to REF. REF: REF is the output of the precision reference. The output is capable of supplying 15mA to peripheral circuitry and is internally short circuit current limited. Bypass REF to VEE with a 0.1µF ceramic capacitor for best performance. RT: A single resistor from RT to VEE sets the charging and discharging currents for the triangle oscillator. The actual charge and discharge is 2X the current programmed by RT and PVSET. For best performance the current out of RT should be limited to 1mA. The voltage level on the RT pin is a buffered version of the PVSET pin voltage. Therefore, if the PVSET voltage divider is tied between VCC and VEE to incorporate line feedforward, the triangle waveform frequency will remain constant. SD: A voltage on SD within 2.5V (typical) of VCC will cause the UC3638 to enter a UVLO condition which disables all of the driver outputs. With an external voltage divider across VCC and VEE, and a capacitor between SD and VCC, a delayed turn-on characteristic can be generated. Since the 2.5V threshold is temperature stabilized it can also be used as a higher UVLO threshold for applications which require a starting voltage higher than the internal 9V UVLO threshold. VEE: All voltages are measured with respect to this pin. All bypass capacitors and timing components except those listed under the PVE section should be connected to this pin. Component leads should be as short and direct as possible. VEE is generally connected to the most negative voltage supply in the system. In single supply applications, VEE is tied to the system ground. VCC: Positive supply rail for the IC. Bypass this pin to VEE and PVE with 0.1 to 1µF low ESL, ESR ceramic capacitor(s). The maximum voltage for VCC is 40V referenced to VEE. The turn on voltage level on VCC is 9V with 1V of hysteresis. 5 UC1638 UC2638 UC3638 APPLICATION INFORMATION UDG-95049-2 Figure 1. Average Motor Current Control Loop The UC3638 is designed to provide pulse width modulation control of DC brush motors in applications requiring precision torque, velocity, or position control. Due to its high frequency capability, other high power applications such as switch mode audio amplifiers can also be addressed. Through a combination of circuit sophistication and integration, the designer can maintain a high level of flexibility, while reducing cost compared to solutions using other PWM ICs. sults in a voltage null point of zero volts. For this condition, AREFIN should be tied to the negative voltage supply rail (VEE), which disables the internal voltage buffer, allowing AREF to be tied to ground. For a single supply system, AREFIN should be left open circuit, and AREF should be decoupled to VEE (system ground) with at least 0.1µF. The resulting voltage null point for this case Figure 1 shows a typical application circuit for the UC3638. By taking advantage of the UC3638's many integrated functions, a low cost and compact average current mode motor controller can be designed. Depending on the level of complexity, as many as 15 discrete components and an additional high bandwidth amplifier can be saved compared to a similar circuit using the UC3637 PWM controller. Oscillator Section and Modulation Scheme Figure 2 depicts the UC3638 oscillator and PWM waveforms for the condition where the output of the voltage amplifier (COMP) is at the null point (same voltage as AREF). For applications using split voltage supply rails, AREF will normally be tied to system ground. This re- UDG-95068-1 Figure 2. Oscillator and PWM Waveforms 6 UC1638 UC2638 UC3638 APPLICATION INFORMATION (cont.) will be half way between ground and VCC, and will automatically track changes in VCC. For cases where a different null point is desired, AREF can be tied to any voltage between VEE + 2V and VCC − 2V. Of course the user must also allow sufficient headroom for the triangle waveform. Once the system null point has been chosen, the triangle wave amplitude and PWM deadband must be programmed. The amplitude of the triangle wave is determined by trading off noise immunity and gain requirements. In general, the larger the triangle wave amplitude, the greater the immunity to premature termination of PWM pulses due to switching noise. However, high amplitude triangle waves require a greater voltage swing at the output of the voltage amplifier which ultimately reduces forward loop gain. Programming the PWM deadband allows the user to trade off gain linearity requirements with power amplifier efficiency. If the modulator is configured as in Figure 1, motor current is alternately pulsed by diagonally opposite drive FETs when the servo loop is at null. By adjusting the deadband, the user can program the offset voltage at the input of the PWM comparators. This offset results in deadtime, or time when neither PWM signal is active. A minimum amount of deadtime is always recommended to provide cross conduction protection at the power amplifier. Setting the deadtime to this minimum level will provide the maximum motor stiffness or holding torque, at the expense of power losses in the output stage. These losses result from the fact that the power amplifier is always sourcing motor current, even at null. As deadtime is increased, amplifier losses at null become less, at the expense of nonlinearity in the gain function. Eventually, if the deadband voltage is increased to equal the amplitude of the triangle wave, error voltages at the null point will result in no PWM pulsing, or a dead zone. After the triangle waveform amplitude and deadband are selected, the operating frequency is easily set by proper selection of CT and RT. Referring to Figure 1, if the voltage supply rails are ±15V, and the desired triangle wave oscillator amplitude is 6V p-p, PVSET is set by: VPK − VVLY = 5 • VPVSET 6 VPVSET = = 1.2V 5 If 1V of deadband is chosen: 5 − VDB = 1V VDB = 4V In order to select the programming resistors, a source current for the reference is first selected. For a 1mA source current: 5 5 = 5k = ISOURCE 1mA 5 - VDB 1V R3 = = 1k = ISOURCE 1mA VDB - VPVSET 4V - 1.2V = 2.8k R4 = = ISOURCE 1mA R5 = 5k − 1k − 2.8k = 1.2k R3 + R4 + R5 = All of the voltages described by these equations are referenced to the negative supply rail. In other words, for a split supply system, VREF is actually a negative voltage referenced to ground. The oscillator frequency is programmed by proper selection of RT and CT. If 220pF is chosen for CT, and an operating frequency of 30kHz is desired, RT is chosen by: F= 1 5 • RT • CT 30kHz = 1 5 • 220pF • RT RT = 30k With RT = 30k, the charge current out of the RT pin is limited to 1.2V = 40µA, 30k which is well within the specified maximum of 1mA. To calculate the actual deadtime or minimum time between PWM pulses (TDB), the ratio of the deadband voltage to the triangle wave amplitude is multiplied by half the oscillator period: DB 1 • VPK - VVLY f 5 - VDB = • (5 • RT • CT) 5 • VPVSET (5 - VDB) • RT • CT = VPVSET TDB = For this example the deadtime is: TDB = 1 • 30k • 220pF = 5.5µsec 1.2 If voltage feedforward is desired, PVSET should be derived off of the supply rails instead of VREF. This way changes in the supply voltage will linearly regulate the modulator gain, which decreases control loop susceptibility to line voltage variations. Since the voltage on the RT pin is a buffered version of PVSET, charge current tracks oscillator amplitude, and therefore the frequency 7 UC1638 UC2638 UC3638 APPLICATION INFORMATION (cont.) remains constant, preventing low frequency oscillator modulation in the presence of line voltage changes. Output Drivers The output driver section provides separate output drivers for high and low side drive of both PWM signals. For many applications, the 500mA peak output current capability of the low side drivers (AOUT2 and BOUT2) is sufficient to directly connect to the appropriate low side MOSFETs of the H-bridge. A current limiting gate resistor may be used to control switching time if high levels of dv/dt or di/dt are expected at the drains of the MOSFETs. If more current drive capability is required, the PWM drive signals can be buffered with bipolar transistors. The open collector high side drivers (AOUT1 and BOUT1) are designed to control high side P-channel MOSFETs. Depending on voltage and speed requirements, the driver stage can be simplified from the one shown on Figure 1. If high side N-channel MOSFETs are desired, a boot strap or charge pump based drive circuit can be used as long as 100% duty cycle operation is not required. Average Current Control The UC3638 incorporates all of the necessary features for precise average current loop control of a DC motor. In the circuit shown in Figure 1, motor current is sensed differentially across two current sense resistors.By using two current sense resistors both the current sourced from the motor voltage supply (Vm) and the flyback current are sensed in the correct polarity to provide true torque control. If only one current sensed resistor is used, the flyback current will circulate through the body diodes of the lower MOSFETs and bypass the current sense resistor. The result will be a duty cycle dependent error term in the loop torque control function. In order to prevent high frequency spikes from contributing excessive error to the current control loop, the switching speed of the MOSFETs must be controlled so that significant transient current spikes do not couple across the drain to source capacitance of the MOSFETs. The X5 current amplifier multiplies the current signal by a factor of 5 and feeds the average current signal into the error amplifier. A window comparator detects if the peak current signal at the output of the current amplifier has a magnitude greater than 2.5V in either polarity and provides pulse-by-pulse peak current limiting. The loop should be designed so that peak motor current never reaches this level during normal operation. With integral compensation, the average current loop will have very high DC gain, resulting in effectively no average DC motor current error. For stability purposes, the high frequency gain of the voltage error amplifier must be designed such that magnitude of the slope of the error amplifier output (COMP) must be less than or equal to the magnitude of the slope of the triangle waveform. If RS1 = RS2 = RS, the DC gain of the current control loop can be calculated as: IMOTOR RG2 = ICMD 5 • RG1 • RS If the UC3638 is set up in a simple velocity or position control loop, the feedback voltage (speed or position) is summed directly into the voltage error amplifier, and the current sense amplifier is only used for peak current limit control. The motor can also be replaced by another high power device, such as an audio speaker, and the same type of amplifier can be used. In the case of audio however, a higher switching frequency will probably be desired to prevent switching noise from infiltrating the audio frequency range. UVLO and Shutdown The UC3638 contains undervoltage lockout (UVLO) circuitry to prevent unwanted bridge turn-on before sufficient supply voltage is available. The open collector drivers (AOUT1 and BOUT1) are held off (no sink current) and the totem pole drivers (AOUT 2 and BOUT2) are pulled low until the voltage between VCC and VEE reaches 9V typical. The UVLO circuitry becomes active at approximately 1V, and before this level the totem pole drivers are held low with passive pull down resistors. The shutdown pin holds the output drivers in their inactive state unless it is pulled 2.5V below VCC. An open collector gate or transistor can be used as an external enable signal, or a turn-on voltage higher than UVLO can be programmed with a resistive divider. In the case of Figure 1, the turn on voltage VSTART can be calculated as: VSTART = 2.5 • (R1+ R2) R1 If a delayed start is desired, a capacitor can be placed in parallel with R1 to slow down the change in voltage at the shutdown pin, and thus provide a user programmable startup time. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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