TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 SYNCHRONOUS BUCK CONTROLLER WITH 4-BIT VID INTERFACE FOR SMART-REFLEX™ DSPs FEATURES CONTENTS 1 • • • 2 • • • • • • • • • Input Voltage Range: 4.5 V to 14 V 4-Bit Dynamic VID-On-The-Fly Support VID Programmable Output Voltage with Programmable Transition Rate Fixed Switching Frequency of 520 kHz Selectable Low-Side (Three Settings) and Fixed High-Side Thermally Compensated Overcurrent Protection Power Good Indicator Internal 5-V Regulator Voltage Mode Control Internally Fixed 5.5-ms Soft-Start Time Pre-Bias Output Safe Thermal Shutdown at 140°C 16-Pin QFN Package 2 Electrical Characteristics 4 Typical Characteristics 6 Device Information 10 Application Information 12 Design Example 18 Additional References 20 DESCRIPTION The TPS40197 is a synchronous buck controller that operates from 4.5 V to 14 V input supply nominally. The controller implements voltage-mode control architecture with the switching frequency fixed at 520 kHz. The higher switching frequency facilitates the use of smaller inductor and output capacitors, thereby providing a compact power-supply solution. An adaptive anti-cross conduction scheme is used to prevent shoot through current in the power FETs. APPLICATIONS • • • Device Ratings The TPS40197 integrates the PWM control and 4-bit VID interface in a single chip to allow seamless onthe-fly VID changes with programmable transition rate. It provides a simple power solution for SmartReflex™ DSP cores. Smart-Reflex™ DSPs POL Modules Telecom TYPICAL APPLICATION CIRCUIT VID3 VID2 VID1 1 16 VID0 VID1 VID2 2 VID0 VID3 15 3 REF HDRV 14 4 EN VIN HOST 5 SW 13 TPS40197 FB BOOT 12 6 COMP SD VOUT VOUT 7 VIN VDD LDRV 11 BP 10 PGOOD GND 8 9 UDG-08100 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SMART-REFLEX, Smart-Reflex, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION CONTINUED Short circuit detection is done by sensing the voltage drop across the low-side FET when it is on and comparing it with a user selected threshold of 100 mV, 200 mV or 280 mV. The threshold is set with a single external resistor connected from COMP to GND. This resistor is sensed at startup and the selected threshold is latched. Pulse by pulse limiting (to prevent current runaway) is provided by sensing the voltage across the high-side FET when it is on and terminating the cycle when the voltage drop rises above a fixed threshold of 550 mV. When the controller senses an output short circuit, both FETs are turned off and a timeout period is observed before attempting to restart. This provides limited power dissipation in the event of a sustained fault. ORDERING INFORMATION (1) (1) 2 TA PACKAGE –40°C to 85°C Plastic Quad Flatpack ORDERING PART NUMBER TPS40197RGYT TPS40197RGYR PINS 16 OUTPUT SUPPLY MINIMUM ORDER QUANTITY Tube 250 Tape-and-Reel 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE VDD, EN –0.3 to 20 SW Input voltage range –5 to 25 BOOT, HDRV –0.3 to 30 BOOT–SW, HDRV–SW –0.3 to 6 FB, BP, LDRV, PGOOD, REF Output voltage range UNIT V –0.3 to 6 COMP –0.3 to 3.5 VID0, VID1, VID2, VID3 V –0.3 to 2 Operating junction temperature range, TJ –40 to150 °C Storage temperature, Tst –55 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Supply voltage VDD Operating junction temperature, TJ MAX UNIT 4.5 14 V –40 125 °C PACKAGE DISSIPATION RATINGS PACKAGE 16-Pin Plastic Quad Flatpack (RGY) (1) AIRFLOW (LFM) RθJA High-K Board (1) (°C/W) Power Rating (W) TA = 25°C Power Rating (W) TA = 85°C 0 (Natural Convection) 49.2 2.0 0.81 200 41.2 2.4 0.97 400 37.7 2.6 1.00 Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief SZZA017. ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN TYP Human body model (HBM) 2500 Charge device model (CDM) 1500 Copyright © 2008–2012, Texas Instruments Incorporated MAX UNIT V 3 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ 85°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE AND VID 0.9 V ≤ VVID ≤ 1.2 V, 0°C ≤ TJ ≤ 85°C –0.5% 0.5% 0.9 V ≤ VVID ≤ 1.2 V, –40°C ≤ TJ ≤ 85°C –1.0% 1.0% VFB FB input voltage VVID IVID VID pull-up current 50 80 120 μA VVID VID pull-up voltage 1.60 1.68 1.78 V tANTI-SKEW (1) Anti-skew filtering time 300 550 750 ns VVIDH VID high-level input voltage 0.8 1.0 1.3 V VVIDL VID low-level input voltage 0.30 0.55 0.70 V IREF REF source/sink current 400 650 850 μA 14.0 V INPUT SUPPLY VVDD Normal input supply voltage range IVDD Operating current 4.5 VENABLE = 3 V 2.5 4.5 mA VENABLE = 0.6 V 45 70 μA 7.0 SOFT-START tSS Soft-start time 3.3 5.5 tSSDLY Soft-start delay time 1.3 2.3 4.0 tREG Time to regulation 5.0 8.0 11.0 5.1 5.3 5.5 V 350 550 mV ms ON-BOARD REGULATOR VBP Output voltage VVDD > 6 V, IBP ≤ 10 mA VDO Regulator dropout voltage (VVDD–VBP) VVDD >5 V, IBP ≤ 25 mA ISC Regulator current limit threshold IBP Average current 50 50 mA OSCILLATOR fSW Switching frequency (1) VRAMP 420 Ramp amplitude 520 600 1 kHz V PWM DMAX (1) tON(min) (1) tDEAD Maximum duty cycle 85% Minimum controllable pulse Output driver dead time 110 HDRV off to LDRV on 50 LDRV off to HDRV on 25 ns ERROR AMPLIFIER GBWP AOL (1) (1) Gain bandwidth product 7 Open loop gain 10 MHz 60 IIB Input bias current (current out of FB pin) IEAOP Output source current VFB = 0 V 1 IEAOM Output sink current VFB = 2 V 1 dB 100 nA mA UNDERVOLTAGE LOCKOUT VUVLO Turn-on voltage 3.9 4.2 4.4 UVLOHYST Hysteresis 700 850 1000 1.9 3.0 V mV SHUTDOWN VIH High-level input voltage, ENABLE VIL Low-level input voltage, ENABLE (1) 4 0.6 1.2 V Specified by design. Not production tested. Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 85°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVERS RHDHI High-side driver pull-up resistance (VBOOT – VSW ) - 4.5 V, IHDR V = – 100 mA 3.0 6.0 RHDLO High-side driver pull-down resistance (VBOOT – VSW ) - 4.5 V, IHDR V = 100 mA 1.5 3.0 RLDHI Low-side driver pull-up resistance ILDR V = –100 mA 2.5 5.0 RLDLO Low-side driver pull-down resistance V = 100 mA 0.8 1.5 ILDR tHRISE (2) High-side driver rise time 15 35 tHFALL (2) High-side driver fall time 10 25 tLRISE (2) Low-side driver rise time 15 35 tLFALL (2) Low-side driver fall time 10 25 CLOAD = 1 nF Ω ns SHORT CIRCUIT PROTECTION tPSS(min) (2) Minimum pulse time during short circuit 250 ns Switch leading-edge blanking pulse time 60 90 tOFF Off-time between restart attempts 30 50 RCOMP(GND) = OPEN, TJ = 25°C Short circuit comparator threshold RCOMP(GND) = 4 kΩ, TJ = 25°C voltage RCOMP(GND) = 12 kΩ, TJ = 25°C 160 200 240 VILIM 80 100 120 228 280 342 400 550 650 106% 110% 114% 86% 90% 94% 10 30 70 (2) tBLNK Short circuit threshold voltage on high-side MOSFET VILIMH TJ = 25°C 120 ms mV POWER GOOD VOV VUV Feedback voltage limit for powergood VPG_HYST Powergood hysteresis voltage at FB pin RPGD Pull-down resistance of PGD pin VFB < 90% VVID mV or VFB > 110% VVID 7 50 Ω IPDGLK Leakage current 90% VVID ≤ VFB ≤ 100% VVID, VPGOOD = 5 V 7 12 μA 0.8 1.2 V VID mV BOOT DIODE VDFWD IBOOT = 5 mA 0.5 THERMAL SHUTDOWN TJSD (2) TJSDH (2) (2) Junction shutdown temperature Hysteresis 140 20 °C Specified by design. Not production tested. Copyright © 2008–2012, Texas Instruments Incorporated 5 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS RELATIVE OSCLLATOR FREQUENCY vs JUNCTION TEMPERATURE RELATIVE REFERENCE VOLTAGE CHANGE vs JUNCTION TEMPERATURE 0.05 VFB – Relative Reference Voltage Change – % fSW – Relative Oscillator Frequency Change – % 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -40 -25 -10 5 20 35 50 65 80 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -40 -25 -10 95 110 125 TJ – Junction Temperature – °C 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 1. Figure 2. SHUTDOWN CURRENT vs JUNCTION TEMPERATURE ENABLE THRESHOLD vs JUNCTION TEMPERATURE 2.5 60 Turn On 2.0 VEN– Enable Threshold – V IVDD – Shutdown Current – mA 50 40 30 20 10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 3. 6 1.5 1.0 Turn Off 0.5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 4. Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 TYPICAL CHARACTERISTICS (continued) LOW-SIDE MOSFET CURRENT LIMIT THRESHOLD vs JUNCTION TEMPERATURE 5.75 400 5.70 350 VILIML– Current Limit Threshold – mV tSS– Soft Start Time – ms SOFT START TIME vs JUNCTION TEMPERATURE 5.65 5.60 5.55 5.50 5.45 5.40 -40 -25 -10 5 20 35 50 65 80 12 4 Open 300 250 200 150 100 50 0 -40 -25 -10 95 110 125 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 5. Figure 6. HIGH-SIDE MOSFET CURRENT LIMIT THRESHOLD vs JUNCTION TEMPERATURE TOTAL TIME-TO-REGULATION vs JUNCTION TEMPERATURE 8.5 800 8.3 700 tREG – Time-to-Regulation – ms VILIMH– Current Limit Threshold – mV RCOMP (kW) 600 500 400 300 200 8.1 7.9 7.7 7.5 7.3 7.1 6.9 6.7 100 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 7. Copyright © 2008–2012, Texas Instruments Incorporated 6.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 8. 7 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VID THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 15 1.1 12 1.0 9 0.9 6 Overvoltage 3 0 -3 -6 Undervoltage -9 VVID– VID Threshold Voltage – V Powergood Threshold Change – % RELATIVE POWER GOOD THRESHOLD vs JUNCTION TEMPERATURE High-Level Input Voltage 0.8 0.7 0.6 0.5 0.3 -12 -15 -40 -25 -10 5 20 35 50 65 80 0.2 -40 -25 -10 95 110 125 20 35 50 65 80 Figure 9. Figure 10. REF SOURCE/SINK CURRENT vs JUNCTION TEMPERATURE VID PULL UP CURRENT vs JUNCTION TEMPERATURE 95 110 125 81.0 658 80.5 656 80.0 654 IVID– VID Pull Up Current – mA IREF– REF Source/Sink Current – mA 5 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 652 650 648 646 644 642 79.5 79.0 78.5 78.0 77.5 77.0 76.5 76.0 75.5 640 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 11. 8 Low-Level Input Voltage 0.4 75.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 12. Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 TYPICAL CHARACTERISTICS (continued) RELATIVE OVERCURRENT TRIP POINT vs FREEWHEEL TIME IOC - Relative Overcurrent Trip Point - A 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.4 0.6 0.8 1.0 1.2 1-D - Freewheel Time - ms 1.4 1.6 Figure 13. Copyright © 2008–2012, Texas Instruments Incorporated 9 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com DEVICE INFORMATION Figure 14. RGY PACKAGE (Bottom View) VID2 VID1 VID3 VID0 HDRV REF SW EN BOOT FB LDRV COMP BP VDD GND PGOOD TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION NO. BOOT 12 I Gate drive voltage for the high-side N-channel MOSFET. A 100-nF capacitor (typical) must be connected between this pin and SW. BP 10 O Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 μF or greater from this pin to GND. COMP 6 O Output of the error amplifier and connection node for loop feedback components. EN 4 I Logic level input which starts or stops the controller from an external user command. A high level turns the controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is not used. Pulling this pin low disables the controller. FB 5 I Inverting input to the error amplifier. HDRV 14 O Bootstrapped gate drive output for the high-side N-channel MOSFET. LDRV 11 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET. PGOOD 8 O Open drain power good output. REF 3 I Non-Inverting input to the error amplifier. Its voltage range is from 0.9 V to 1.2 V in 20-mV steps. It is also internally connected to the DAC output through a unit gain buffer with 650-μA source/sink current capability. An external capacitor connected from this pin to GND programs the output voltage transition rate when VID code changes. VDD 7 I Power input to the controller. A 1-μF bypass capacitor should be connected closely from this pin to GND. VID0 2 I VID1 1 I VID2 16 I VID3 15 I GND 9 10 Logic level inputs to the internal DAC that provides the reference voltage for output regulation. These pins are internally pulled up to a 1.68-V source with 80-μA pull-up current. Ground connection to the controller Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 FUNCTIONAL BLOCK DIAGRAM VDD SC 1.5 M OCL SD EN CLK 4 FAULT Fault Controller SD UVLO Soft Start Ramp Generator OCH 5.3 V VDD 5V Regulator 7 VDD – 0.5 V 4.2 V UVLO SD 12 BOOT 14 HDRV 13 SW 11 LDRV 8 PGOOD 9 GND UVLO BP Oscillator 10 5.3 V COMP CLK 6 PWM Logic and Anti-Cross Conduction SS VREF FB 5 REF 3 Error Amplifier 5.3 V FAULT SC Threshold Latch VID3 15 VID2 16 VID1 1 VID0 2 5.3 V FAULT IREF Dynamic VID D/A IREF 750 K Short Circuit Threshold Selector SC: 100 mV, 200 mV or 280 mV Copyright © 2008–2012, Texas Instruments Incorporated SD Power Good Control FB UVLO 11 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com APPLICATION INFORMATION Introduction The TPS40197 is a synchronous buck controller which provides all the necessary features to construct a highperformance DC/DC converter. Support for pre-biased outputs eliminates concerns about damaging sensitive loads during startup. Strong gate drivers for the high-side and rectifier MOSFETs decrease switching losses for increased efficiency. Adaptive gate drive timing prevents shoot through and minimizes body diode conduction in the rectifier MOSFET, also increasing efficiency. Selectable short-circuit protection thresholds and hiccup recovery from a short-circuit increase design flexibility and minimize power dissipation in the event of a prolonged output fault. A dedicated enable pin allows the converter to be placed in a very low quiescent current shutdown mode. Internally fixed switching frequency and soft-start time reduce external component count, simplifying design and layout, as well as reducing footprint and cost. The dynamic voltage identification (VID) circuitry is designed to provide Smart-Reflex™ power supply solution to DSPs with core voltage optimization. Enable The TPS40197 includes a dedicated EN pin. This simplifies user level interface design since no multiplexed functions exist. Another benefit is a true low-power shutdown mode of operation. When the EN pin is pulled to GND, all unnecessary functions, including the BP regulator, are turned off, reducing the IVDD current to 45 μA. A functionally equivalent circuit of the enable circuitry is shown in Figure 15. VDD 7 200 kW 1.5 MW 1 kW EN 4 To Enable chip 200 W 1 kW 300 kW GND 9 UDG-08097 Figure 15. TPS40197 EN Pin Internal Circuitry If the EN pin is left floating, the device starts automatically. The pin must be pulled to less than 600 mV to specify that the TPS40197 is in shutdown mode. Note that the EN pin is relatively high impedance. In some situations, there could be enough noise nearby to cause the EN pin to swing below the 600-mV threshold and give erroneous shutdown commands to other components of the device. There are two solutions to this potential problem. • Place a capacitor from EN to GND. A side-effect of this is to delay the start of the converter while the capacitor charges past the enable threshold. • Place a resistor from VDD to EN. This causes more current to flow in the shutdown mode, but does not delay converter startup. If a resistor is used, the total current into the EN pin should be limited to no more than 500 μA. 12 Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 The ENABLE pin is self-clamping. The clamp voltage can be as low as 1 V with a 1-kΩ ground impedance. Due to this self-clamping feature, the pull-up impedance on the ENABLE pin should be selected to limit the sink current to less than 500 μA. Driving the ENABLE pin with a low-impedance source voltage can result in damage to the device. Because of the self-clamping feature, it requires care when connecting multiple ENABLE pins together. For enabling multiple TPS4019x devices (TPS40190, TPS40192, TPS40193, TPS40195, TPS40197), please refer to the Application Report SLVA509. Oscillator The fixed internal switching frequency of the TPS40197 is 520 kHz. UVLO When the input voltage is below the UVLO threshold, the device holds all gate drive outputs in the low (OFF) state. When the input rises above the UVLO threshold, and the EN pin is above the turn ON threshold, the oscillator begins to operate and the start-up sequence is allowed to begin. The UVLO level is internally fixed at 4.2 V. Startup Sequence and Timing The TPS40197 startup sequence is as follows. After input power is applied, the 5-V onboard regulator initiates. Once this regulator comes up, the device goes through a period where it samples the impedance at the COMP pin and determines the short-circuit protection threshold voltage, by placing 400 mV on the COMP pin for approximately 1.15 ms. During this time, the current is measured and compared against internal thresholds to select the short circuit protection threshold. After this, the COMP pin is brought low for 1.15 ms. This ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the converter when the converter is allowed to start switching. After these initial 2.3 ms, the internal soft-start circuitry is engaged and the converter is allowed to start as shown in Figure 16. EN COMP VOUT Soft-Start Time (5.5 ms) SC Threshold Configured (1.15 ms) Compensation Network Zeroed (1.15 ms) UDG-08099 Figure 16. Startup Sequence Copyright © 2008–2012, Texas Instruments Incorporated 13 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com Selecting the Short Circuit Current A short circuit in the TPS40197 is detected by sensing the voltage drop across the low-side FET when it is on, and across the high-side FET when it is on. If the voltage drop across either FET exceeds the short-circuit threshold in any given switching cycle, a counter increments one count. If the voltage across the high-side FET was higher than the short circuit threshold, that FET is turned off early. If the voltage drop across either FET does not exceed the short circuit threshold during a cycle, the counter is decremented for that cycle. If the counter fills up (a count of 7) a fault condition is declared and the drivers turn off both MOSFETs. After a timeout of approximately 50 ms, the controller attempts to restart. If a short circuit continues at the output, the current quickly ramps up to the short-circuit threshold and another fault condition is declared and the process of waiting for the 50 ms and attempting to restart repeats. The low-side threshold increases as the low-side on time decreases due to blanking time and comparator response time. See Figure 13 for changes in the threshold as the low-side FET conduction time decreases. The TPS40197 provides three selectable short-circuit protection thresholds for the low-side FET: 100 mV, 200 mV and 280 mV. The particular threshold is selected by connecting a resistor from COMP to GND. Table 1 shows the short-circuit thresholds for corresponding resistors from COMP to GND. When designing the compensation for the feedback loop, remember that a low impedance compensation network combined with a long network time constant can cause the short-circuit threshold setting to not be as expected. The time constant and impedance of the network connected from COMP to FB should be as in Equation 1 to ensure no interaction with the short-circuit threshold setting. æ -t ö æ 0.4 V ö çè (R1´C1)÷ø £ 10 mA ç R1 ÷ ´ e è ø where • • t is 1.15 ms, the sampling time of the short circuit threshold setting circuit R1 and C1 are the values of the components in Figure 17 VOUT C2 R1 (1) RCOMP C1 5 6 FB COMP TPS40197 UDG-08098 Figure 17. Short Circuit Threshold Feedback Network 14 Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 Table 1. Circuit Threshold Voltage Selection COMPARATOR RESISTANCE RCOMP (kΩ) CURRENT LIMIT THRESHOLD VOLTAGE VILIM (mV) 12 ±10% 280 OPEN 200 4 ±10% 100 The range of expected short-circuit current thresholds is shown in Equation 2 and Equation 3. ISCP(max) = ISCP(min) = VILIM(max) RDS(on)min (2) VILIM(min) RDS(on)max where • • • ISCP is the short circuit current VILIM is the short-circuit threshold for the low-side MOSFET RDS(on) is the channel resistance of the low-side MOSFET (3) Note that due to blanking time considerations, overcurrent threshold accuracy may fall off for duty cycle greater than 75% because the overcurrent comparator has only a very short time to sample the SW pin voltage under these conditions and may not have time to respond to voltages very near the threshold. The short-circuit protection threshold for the high-side MOSFET is fixed at 550 mV typical, 400 mV minimum. This threshold is in place to provide a maximum current output using pulse-by-pulse current limit in the case of a fault. The pulse terminates when the voltage drop across the high-side FET exceeds the short-circuit threshold. The maximum amount of current that can be specified to be sourced from a converter can be found by Equation 4. IOUT(max) = VILIMH(min) RDS(on)max where • • • IOUT(max) is the maximum current that the converter is specified to source VILIMH(min) is the short-circuit threshold for the high-side MOSFET (400 mV) RDS(on)max is the maximum resistance of the high-side MOSFET (4) If the required current from the converter is greater than the calculated IOUT(max), a lower resistance high-side MOSFET must be chosen. Both the high-side and low-side thresholds use temperature compensation to approximate the change in resistance for a typical power MOSFET. This helps counteract shifts in overcurrent thresholds as temperature increases. For this to be effective, the MOSFETs and the device must be well coupled thermally. Copyright © 2008–2012, Texas Instruments Incorporated 15 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com Voltage Reference and Dynamic VID To provide optimized voltage for Smart-Reflex™ DSP cores, the TPS40197 is designed to monitor the VID code at all times once soft-start is complete, and actively adjusts its output voltage if the VID code should change during normal operation. A digital-to-analog converter (DAC) generates a reference voltage based on the state of logical signals at pins VID0 through VID3. The DAC decodes the 4-bit logic signal into one of the discrete voltages shown in Table 2. The default setting for the output is 1.2 V (VID code 1111). The output voltage is 1.2 V during initial start or restart after cycling the input, toggling EN pin or recovering from a short circuit at the output. To ensure that no erroneous output voltage is produced, the TPS40197 VID inputs have internal anti-skew circuit with approximately 550 ns of filtering time. Each VID input is pulled up to an internal 1.68-V source with 80-μA pull-up current for use with open-drain outputs. The output voltage can be programmed from 0.9 V to 1.2 V in 20 mV steps. Smooth upward and downward core voltage transition can be achieved by programming the transition rate with an external capacitor connected from REF pin to GND. The required capacitance can be calculated using Equation 5. CREF = (IREF ´ TTR ) VVID-TR where • • • VVID-TR is the total voltage transition through VID IREF is the internal reference source/sink current TTR is the intended total VID voltage transition time (5) CREF must be limited to a maximum of 1.5 μF to avoid interfering with the soft-start. A capacitor (CREF) with a minimum capacitance of 100-nF is also recommended. 16 Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 Table 2. Voltage Identification Codes VID TERMINALS (0 = LOW, 1 = HIGH) VREF VID3 VID2 VID1 VID0 (Vdc) 0 0 0 0 0.90 0 0 0 1 0.92 0 0 1 0 0.94 0 0 1 1 0.96 0 1 0 0 0.98 0 1 0 1 1.00 0 1 1 0 1.02 0 1 1 1 1.04 1 0 0 0 1.06 1 0 0 1 1.08 1 0 1 0 1.10 1 0 1 1 1.12 1 1 0 0 1.14 1 1 0 1 1.16 1 1 1 0 1.18 1 1 1 1 1.20 Minimum On-Time Consideration The TPS40197 has a minimum on-time of 110 ns (maximum). With the restriction of this minimum on-time, the device may begin to skip pulses to effectively lower the overall on-time to keep the output in regulation when operating at high input-to-output conversion ratio. If pulse skipping is undesirable for some reason, it is recommended that the maximum input voltage be limited to 13.5 V. BP Regulator The TPS40197 has an on board 5-V BP regulator that allows the parts to operate from a single voltage feed. No separate 5-V feed to the part is required. This regulator needs to have a minimum of 1-μF of capacitance on the BP pin for stability. A ceramic capacitor is suggested for this purpose. This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in some cases. If this pin is used for external loads, be aware that this is the power supply for the internals of the TPS40197. While efforts have been made to reduce sensitivity, any noise induced on this line has an adverse effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or skewed reference voltage. Also, when the device is disabled by pulling the EN pin low, this regulator is turned off and will not be available to supply power. The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must operate. Larger MOSFETs require more gate drive current and reduce the amount of power available on this pin for other tasks. The total current that can be drawn from this pin by both the gate drive and external loads cannot exceed 50 mA. The device itself consumes up to 4 mA from the regulator and the total gate drive current can be found from Equation 6. Copyright © 2008–2012, Texas Instruments Incorporated 17 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com For regulator stability, a 1-μF capacitor is required to be connected from BP to GND. In some applications using higher gate charge MOSFETs, a larger capacitor is required for noise suppression. For a total gate charge of both the high-side and low-side MOSFETs greater than 20 nC, a 2.2-μF or larger capacitor is recommended. ( IG = fSW ´ QG(high ) + QG(low ) ) where • • • • IG is the required gate drive current fSW is the switching frequency QG(high) is the gate charge requirement for the high-side FET when VGS = 5 V QG(low) is the gate charge requirement for the low-side FET when VGS = 5 V (6) Pre-Bias Startup The TPS40197 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous rectification by starting the first LDRV pulse with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensures that the output voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased startup to normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of switching until the low-side MOSFET is turned on for the full (1-D) interval is defined by 32 clock cycles. Drivers The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate-to-source voltage of 5 V. The LDRV driver switches between BP and GND, while HDRV driver is referenced to SW and switches between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier. The drivers are capable of driving MOSFETS that are appropriate for a 15-A converter. Power Good The TPS40197 provides an indication that output power is good for the converter. This is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include: • VFB is more than 10% from the reference voltage based on VID codes • soft-start is active • an undervoltage condition exists for the device • a short-circuit condition has been detected • die temperature is over (140°C) NOTE When there is no power to the device, PGOOD is not able to pull close to GND if an auxiliary supply is used for the power good indication. In this case, a built in resistor connected from drain to gate on the PGOOD pull down device makes the PGOOD pin look approximately like a diode to GND. Thermal Shutdown If the junction temperature of the device reaches the thermal shutdown limit of 140°C, the PWM and the oscillator are turned off and HDRV and LDRV are driven low, turning off both FETs. When the junction cools to the required level (120°C nominal), the PWM initiates soft-start as during a normal power-up cycle. 18 Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 DESIGN EXAMPLE This example illustrates a design for a 12 V to 0.9 V~1.2 V point-of-load synchronous buck converter. The design goal parameters are given in Table 3. Table 3. Design Goal Parameters PARAMETER VIN TEST CONDITION Input voltage MIN TYP 10.8 MAX UNIT 13.2 V Input current IOUT = 7 A, VIN = 12 V 0.85 1 A No load input current IOUT = 0 A, VIN = 12 V 35 50 mA Output voltage IOUT = 7 A, VIN = 12 V 1.50% VVID Line regulation IOUT = 7 A, 10.8 ≤ VIN ≤ 13.2 V 0.50% Load regulation 0 A ≤ IOUT ≤ 7 A, VIN = 12 V 0.50% VRIPPLE Output ripple IOUT = 7 A 24 mV VTRANS Transient deviation ΔIOUT = 6A @ 1 A/μs IOUT Output current 10.8 ≤ VIN ≤ 13.2 V fSW Switching frequency IIN VOUT -1.50% 24 0 mV 7 520 A kHz The schematic for the design is shown in Figure 18 and the list of materials is shown in Table 4. + + Figure 18. TPS40197 Sample Schematic Copyright © 2008–2012, Texas Instruments Incorporated 19 TPS40197 SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 www.ti.com Table 4. Design Example List of Materials REFERENCE DESIGNATOR QTY DESCRIPTION MFR PART NUMBER C1, C2, C3 3 Capacitor, ceramic, 16 V, X7R, 20%, 22 μF, 1210 TDK C3225X7R1C226K C4, C12 2 Capacitor, POSCAP, 2.5 V, 20%, 1 mF, 5 mΩ, D4D Sanyo 2R5TPD1000M5 C5 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 100 μF, 1210 TDK C3225X5R0J107K C6, C9, C10 3 Capacitor, ceramic, 16 V, X7R, 20%, 1 μF, 0603 Std Std C7 1 Capacitor, ceramic, 10 V, X5R, 20%, 470 nF, 0603 Std Std C8 1 Capacitor, ceramic, 50 V, NPO, 10%, 2.2 nF, 0603 Std Std C11 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 4.7 μF, 0603 TDK C1608X5R0J475K C13 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 10 μF, 0603 TDK C1608X5R0J106K C14 1 Capacitor, ceramic, 50 V, NPO, 10%, 15 pF, 0603 Std Std C15 1 Capacitor, ceramic, 50 V, X7R, 20%, 3.3 nF, 0603 Std Std C100 1 Capacitor, ceramic, 50 V, X7R, 20%, 4.7 nF, 0603 Std Std L1 1 Inductor, SMT, 27 A, 1.5 μH, 2.5 mΩ, 0.508 x 0.520 Vishay IHLP5050FDER1R5M01 Q1 1 MOSFET, N-channel, 30 V, 11A, 13.8 mΩ, SO-8 IR IRF7807Z Q2 1 MOSFET, N-channel, 30 V, 13.6 A, 9.1 mΩ, SO-8 IR IRF7821 R1 1 Resistor, chip, 1/16 W, 5%, 10 kΩ, 0603 Std Std R2 1 Resistor, chip, 1/16 W, 5%, 1 Ω, 0603 Std Std R3 1 Resistor, chip, 1/16 W, 1%, 46.4 kΩ, 0603 Std Std R5 1 Resistor, chip, 1/16 W, 1%, 1.33 kΩ, 0603 Std Std R6 1 Resistor, chip, 1/16 W, 1%, 23.2 kΩ, 0603 Std Std R100 1 Resistor, chip, 1/4 W, 5%, 5.6 Ω, 1206 Std Std 1 IC, synchronous buck controller with 4-bit VID interface for Smart-Reflex DSPs, QFN-16 TI TPS40197RGY U1 20 Copyright © 2008–2012, Texas Instruments Incorporated TPS40197 www.ti.com SLUS886A – NOVEMBER 2008 – REVISED JULY 2012 ADDITIONAL REFERENCES RELATED DEVICES The following devices have characteristics similar to the TPS40197 and may be of interest. TI LITERATURE NUMBER SLUS719 DEVICE TPS40192 TPS40193 DESCRIPTION 4.5 V to 18 V Input Synchronous Buck Controller with Power Good REFERENCES TI LITERATURE NUMBER DOCUMENT TYPE SPRAAW7 Application Report TMS320C6474 Hardware Design Guide SLVA057 Application Report Understanding Buck Power Stages in Switchmode Power Supplies SLUP206 Seminar Series Under the Hood of Low-Voltage DC/DC Converters, SEM-1500, 2003 Designing Stable Control Loops, SEM-1400, 2001 DESCRIPTION SLUP173 Seminar Series SLMA002 Application Report PowerPAD™ Thermally Enhanced Package SLMA004 Application Report PowerPAD™ Made Easy Spacer REVISION HISTORY Changes from Original (November 2008) to Revision A • Page Added a new paragraph to the Enable section .................................................................................................................. 12 Copyright © 2008–2012, Texas Instruments Incorporated 21 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS40197RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40197RGYT ACTIVE VQFN RGY 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40197RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 TPS40197RGYT VQFN RGY 16 250 180.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40197RGYR VQFN RGY 16 3000 367.0 367.0 35.0 TPS40197RGYT VQFN RGY 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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