PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Stereo Audio Codec With Embedded miniDSP Check for Samples: PCM3070 FEATURES APPLICATIONS • • • • • • • • • • 1 • • • • • • • Stereo Audio DAC with 100dB SNR Stereo Audio ADC with 93dB SNR Extensive Signal Processing Options Embedded miniDSP Six Single-Ended or 3 Fully-Differential Analog Inputs Stereo Headphone Outputs Stereo Line Outputs Very Low-Noise PGA Analog Bypass Mode Programmable PLL Integrated LDO 5mm x 5mm 32-pin QFN Package Soundbar Flat Panel Television MP3 Docking stations Cell Phone Docking Stations Other Stereo or 2.1 Home Audio systems DESCRIPTION The PCM3070 is a flexible stereo audio codec with programmable inputs and outputs, fully-programmable miniDSP, fixed predefined and parameterizable signal processing blocks, integrated PLL, integrated LDOs and flexible digital interfaces. IN1_L IN2_L IN3_L 0…+47.5 dB + Left ADC tpl + ´ AGC DRC ADC Signal Proc. DAC Signal Proc. Vol . Ctrl -72...0dB -6...+29dB HPL + Left DAC ´ 1dB steps Gain Adj. 0.5 dB steps -6...+29dB -30...0 dB LOL + Data Interface miniDSP 1dB steps miniDSP -6...+29dB -30...0 dB LOR + 1dB steps 0… +47.5 dB + Gain Adj. Right ADC IN3_R + tpr ´ 0.5 dB steps IN2_R ADC Signal Proc. DAC Signal Proc. AGC DRC -6...+29dB Right DAC ´ Vol . Ctrl HPR + 1dB steps -72...0dB IN1_R SPI_Select SPI / I2C Control Block Reset PLL Interrupt Ctrl Secondary I2S IF Primary I2S Interface HPVdd ALDO Supplies Ref Ref Pin Muxing/ Clock Routing DLDO BCLK WCLK DIN DOUT GPIO MCLK SCLK MISO SDA/MOSI SCL/SSZ IOVss DVss AVss IOVdd DVdd AVdd LDO Select LDO in Figure 1. Simplified Block Diagram 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2011, Texas Instruments Incorporated PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) The PCM3070 features two fully-programmable miniDSP cores that support application-specific algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software controlled. Target algorithms, like speaker EQ, Crossovers, Dynamic Range Controls, Intelligent volume controls and other post-processing algorithms are loaded into the device after power-up. Extensive register-based control of input/output channel configuration, gains, effects, pin-multiplexing and clocks is included, allowing the device to be precisely targeted to its application. The record path of the PCM3070 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations covering single-ended and differential setups, as well as floating or mixed input signals. The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC and analog input signals as well as programmable volume controls. The playback path contains two high-power output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways, including stereo and mono BTL. The voltage supply range for the PCM3070 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, LDOs are integrated to generate the appropriate analog or digital supply from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.5V–3.6V. The required internal clock of the PCM3070 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz. The device is available in the 5mm × 5mm, 32-pin QFN package. 2 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Package and Signal Descriptions Packaging/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE PCM3070 QFN RHB –40°C to 85°C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PCM3070RHBT Tape and Reel, 250 PCM3070RHBR Tape and Reel, 3000 8 1 GPIO/MFP5 (32) SCLK/MFP3 IOVSS IOVDD DIN/MFP1 DOUT/MFP2 WCLK BCLK MCLK (1) Pin Assignments 32 9 SCL/SSZ SDA/MOSI RESET LDO_SELECT MISO/MFP4 DVDD SPI_SELECT DVSS IN1_L HPR IN1_R LDOIN HPL IN2_L 25 16 24 IN2_R 17 AVSS NC REF IN3_L IN3_R LOL LOR AVDD Figure 2. QFN () Package, Bottom View Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 3 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 1. Terminal Functions TERMINAL NAME TYPE 1 MCLK I DESCRIPTION 2 BCLK IO Audio serial data bus (primary) bit clock 3 WCLK IO Audio serial data bus (primary) word clock 4 DIN I Master Clock Input Primary function Audio serial data bus data input MFP1 Secondary function Audio serial data bus (secondary) bit clock input Audio serial data bus (secondary) word clock input Clock Input General Purpose Input 5 DOUT O Primary Audio serial data bus data output MFP2 Secondary General Purpose Output Clock Output INT1 Output INT2 Output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output 6 IOVDD Power I/O voltage supply 1.1V – 3.6V 7 IOVSS Ground I/O ground supply 8 SCLK I Primary (SPI_Select = 1) SPI serial clock MFP3 Secondary: (SPI_Select = 0) Audio serial data bus (secondary) bit clock input Audio serial data bus (secondary) DAC/common word clock input Audio serial data bus (secondary) ADC word clock input Audio serial data bus (secondary) data input General Purpose Input 9 SCL/ SSZ I I2C interface serial clock (SPI_Select = 0) SPI interface mode chip-select signal (SPI_Select = 1) 10 SDA/ MOSI I I2C interface mode serial data input (SPI_Select = 0) SPI interface mode serial data input (SPI_Select = 1) 11 MISO O Primary (SPI_Select = 1) Serial data output MFP4 Secondary (SPI_Select = 0) General purpose output CLKOUT output INT1 output INT2 output Audio serial data bus (primary) ADC word clock output Audio serial data bus (secondary) data output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output 12 4 SPI_ SELECT I Control mode select pin ( 1 = SPI, 0 = I2C ) Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 1. Terminal Functions (continued) TERMINAL NAME TYPE 13 IN1_L I DESCRIPTION Multifunction Analog Input, or Single-ended configuration: Line 1 left or Differential configuration: Line right, negative 14 IN1_R I Multifunction Analog Input, or Single-ended configuration: or Line 1 right or Differential configuration: Line right, positive 15 IN2_L I Multifunction Analog Input, or Single-ended configuration: Line 2 right or Differential configuration: Line left, positive 16 IN2_R I Multifunction Analog Input, or Single-ended configuration: Line 2 right or Differential configuration: Line left, negative 17 AVss Ground 18 REF O Reference voltage output for filtering 19 NC - NC, do not connect 20 IN3_L I Multifunction Analog Input, or Single-ended configuration: Line 3 left, or Differential configuration: Line left, positive, or Differential configuration: Line right, negative 21 IN3_R I Multifunction Analog Input, or Single-ended configuration: Line 3 right, or Differential configuration: Line left, negative, or Differential configuration: Line right, positive 24 AVdd Power 25 HPL O 26 LDOIN/ HPVDD Power 27 HPR O 28 DVss Ground Digital Ground and Chip-substrate 29 DVdd Power If LDO_SELECT Pin = 0 (D-LDO disabled) Analog ground supply Analog voltage supply 1.5V–1.95V Input when A-LDO disabled, Filtering output when A-LDO enabled Left high power output driver LDO Input supply and Headphone Power supply 1.9V– 3.6V Right high power output driver Digital voltage supply 1.26V – 1.95V If LDO_SELECT Pin = 1 (D-LDO enabled) Digital voltage supply filtering output 30 LDO_ SELECT I connect to DVss. 31 RESET I Reset (active low) 32 GPIO I Primary General Purpose digital IO MFP5 Secondary CLKOUT Output INT1 Output INT2 Output Audio serial data bus ADC word clock output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 5 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT AVdd to AVss –0.3 to 2.2 V DVdd to DVss –0.3 to 2.2 V IOVDD to IOVSS –0.3 to 3.9 V LDOIN to AVss –0.3 to 3.9 V Digital Input voltage to IOVDD + 0.3 V Analog input voltage to AVdd + 0.3 V –40 to 85 °C Operating temperature range °C Storage temperature range Junction temperature (TJ Max) QFN package (RHB) θJA Thermal impedance (1) °C 105 Power dissipation (TJ Max – TA)/ θJA W 35 C/W Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions MIN NOM LDOIN Power Supply Voltage Range Referenced to AVss (1) AVdd 1.5 Referenced to IOVSS (1) IOVDD DVdd (2) Clock divider uses fractional divide (D > 0), P=1, DVdd ≥ 1.65V Master Clock Frequency SCL SCL Clock Frequency CLout Digital output load capacitance TOPR Operating Temperature Range (1) (2) 6 1.95 1.8 1.95 3.6 10 20 MHz 0.512 20 MHz MCLK; Master Clock Frequency; DVdd ≥ 1.65V 50 MHz MCLK; Master Clock Frequency; DVdd ≥ 1.26V 25 Clock divider uses integer divide (D = 0), P=1, DVdd ≥ 1.65V MCLK UNIT V 1.8 1.5 Referenced to DVss (1) PLL Input Frequency MAX 1.9 400 10 –40 kHz pF 85 °C All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground signals. At DVdd values lower than 1.65V, the PLL does not function. Please see the Maximum PCM3070 Clock Frequencies table in the PCM3070 Application Reference Guide (SLAU332) for details on maximum clock frequencies. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, ADC At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER AUDIO ADC TEST CONDITIONS Input signal level (0dB) Single-ended, CM = 0.9V Device Setup 1kHz sine wave input Single-ended Configuration IN1R to Right ADC and IN1L to Left ADC, Rin = 20K, fs = 48kHz, AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1, Inputs ac-shorted to ground SNR Signal-to-noise ratio, A-weighted (1) DR Dynamic range A-weighted (1) THD+N MIN TYP MAX UNIT (1) (2) (2) (2) Total Harmonic Distortion plus Noise IN2R, IN3R routed to Right ADC and ac-shorted to ground IN2L, IN3L routed to Left ADC and ac-shorted to ground 0.5 80 VRMS 93 93 dB –60dB full-scale, 1-kHz input signal 92 –3 dB full-scale, 1-kHz input signal –85 IN2R,IN3R routed to Right ADC IN2L, IN3L routed to Left ADC –3dB full-scale, 1-kHz input signal –85 dB –70 dB AUDIO ADC SNR Input signal level (0dB) Single-ended, CM=0.75V, AVdd = 1.5V Device Setup 1kHz sine wave input Single-ended Configuration IN1R, IN2R, IN3R routed to Right ADC IN1L, IN2L, IN3L routed to Left ADC Rin = 20K, fs = 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled, AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1 Signal-to-noise ratio, A-weighted (1) (2) (1) (2) DR Dynamic range A-weighted THD+N Total Harmonic Distortion plus Noise (1) (2) 0.375 VRMS Inputs ac-shorted to ground 91 dB –60dB full-scale, 1-kHz input signal 90 dB –3dB full-scale, 1-kHz input signal –80 dB Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer. All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 7 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, ADC (continued) At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC ICN Input signal level (0dB) Differential Input, CM=0.9V Device Setup 1kHz sine wave input Differential configuration IN1L and IN1R routed to Right ADC IN2L and IN2R routed to Left ADC Rin =10K, fs =48kHz, AOSR=128 MCLK = 256* fs PLL Disabled AGC = OFF, Channel Gain=40dB Processing Block = PRB_R1, Idle-Channel Noise, A-weighted (3) (4) Inputs ac-shorted to ground, input referred noise 10 mV 2 μVRMS AUDIO ADC –0.05 dB Gain Error 1kHz sine wave input Single-ended configuration Rin = 20K fs = 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled AGC = OFF, Channel Gain=0dB Processing Block = PRB_R1, 108 dB Input Channel Separation 1kHz sine wave input at -3dBFS Single-ended configuration IN1L routed to Left ADC IN1R routed to Right ADC, Rin = 20K AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V 1kHz sine wave input at –3dBFS on IN2L, IN2L internally not routed. IN1L routed to Left ADC ac-coupled to ground 115 dB Input Pin Crosstalk 55 dB Single-Ended, Rin = 10K, PGA gain set to 0dB 0 dB Single-Ended, Rin = 10K, PGA gain set to 47.5dB 47.5 dB Single-Ended, Rin = 20K, PGA gain set to 0dB –6 dB Single-Ended, Rin = 20K, PGA gain set to 47.5dB 41.5 dB Single-Ended, Rin = 40K, PGA gain set to 0dB –12 dB Single-Ended, Rin = 40K, PGA gain set to 47.5dB 35.5 dB 1kHz sine wave input at –3dBFS on IN2R, IN2R internally not routed. IN1R routed to Right ADC ac-coupled to ground Single-ended configuration Rin = 20K, AOSR=128 Channel, Gain=0dB, CM=0.9V PSRR ADC programmable gain amplifier gain (3) (4) 8 217Hz, 100mVpp signal on AVdd, Single-ended configuration, Rin=20K, Channel Gain=0dB; CM=0.9V Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer. All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, ADC (continued) At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER ADC programmable gain amplifier step size TEST CONDITIONS MIN 1-kHz tone TYP MAX UNIT 0.5 dB Electrical Characteristics, Bypass Outputs At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE Device Setup Load = 16Ω (single-ended), 50pF; Input and Output CM=0.9V; Headphone Output on LDOIN Supply; IN1L routed to HPL and IN1R routed to HPR; Channel Gain=0dB –0.8 Gain Error THD Noise, A-weighted (1) Idle Channel, IN1L and IN1R ac-shorted to ground Total Harmonic Distortion 446mVrms, 1kHz input signal 3 dB μVRMS –89 dB 0.6 dB ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE Device Setup Load = 10kΩ (single-ended), 56pF; Input and Output CM=0.9V; LINE Output on LDOIN Supply; IN1L routed to ADCPGA_L and IN1R routed to ADCPGA_R; Rin = 20kΩ ADCPGA_L routed to LOL and ADCPGA_R routed to LOR; Channel Gain = 0dB Gain Error Idle Channel, IN1L and IN1R ac-shorted to ground Noise, A-weighted (1) (1) Channel Gain=40dB, Input Signal (0dB) = 5mVrms Inputs ac-shorted to ground, Input Referred 7 μVRMS 3.4 μVRMS All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 9 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, Audio DAC Outputs At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 VRMS 87 100 dB –60dB 1kHz input full-scale signal, Word length=20 bits 100 dB AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT Load = 10kΩ (single-ended), 56pF Line Output on AVdd Supply Input & Output CM=0.9V DOSR = 128, MCLK=256* fs, Channel Gain = 0dB, word length = 16 bits, Processing Block = PRB_P1, Device Setup Full scale output voltage (0dB) SNR Signal-to-noise ratio A-weighted (1) (2) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1kHz input signal –83 DAC Gain Error 0 dB, 1kHz input full scale signal 0.3 dB DAC Mute Attenuation Mute 119 dB DAC channel separation –1 dB, 1kHz signal, between left and right HP out 113 dB 100mVpp, 1kHz signal applied to AVdd 73 dB 100mVpp, 217Hz signal applied to AVdd 77 dB (1) (2) DAC PSRR All zeros fed to DAC input –70 dB AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT Load = 10kΩ (single-ended), 56pF Line Output on AVdd Supply Input & Output CM=0.75V; AVdd=1.5V DOSR = 128 MCLK=256* fs Channel Gain = –2dB word length = 20 bits Processing Block = PRB_P1 Device Setup Full scale output voltage (0dB) SNR Signal-to-noise ratio, A-weighted 0.375 (1) (2) (1) (2) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise All zeros fed to DAC input VRMS 99 dB –60dB 1 kHz input full-scale signal 97 dB –1 dB full-scale, 1-kHz input signal –85 dB AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16Ω (single-ended), 50pF Headphone Output on AVdd Supply, Input & Output CM=0.9V, DOSR = 128, MCLK=256* fs, Channel Gain=0dB word length = 16 bits; Processing Block = PRB_P1 Device Setup Full scale output voltage (0dB) 0.5 VRMS dB 99 dB Signal-to-noise ratio, A-weighted (1) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1kHz input signal –83 DAC Gain Error 0dB, 1kHz input full scale signal –0.3 dB DAC Mute Attenuation Mute 122 dB DAC channel separation –1dB, 1kHz signal, between left and right HP out 110 dB (1) (2) 10 (2) 100 SNR (1) (2) All zeros fed to DAC input –60dB 1kHz input full-scale signal, Word Length = 20 bits 87 –70 dB Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer. All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, Audio DAC Outputs (continued) At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS DAC PSRR Power Delivered MIN TYP MAX UNIT 100mVpp, 1kHz signal applied to AVdd 73 dB 100mVpp, 217Hz signal applied to AVdd 78 dB RL=16Ω, Output Stage on AVdd = 1.8V THDN < 1%, Input CM=0.9V, Output CM=0.9V 15 RL=16Ω Output Stage on LDOIN = 3.3V, THDN < 1% Input CM=0.9V, Output CM=1.65V 64 mW AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16Ω (single-ended), 50pF, Headphone Output on AVdd Supply, Input & Output CM=0.75V; AVdd=1.5V, DOSR = 128, MCLK=256* fs, Channel Gain = –2dB, word length=20-bits; Processing Block = PRB_P1, Device Setup Full scale output voltage (0dB) SNR 0.375 Signal-to-noise ratio, A-weighted (1) (2) (3) (4) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise All zeros fed to DAC input VRMS 99 dB -60dB 1kHz input full-scale signal 98 dB –1dB full-scale, 1kHz input signal –83 dB 1778 mVRMS AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT Load = 32Ω (differential), 50pF, Headphone Output on LDOIN Supply Input CM = 0.75V, Output CM=1.5V, AVdd=1.8V, LDOIN=3.0V, DOSR = 128 MCLK=256* fs, Channel (headphone driver) Gain = 5dB for full scale output signal, word length=16-bits, Processing Block = PRB_P1, Device Setup Full scale output voltage (0dB) SNR Signal-to-noise ratio, A-weighted DR Dynamic range, A-weighted THD Total Harmonic Distortion Power Delivered (3) (4) (3) (4) (3) (4) All zeros fed to DAC input 98 dB –60dB 1kHz input full-scale signal 96 dB –3dB full-scale, 1kHz input signal –82 dB RL=32Ω, Output Stage on LDOIN = 3.3V, THDN < 1%, Input CM=0.9V, Output CM=1.65V 136 mW RL=32Ω Output Stage on LDOIN = 3.0V, THDN < 1% Input CM=0.9V, Output CM=1.5V 114 mW Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer. All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values space Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 11 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, LDO over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW DROPOUT REGULATOR (AVdd) Output Voltage LDOMode = 1, LDOin > 1.95V 1.67 LDOMode = 0, LDOin > 2.0V 1.72 LDOMode = 2, LDOin > 2.05V 1.77 Output Voltage Accuracy Load Regulation Load current range 0 to 50mA Line Regulation Input Supply Range 1.9V to 3.6V Decoupling Capacitor 12 ±2 % 15 mV 5 mV 60 μA μF 1 Bias Current Submit Documentation Feedback V © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Electrical Characteristics, Misc. At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE Reference Voltage Settings Reference Noise CMMode = 0 (0.9V) 0.9 CMMode = 1 (0.75V) 0.75 CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, Cref = 10μF Decoupling Capacitor 1 V 1 μVRfcMS 10 μF miniDSP (1) Maximum miniDSP clock frequency - ADC DVdd = 1.65V 55.3 MHz Maximum miniDSP clock frequency - DAC DVdd = 1.65V 55.3 MHz I(DVdd) 0.9 μA I(IOVDD) 13 nA Shutdown Current Coarse AVdd supply turned off, LDO_select held at ground, No external digital input is toggled Device Setup (1) docato-extra-info-title miniDSP miniDSP Processing-block clock speed is specified by design and not tested in production. Electrical Characteristics, Logic Levels At 25°C, AVdd, DVdd, IOVDD = 1.8V PARAMETER TEST CONDITIONS MIN LOGIC FAMILY VIH Logic Level VIL TYP MAX UNIT CMOS IIH = 5 μA, IOVDD > 1.6V 0.7 × IOVDD V IIH = 5μA, 1.2V ≤ IOVDD <1.6V 0.9 × IOVDD V IIH = 5μA, IOVDD < 1.2V IOVDD V IIL = 5 μA, IOVDD > 1.6V –0.3 IIL = 5μA, 1.2V ≤ IOVDD <1.6V IIL = 5μA, IOVDD < 1.2V VOH IOH = 2 TTL loads VOL IOL = 2 TTL loads 0.3 × IOVDD V 0.1 × IOVDD V 0 V 0.8 × IOVDD Capacitive Load V 0.1 × IOVDD 10 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 V pF 13 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Interface Timing Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S) All specifications at 25°C, DVdd = 1.8V WCLK td(WS) BCLK td(DO-BCLK) td(DO-WS) DOUT th(DI) tS(DI) DIN I2S/LJF Timing in Master Mode 2 Figure 3. I S/LJF/RJF Timing in Master Mode Table 2. I2S/LJF/RJF Timing in Master Mode (see Figure 3) PARAMETER IOVDD=1.8V MIN IOVDD=3.3V MAX MIN UNITS MAX td(WS) WCLK delay 30 20 ns td (DO-WS) WCLK to DOUT delay (For LJF Mode only) 20 20 ns td (DO-BCLK) BCLK to DOUT delay 22 20 ns ts(DI) DIN setup 8 8 th(DI) DIN hold 8 8 tr Rise time 24 12 ns tf Fall time 24 12 ns 14 Submit Documentation Feedback ns ns © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com WCLK th(WS) tL(BCLK) BCLK tH(BCLK) ts(WS) td(DO-WS) td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 4. I2S/LJF/RJF Timing in Slave Mode Table 3. I2S/LJF/RJF Timing in Slave Mode (see Figure 4) PARAMETER IOVDD=1.8V MIN IOVDD=3.3V MAX MIN UNITS MAX tH (BCLK) BCLK high period 35 35 tL (BCLK) BCLK low period 35 35 ns ts (WS) WCLK setup 8 8 th (WS) WCLK hold 8 td (DO-WS) WCLK to DOUT delay (For LJF mode only) td (DO-BCLK) BCLK to DOUT delay ts(DI) DIN setup 8 8 th(DI) DIN hold 8 8 tr Rise time 4 4 tf Fall time 4 4 8 20 20 22 22 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 15 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Typical DSP Timing Characteristics All specifications at 25°C, DVdd = 1.8V WCLK td(WS) td(WS) BCLK td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 5. DSP Timing in Master Mode Table 4. DSP Timing in Master Mode (see Figure 5) PARAMETER IOVDD=1.8V MIN IOVDD=3.3V MAX MIN 30 UNITS MAX td (WS) WCLK delay td (DO-BCLK) BCLK to DOUT delay ts(DI) DIN setup 8 8 th(DI) DIN hold 8 8 tr Rise time 24 12 ns tf Fall time 24 12 ns 22 20 ns 20 ns ns ns WCLK th(ws) BCLK ts(ws) th(ws) th(ws) tL(BCLK) tH(BCLK) td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 6. DSP Timing in Slave Mode Table 5. DSP Timing in Slave Mode (see Figure 6) PARAMETER IOVDD=1.8V MIN IOVDD=3.3V MAX MIN UNITS MAX tH (BCLK) BCLK high period 35 35 ns tL (BCLK) BCLK low period 35 35 ns ts(WS) WCLK setup 8 8 ns th(WS) WCLK hold 8 8 td (DO-BCLK) BCLK to DOUT delay ts(DI) DIN setup 8 8 th(DI) DIN hold 8 8 tr Rise time 4 4 ns tf Fall time 4 4 ns 16 Submit Documentation Feedback 22 ns 22 ns ns ns © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com I2C Interface Timing Figure 7. I2C Interface Timing Table 6. I2C Interface Timing PARAMETER TEST CONDITION Standard-Mode MIN TYP 0 Fast-Mode MAX 0 TYP UNITS MAX fSCL SCL clock frequency tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4.0 0.8 μs tLOW LOW period of the SCL clock 4.7 1.3 μs tHIGH HIGH period of the SCL clock 4.0 0.6 μs tSU;STA Setup time for a repeated START condition 4.7 0.8 μs tHD;DAT Data hold time: For I2C bus devices tSU;DAT Data set-up time tr SDA and SCL Rise Time tf SDA and SCL Fall Time tSU;STO Set-up time for STOP condition 4.0 0.8 μs tBUF Bus free time between a STOP and START condition 4.7 1.3 μs Cb Capacitive load for each bus line 0 100 MIN 400 3.45 0 1000 20+0.1Cb 300 300 20+0.1Cb 300 250 0.9 100 400 Product Folder Link(s): PCM3070 μs ns 400 Submit Documentation Feedback © 2011, Texas Instruments Incorporated kHz ns ns pF 17 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com SPI Interface Timing SS S t t Lead t t Lag td sck SCLK t sckl tf tr t sckh tv MISO t dis MSB OUT BIT 6 . . . 1 LSB OUT ta MOSI t hi t su MSB IN BIT 6 . . . 1 LSB IN Figure 8. SPI Interface Timing Diagram Timing Requirements (See Figure 8) At 25°C, DVdd = 1.8V Table 7. SPI Interface Timing PARAMETER TEST CONDITION IOVDD=1.8V MIN tsck SCLK Period (1) tsckh tsckl IOVDD=3.3V TYP MAX MIN TYP UNITS MAX 100 50 ns SCLK Pulse width High 50 25 ns SCLK Pulse width Low 50 25 ns tlead Enable Lead Time 30 20 ns ttrail Enable Trail Time 30 20 ns td;seqxfr Sequential Transfer Delay 40 20 ta Slave DOUT access time 40 20 ns tdis Slave DOUT disable time 40 20 ns tsu DIN data setup time 15 10 th;DIN DIN data hold time 15 10 tv;DOUT DOUT data valid time tr tf (1) 18 ns ns ns 25 18 ns SCLK Rise Time 4 4 ns SCLK Fall Time 4 4 ns These parameters are based on characterization and are not tested in production. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Typical Characteristics Typical Performance ADC SNR vs CHANNEL GAIN TOTAL HARMONIC DISTORTION vs HEADPHONE OUTPUT POWER 100 0 THD - Total Harmonic Distortion - dB SNR - Signal-to-Noise Ratio - dB CM=0.9 V, -10 RL = 32 W RIN = 10 kW, Differential 95 90 RIN = 20 kW, Differential 85 80 75 RIN = 10 kW, Single Ended 70 65 RIN = 20 kW, Single Ended 60 -40 -50 -60 -70 -80 -90 -100 20 60 40 CM=1.65 V, RL = 16 W -30 55 0 0 20 Channel Gain - dB 40 60 80 Headphone Output Power - mW Figure 9. 100 Figure 10. TOTAL HARMONIC DISTORTION vs HEADPHONE OUTPUT POWER HEADPHONE SNR AND OUTPUT POWER vs OUTPUT COMMON MODE SETTING 0 70 105 Load = 32 W BTL -10 100 -20 SNR - Signal-to-Noise Ratio - dB THD - Total Harmonic Distortion - dB CM=1.65 V, RL = 32 W -20 50 -20 CM=0.9 V, RL = 16 W -30 CM=1.5 V -40 CM=1.65 V -50 -60 -70 -80 60 SNR 95 50 90 40 85 80 30 OUTPUT POWER 75 20 70 10 65 -90 -100 60 0 50 100 150 Headphone output Power - mW 200 0 0.75 Figure 11. 0.9 1.5 1.25 Output Common Mode Setting - V 1.65 Figure 12. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 19 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com LDO DROPOUT VOLTAGE vs LOAD CURRENT LDO LOAD RESPONSE 350 20 DVDD LDO 15 Change In Output Voltage - mV 300 Dropout Voltage - mV 250 200 AVDD LDO 150 100 50 10 AVDD LDO 5 0 DVDD LDO -5 -10 -15 0 -20 0 10 20 30 Load - mA 40 50 0 10 Figure 13. 20 Load - mA 30 40 50 Figure 14. FFT SINGLE ENDED LINE INPUT TO ADC FFT @ -1dBr vs FREQUENCY PLAYBACK TO HEADPHONE FFT @ -1dBFS vs FREQUENCY 0 0 DAC ADC -20 -20 -40 Power - dBr Power - dBFs -40 -60 -80 -60 -80 -100 -100 -120 -120 -140 0 5000 10000 f - Frequency - Hz 15000 20000 0 Figure 15. 20 5000 10000 f - Frequency - Hz 15000 20000 Figure 16. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com DAC PLAYBACK TO LINE-OUT FFT @ -1dBFS vs FREQUENCY LINE INPUT TO HEADPHONE FFT @ 446mVrms vs FREQUENCY 0 0 DAC -20 -20 -40 Power - dBr Power - dBr -40 -60 -60 -80 -80 -100 -100 -120 -140 -120 0 5000 10000 f - Frequency - Hz 15000 0 20000 5000 10000 f - Frequency - Hz Figure 17. 15000 20000 Figure 18. LINE INPUT TO LINE-OUT FFT @ 446mVrms vs FREQUENCY 0 -20 Power - dBr -40 -60 -80 -100 -120 -140 0 5000 10000 15000 20000 f - Frequency - Hz Figure 19. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 21 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Typical Circuit Configuration MSP430 SCL IN1_L 7.5KW 2.49KW SDA MCLK 0.47mF BCLK DIR9001 2.49KW WCLK IN1_R 0.47mF 7.5KW DIN 7.5KW 2.49KW 0.47mF IN2_L TAS57xx 2.49KW DOUT IN2_R PCM3070 0.47mF 7.5KW 100W LOL 1mF 1KW 0.047mF 7.5KW 2.49KW 0.47mF IN3_L 0.047mF 0.47mF IN3_R 100W HPL LDOIN IOVDD REF DVDD AVDD IOVSS DVSS AVSS LDO_SELECT 2.49KW 7.5KW LOR 47mF HPR 1KW TPA3123 1mF Headphone Output 47mF 1mF 10mF 10mF 10mF 0.1mF 3V3 10mF Figure 20. Typical Circuit Configuration Application Overview The PCM3070 offers a wide range of configuration options. Figure 1 shows the basic functional blocks of the device. Device Connections Digital Pins Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a default function, and also can be reprogrammed to cover alternative functions for various applications. The fixed-function pins are Reset and the SPI_Select pin, which are HW control pins. Depending on the state of SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI protocol. Other digital IO pins can be configured for various functions via register control. An overview of available functionality is given in Multifunction Pins. Analog Pins Analog functions can also be configured to a large degree. Analog blocks are powered down by default. The blocks can be powered up with fine granularity according to the application needs. 22 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Multifunction Pins Table 8 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO). Table 8. Multifunction Pin Assignments Pin Function A 2 3 4 5 6 7 8 MCLK BCLK WCLK DIN MFP1 DOUT MFP2 MFP3/ SCLK MFP4/ MISO GPIO MFP5 S (1) S (2) PLL Input B Codec Clock Input C I2S BCLK input D 1 2 I S BCLK output 2 E I S WCLK input F I2S WCLK output S (1) ,D (4) S S (3) E (2) S (3) S (2),D E (5) E, D E 2 G I S ADC word clock input H I2S ADC WCLK out E I I2S DIN J I2S DOUT K General Purpose Output I K General Purpose Output II K General Purpose Output III L General Purpose Input I L General Purpose Input II L General Purpose Input III M INT1 output E E E N INT2 output E E E Q Secondary I2S BCLK input E E, D E, D E E E E E E 2 E E E R Secondary I S WCLK in E S Secondary I2S DIN E T Secondary I2S DOUT U Secondary I2S BCLK OUT Secondary I S WCLK OUT W Reserved X Aux Clock Output E E 2 V (1) (2) (3) (4) (5) E E E E E E E E E E E S(1): The MCLK pin can be used to drive the PLL and Codec Clock inputs simultaneously S(2): The BCLK pin can be used to drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously S(3): The GPIO/MFP5 pin can be used to drive the PLL and Codec Clock inputs simultaneously D: Default Function E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if GPIO/MFP5 has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time) Analog Audio I/O The analog I/O path of the PCM3070 features a large set of options for signal conditioning as well as signal routing: • 6 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration • 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB • 2 mixer amplifiers for analog bypass • 2 low power analog bypass channels • Mute function • Automatic gain control (AGC) • Channel-to-channel phase adjustment Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 23 PCM3070 SLAS724 – FEBRUARY 2011 • • www.ti.com Fast charge of ac-coupling capacitors Anti thump Analog Bypass The PCM3070 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC resources are required for such operation. In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs INL to the left headphone amplifier (HPL) and INR to HPR. ADC Bypass Using Mixer Amplifiers In addition to the analog bypass mode, there is a bypass mode that uses the programmable gain amplifiers of the input stage in conjunction with a mixer amplifier. With this mode, low-level signals can be amplified and routed to the line or headphone outputs, fully bypassing the ADC and DAC. To enable this mode, the mixer amplifiers are powered on via software command. Headphone Outputs The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in single-ended AC-coupled headphone configurations, or loads down to 32Ω in differential mode, where a speaker is connected between HPL and HPR. In single-ended drive configuration these drivers can drive up to 15mW power into each headphone channel while operating from 1.8V analog supplies. While running from the AVdd supply, the output common-mode of the headphone driver is set by the common-mode setting of analog inputs in Page 1 / Register 10, Bit D6, to allow maximum utilization of the analog supply range while simultaneously providing a higher output-voltage swing. In cases when higher output-voltage swing is required, the headphone amplifiers can run directly from the higher supply voltage on LDOIN input (up to 3.6V). To use the higher supply voltage for higher output signal swing, the output common-mode can be adjusted to either 1.25V, 1.5V or 1.65V by configuring Page 1 / Register 10, Bits D5-D4. When the common-mode voltage is configured at 1.65V and LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power into a 16Ω load. The headphone drivers are capable of driving a mixed combination of DAC signal and bypass from analog input INL and INR by configuring Page 1 / Register 12 and Page 1 / Register 13 respectively. The analog input signals can be attenuated up to 72dB before routing by configuring Page 1 / Register 22 and 23. The level of the DAC signal can be controlled using the digital volume control of the DAC in Page 0, Reg 65 and 66. To control the output-voltage swing of headphone drivers, the digital volume control provides a range of –6.0dB to +29.0dB (6) in steps of 1dB. These can be configured by programming Page 1 / Register 16 and 17. These level controls are not meant to be used as dynamic volume control, but more to set output levels during initial device configuration. Refer to for recommendations for using headphone volume control for achieving 0dB gain through the DAC channel with various configurations. Line Outputs The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the analog input common-mode setting or to 1.65V. With output common-mode setting of 1.65V and DRVdd_HP supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable. ADC The PCM3070 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter. The stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required. The ADC path of the PCM3070 features a large set of options for signal conditioning as well as signal routing: • 2 ADCs • 6 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration (6) 24 If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com • • • • • • • 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB 2 mixer amplifiers for analog bypass 2 analog bypass channels Fine gain adjust of digital channels with 0.1 dB step size Digital volume control with a range of -12 to +20dB Mute function Automatic gain control (AGC) In • • • • addition to the standard set of ADC features the PCM3070 also offers the following special functions: Channel-to-channel phase adjustment Fast charge of ac-coupling capacitors Anti thump Adaptive filter mode ADC Processing The PCM3070 ADC channel includes a built-in digital decimation filter to process the oversampled data from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay and sampling rate. ADC Processing Blocks The PCM3070 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied. Table 9 gives an overview of the available processing blocks of the ADC channel and their properties. The signal processing blocks available are: • First-order IIR • Scalable number of biquad filters • Variable-tap FIR filter • AGC The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column (RC) gives an approximate indication of power consumption. Table 9. ADC Processing Blocks Processing Blocks Channel Decimation Filter 1st Order IIR Available Number BiQuads FIR Required AOSR Value Resource Class PRB_R1 (1) Stereo A Yes 0 No 128,64 6 PRB_R2 Stereo A Yes 5 No 128,64 8 PRB_R3 Stereo A Yes 0 25-Tap 128,64 8 PRB_R4 Right A Yes 0 No 128,64 3 PRB_R5 Right A Yes 5 No 128,64 4 PRB_R6 Right A Yes 0 25-Tap 128,64 4 PRB_R7 Stereo B Yes 0 No 64 3 PRB_R8 Stereo B Yes 3 No 64 4 PRB_R9 Stereo B Yes 0 20-Tap 64 4 PRB_R10 Right B Yes 0 No 64 2 PRB_R11 Right B Yes 3 No 64 2 (1) Default Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 25 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 9. ADC Processing Blocks (continued) Processing Blocks Channel Decimation Filter 1st Order IIR Available Number BiQuads FIR Required AOSR Value Resource Class PRB_R12 Right B Yes 0 20-Tap 64 2 PRB_R13 Stereo C Yes 0 No 32 3 PRB_R14 Stereo C Yes 5 No 32 4 PRB_R15 Stereo C Yes 0 25-Tap 32 4 PRB_R16 Right C Yes 0 No 32 2 PRB_R17 Right C Yes 5 No 32 2 PRB_R18 Right C Yes 0 25-Tap 32 2 For more detailed information see the PCM3070 Application Reference Guide, SLAU332. 26 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com DAC The PCM3070 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize performance, the PCM3070 allows the system designer to program the oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates. The PCM3070 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on required frequency response, group delay and sampling rate. The DAC path of the PCM3070 features many options for signal conditioning and signal routing: • 2 headphone amplifiers – Usable in single-ended or differential mode – Analog volume setting with a range of -6 to +29 dB • 2 line-out amplifiers – Usable in single-ended or differential mode – Analog volume setting with a range of -6 to +29 dB • Digital volume control with a range of -63.5 to +24dB • Mute function • Dynamic range compression (DRC) In • • • addition to the standard set of DAC features the PCM3070 also offers the following special features: Built in sine wave generation (beep generator) Digital auto mute Adaptive filter mode DAC Processing Blocks — Overview The PCM3070 implements signal processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied. Table 10 gives an overview over all available processing blocks of the DAC channel and their properties. The Resource Class Column (RC) gives an approximate indication of power consumption. The signal processing blocks available are: • First-order IIR • Scalable number of biquad filters • 3D – Effect • Beep Generator The processing blocks are tuned for typical cases and can achieve high image rejection or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. The Resource Class Column (RC) gives an approximate indication of power consumption. Table 10. Overview – DAC Predefined Processing Blocks (1) Processing Block No. Interpolation Filter Channel 1st Order IIR Available Num. of Biquads PRB_P1 (1) A PRB_P2 A DRC 3D Beep Generator Stereo No Stereo Yes Resource Class 3 No No No 8 6 Yes No No 12 Default Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 27 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 10. Overview – DAC Predefined Processing Blocks (continued) Processing Block No. Interpolation Filter Channel 1st Order IIR Available Num. of Biquads DRC 3D Beep Generator Resource Class PRB_P3 A Stereo Yes 6 No No No 10 PRB_P4 A Left No 3 No No No 4 PRB_P5 A Left Yes 6 Yes No No 6 PRB_P6 A Left Yes 6 No No No 6 PRB_P7 B Stereo Yes 0 No No No 6 PRB_P8 B Stereo No 4 Yes No No 8 PRB_P9 B Stereo No 4 No No No 8 PRB_P10 B Stereo Yes 6 Yes No No 10 PRB_P11 B Stereo Yes 6 No No No 8 PRB_P12 B Left Yes 0 No No No 3 PRB_P13 B Left No 4 Yes No No 4 PRB_P14 B Left No 4 No No No 4 PRB_P15 B Left Yes 6 Yes No No 6 PRB_P16 B Left Yes 6 No No No 4 PRB_P17 C Stereo Yes 0 No No No 3 PRB_P18 C Stereo Yes 4 Yes No No 6 PRB_P19 C Stereo Yes 4 No No No 4 PRB_P20 C Left Yes 0 No No No 2 PRB_P21 C Left Yes 4 Yes No No 3 PRB_P22 C Left Yes 4 No No No 2 PRB_P23 A Stereo No 2 No Yes No 8 PRB_P24 A Stereo Yes 5 Yes Yes No 12 PRB_P25 A Stereo Yes 5 Yes Yes Yes 12 For more detailed information see the PCM3070 Application Reference Guide, SLAU332. Digital Audio I/O Interface Audio data is transferred between the host processor and the PCM3070 via the digital audio data serial interface, or audio bus. The audio bus on this device is very flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. The audio bus of the PCM3070 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27, D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0, Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple PCM3070s may share the same audio bus. The PCM3070 also includes a feature to offset the position of start of data transfer with respect to the word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0, Register 28. The PCM3070 also has the feature of inverting the polarity of the bit-clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. This can be configured via Page 0, Register 29, D(3). 28 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com The PCM3070 further includes programmability (Page 0, Register 27, D0) to place the DOUT line into a hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z output condition. By default when the word-clocks and bit-clocks are generated by the PCM3070, these clocks are active only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the system as general-purpose clocks. Clock Generation and PLL The PCM3070 supports a wide range of options for generating clocks for the ADC and DAC sections as well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference clocks on MCLK BCLK or GPIO, the PCM3070 also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the PCM3070 provides several programmable clock dividers to help achieve a variety of sampling rates for ADC, DAC and clocks for the miniDSP . For more detailed information see the PCM3070 Application Reference Guide, SLAU332. Control Interfaces The PCM3070 control interface supports SPI or I2C communication protocols, with the protocol selectable using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low. It is not recommended to change the state of SPI_SELECT during device operation. I2C Control The PCM3070 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. SPI Control In the SPI control mode, the PCM3070 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO, SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the PCM3070) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. For more detailed information see the PCM3070 Application Reference Guide, SLAU332. Power Supply To power up the device, a 3.3V system rail (1.9V to 3.6V) can be used. The IOVDD voltage can be in the range of 1.1V - 3.6V. Internal LDOs generate the appropriate digital core voltage of 1.65V and analog core voltage of 1.8V (minimum 1.5V). For maximum flexibility, the respective voltages can also be supplied externally, bypassing the built-in LDOs. To support high-output drive capabilities, the output stages of the output amplifiers can either be driven from the analog core voltage or the 1.9…3.6V rail used for the LDO inputs (LDO_in). Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 29 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com For more detailed information see the PCM3070 Application Reference Guide, SLAU332. Device Special Functions The following special functions are available to support advanced system requirements: • Interrupt generation • Flexible pin multiplexing For more detailed information see the PCM3070 Application Reference Guide, SLAU332. MiniDSP The PCM3070 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each miniDSP can run up to 1152 instructions on every audio sample at a 48kHz sample rate. The two cores can run fully synchronized and can exchange data. Software Software development for the PCM3070 is supported through TI's comprehensive PurePath Studio Development Environment; a powerful, easy-to-use tool designed specifically to simplify software development on the PCM3070 miniDSP audio platform. The Graphical Development Environment consists of a library of common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse. Please visit the PCM3070 product folder on www.ti.com to learn more about PurePath Studio and the latest status on available, ready-to-use DSP algorithms. Register Map Summary Table 11. Summary of Register Map Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 0 0 0x00 0x00 Page Select Register 0 1 0x00 0x01 Software Reset Register 0 2 0x00 0x02 Reserved Register 0 3 0x00 0x03 Reserved Register 0 4 0x00 0x04 Clock Setting Register 1, Multiplexers 0 5 0x00 0x05 Clock Setting Register 2, PLL P&R Values 0 6 0x00 0x06 Clock Setting Register 3, PLL J Values 0 7 0x00 0x07 Clock Setting Register 4, PLL D Values (MSB) 0 8 0x00 0x08 Clock Setting Register 5, PLL D Values (LSB) 0 9-10 0x00 0x09-0x0A Reserved Register 0 11 0x00 0x0B Clock Setting Register 6, NDAC Values 0 12 0x00 0x0C Clock Setting Register 7, MDAC Values 0 13 0x00 0x0D DAC OSR Setting Register 1, MSB Value 0 14 0x00 0x0E DAC OSR Setting Register 2, LSB Value 0 15 0x00 0x0F miniDSP_D Instruction Control Register 1 0 16 0x00 0x10 miniDSP_D Instruction Control Register 2 0 17 0x00 0x11 miniDSP_D Interpolation Factor Setting Register 0 18 0x00 0x12 Clock Setting Register 8, NADC Values 0 19 0x00 0x13 Clock Setting Register 9, MADC Values 0 20 0x00 0x14 ADC Oversampling (AOSR) Register 0 21 0x00 0x15 miniDSP_A Instruction Control Register 1 30 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 0 22 0x00 0x16 miniDSP_A Instruction Control Register 2 0 23 0x00 0x17 miniDSP_A Decimation Factor Setting Register 0 24 0x00 0x18 Reserved Register 0 25 0x00 0x19 Clock Setting Register 10, Multiplexers 0 26 0x00 0x1A Clock Setting Register 11, CLKOUT M divider value 0 27 0x00 0x1B Audio Interface Setting Register 1 0 28 0x00 0x1C Audio Interface Setting Register 2, Data offset setting 0 29 0x00 0x1D Audio Interface Setting Register 3 0 30 0x00 0x1E Clock Setting Register 12, BCLK N Divider 0 31 0x00 0x1F Audio Interface Setting Register 4, Secondary Audio Interface 0 32 0x00 0x20 Audio Interface Setting Register 5 0 33 0x00 0x21 Audio Interface Setting Register 6 0 34 0x00 0x22 Digital Interface Misc. Setting Register 0 35 0x00 0x23 Reserved Register 0 36 0x00 0x24 ADC Flag Register 0 37 0x00 0x25 DAC Flag Register 1 0 38 0x00 0x26 DAC Flag Register 2 0 39-41 0x00 0x27-0x29 Reserved Register 0 42 0x00 0x2A Sticky Flag Register 1 0 43 0x00 0x2B Interrupt Flag Register 1 0 44 0x00 0x2C Sticky Flag Register 2 0 45 0x00 0x2D Sticky Flag Register 3 0 46 0x00 0x2E Interrupt Flag Register 2 0 47 0x00 0x2F Interrupt Flag Register 3 0 48 0x00 0x30 INT1 Interrupt Control Register 0 49 0x00 0x31 INT2 Interrupt Control Register 0 50-51 0x00 0x32-0x33 Reserved Register 0 52 0x00 0x34 GPIO/MFP5 Control Register 0 53 0x00 0x35 DOUT/MFP2 Function Control Register 0 54 0x00 0x36 DIN/MFP1 Function Control Register 0 55 0x00 0x37 MISO/MFP4 Function Control Register 0 56 0x00 0x38 SCLK/MFP3 Function Control Register 0 57-59 0x00 0x39-0x3B Reserved Registers 0 60 0x00 0x3C DAC Signal Processing Block Control Register 0 61 0x00 0x3D ADC Signal Processing Block Control Register 0 62 0x00 0x3E miniDSP_A and miniDSP_D Configuration Register 0 63 0x00 0x3F DAC Channel Setup Register 1 0 64 0x00 0x40 DAC Channel Setup Register 2 0 65 0x00 0x41 Left DAC Channel Digital Volume Control Register 0 66 0x00 0x42 Right DAC Channel Digital Volume Control Register 0 67 0x00 0x43 RESERVED 0 68 0x00 0x44 DRC Control Register 1 0 69 0x00 0x45 DRC Control Register 2 0 70 0x00 0x46 DRC Control Register 3 0 71 0x00 0x47 Beep Generator Register 1 0 72 0x00 0x48 Beep Generator Register 2 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 31 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 0 73 0x00 0x49 Beep Generator Register 3 0 74 0x00 0x4A Beep Generator Register 4 0 75 0x00 0x4B Beep Generator Register 5 0 76 0x00 0x4C Beep Generator Register 6 0 77 0x00 0x4D Beep Generator Register 7 0 78 0x00 0x4E Beep Generator Register 8 0 79 0x00 0x4F Beep Generator Register 9 0 80 0x00 0x50 Reserved Register 0 81 0x00 0x51 ADC Channel Setup Register 0 82 0x00 0x52 ADC Fine Gain Adjust Register 0 83 0x00 0x53 Left ADC Channel Volume Control Register 0 84 0x00 0x54 Right ADC Channel Volume Control Register 0 85 0x00 0x55 ADC Phase Adjust Register 0 86 0x00 0x56 Left Channel AGC Control Register 1 0 87 0x00 0x57 Left Channel AGC Control Register 2 0 88 0x00 0x58 Left Channel AGC Control Register 3 0 89 0x00 0x59 Left Channel AGC Control Register 4 0 90 0x00 0x5A Left Channel AGC Control Register 5 0 91 0x00 0x5B Left Channel AGC Control Register 6 0 92 0x00 0x5C Left Channel AGC Control Register 7 0 93 0x00 0x5D Left Channel AGC Control Register 8 0 94 0x00 0x5E Right Channel AGC Control Register 1 0 95 0x00 0x5F Right Channel AGC Control Register 2 0 96 0x00 0x60 Right Channel AGC Control Register 3 0 97 0x00 0x61 Right Channel AGC Control Register 4 0 98 0x00 0x62 Right Channel AGC Control Register 5 0 99 0x00 0x63 Right Channel AGC Control Register 6 0 100 0x00 0x64 Right Channel AGC Control Register 7 0 101 0x00 0x65 Right Channel AGC Control Register 8 0 102 0x00 0x66 DC Measurement Register 1 0 103 0x00 0x67 DC Measurement Register 2 0 104 0x00 0x68 Left Channel DC Measurement Output Register 1 0 105 0x00 0x69 Left Channel DC Measurement Output Register 2 0 106 0x00 0x6A Left Channel DC Measurement Output Register 3 0 107 0x00 0x6B Right Channel DC Measurement Output Register 1 0 108 0x00 0x6C Right Channel DC Measurement Output Register 2 0 109 0x00 0x6D Right Channel DC Measurement Output Register 3 0 110-127 0x00 0x6E-0x7F Reserved Register 1 0 0x01 0x00 Page Select Register 1 1 0x01 0x01 Power Configuration Register 1 2 0x01 0x02 LDO Control Register 1 3 0x01 0x03 Playback Configuration Register 1 1 4 0x01 0x04 Playback Configuration Register 2 1 5-8 0x01 0x05-0x08 Reserved Register 1 9 0x01 0x09 Output Driver Power Control Register 1 10 0x01 0x0A Common Mode Control Register 32 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 1 11 0x01 0x0B Over Current Protection Configuration Register 1 12 0x01 0x0C HPL Routing Selection Register 1 13 0x01 0x0D HPR Routing Selection Register 1 14 0x01 0x0E LOL Routing Selection Register 1 15 0x01 0x0F LOR Routing Selection Register 1 16 0x01 0x10 HPL Driver Gain Setting Register 1 17 0x01 0x11 HPR Driver Gain Setting Register 1 18 0x01 0x12 LOL Driver Gain Setting Register 1 19 0x01 0x13 LOR Driver Gain Setting Register 1 20 0x01 0x14 Headphone Driver Startup Control Register 1 21 0x01 0x15 Reserved Register 1 22 0x01 0x16 IN1L to HPL Volume Control Register 1 23 0x01 0x17 IN1R to HPR Volume Control Register 1 24 0x01 0x18 Mixer Amplifier Left Volume Control Register 1 25 0x01 0x19 Mixer Amplifier Right Volume Control Register 1 26-50 0x01 0x1A-0x32 Reserved Register 1 51 0x01 0x33 Rerved. Do Not Use 1 52 0x01 0x34 Left PGA Positive Terminal Input Routing Configuration Register 1 53 0x01 0x35 Reserved Register 1 54 0x01 0x36 Left PGA Negative Terminal Input Routing Configuration Register 1 55 0x01 0x37 Right PGA Positive Terminal Input Routing Configuration Register 1 56 0x01 0x38 Reserved Register 1 57 0x01 0x39 Right PGA Negative Terminal Input Routing Configuration Register 1 58 0x01 0x3A Floating Input Configuration Register 1 59 0x01 0x3B Left PGA Volume Control Register 1 60 0x01 0x3C Right PGA Volume Control Register 1 61 0x01 0x3D Reserved. Do Not Use 1 62 0x01 0x3E ADC Analog Volume Control Flag Register 1 63 0x01 0x3F DAC Analog Gain Control Flag Register 1 64-70 0x01 0x40-0x46 Reserved Register 1 71 0x01 0x47 Analog Input Quick Charging Configuration Register 1 72-122 0x01 0x48-0x7A Reserved Register 1 123 0x01 0x7B Reference Power-up Configuration Register 1 124-127 0x01 0x7C-0x7F Reserved Register 8 0 0x08 0x00 Page Select Register 8 1 0x08 0x01 ADC Adaptive Filter Configuration Register 8 2-7 0x08 0x02-0x07 Reserved 8 8-127 0x08 0x08-0x7F ADC Coefficients Buffer-A C(0:29) 9-16 0 0x09-0x10 0x00 Page Select Register 9-16 1-7 0x09-0x10 0x01-0x07 Reserved 9-16 8-127 0x09-0x10 0x08-0x7F ADC Coefficients Buffer-A C(30:255) 26-34 0 0x1A-0x22 0x00 Page Select Register 26-34 1-7 0x1A-0x22 0x01-0x07 Reserved. 26-34 8-127 0x1A-0x22 0x08-0x7F ADC Coefficients Buffer-B C(0:255) 44 0 0x2C 0x00 Page Select Register 44 1 0x2C 0x01 DAC Adaptive Filter Configuration Register Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 33 PCM3070 SLAS724 – FEBRUARY 2011 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 44 2-7 0x2C 0x02-0x07 Reserved 44 8-127 0x2C 0x08-0x7F DAC Coefficients Buffer-A C(0:29) 45-52 0 0x2D-0x34 0x00 Page Select Register 45-52 1-7 0x2D-0x34 0x01-0x07 Reserved. 45-52 8-127 0x2D-0x34 0x08-0x7F DAC Coefficients Buffer-A C(30:255) 62-70 0 0x3E-0x46 0x00 Page Select Register 62-70 1-7 0x3E-0x46 0x01-0x07 Reserved. 62-70 8-127 0x3E-0x46 0x08-0x7F DAC Coefficients Buffer-B C(0:255) 80-114 0 0x50-0x72 0x00 Page Select Register 80-114 1-7 0x50-0x72 0x01-0x07 Reserved. 80-114 8-127 0x50-0x72 0x08-0x7F miniDSP_A Instructions 152-186 0 0x98-0xBA 0x00 Page Select Register 152-186 1-7 0x98-0xBA 0x01-0x07 Reserved. 152-186 8-127 0x98-0xBA 0x08-0x7F miniDSP_D Instructions 34 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): PCM3070 PACKAGE OPTION ADDENDUM www.ti.com 3-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) PCM3070IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM3070IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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