TI TPS51206

TPS51206
SLUSAH1 – MAY 2011
www.ti.com
2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For
DDR2, DDR3 and DDR3L
Check for Samples: TPS51206
FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
Supply Input Voltage: Supports 3.3-V Rail and
5-V Rail
VLDOIN Input Voltage Range: VTT+0.4 V to
3.5 V
VTT Termination Regulator
– Output Voltage Range: 0.5 V to 0.9 V
– 2-A Peak Sink and Source Current
– Requires Only 10-μF MLCC Output
Capacitor
– ±20 mV Accuracy
VTTREF Buffered Reference
– VDDQ/2 ± 1% Accuracy
– 10-mA Sink/Source Current
Supports High-Z in S3 and Soft-Stop in S4/S5
with S3/S5 Inputs
Over Temperature Protection
10-pin 2mm x 2mm SON(DSQ) Package
DDR2/DDR3/DDR3L Memory Power Supplies
SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination
DESCRIPTION
The TPS51206 is a sink/source double date rate
(DDR) termination regulator with VTTREF buffered
reference output. It is specifically designed for low
input voltage, low cost, low external component count
systems where space is a key consideration. The
TPS51206 maintains fast transient response and only
requires 1 × 10-µF of ceramic output capacitance.
The TPS51206 supports a remote sensing function
and all power requirements for DDR2, DDR3 and
Low-Power DDR3 (DDR3L) VTT bus. The VTT
current capability is ±2A peak. The TPS51206
supports all of the DDR power states, putting VTT to
High-Z in S3 state (suspend to RAM) and discharging
VTT and VTTREF in S4/S5 state (suspend to disk).
The TPS51206 is available in 10-pin, 2x2, SON
(DSQ) PowerPAD™ package and specified
from –40°C to 85°C.
SIMPLIFIED APPLICATION
TPS51206
VDDQ
1
VDDQSNS
2
VLDOIN
S3_SLP
7
S3
S5_SLP
9
S5
5 V or 3.3 V
Supply
VTT
3
VTTSNS
5
PGND
4
VTTREF
6
GND
8
VTT
VTTREF
10 VDD
PowerPad
UDG-11024
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS51206
SLUSAH1 – MAY 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1) (2)
TA
PACKAGE
–40°C to 85°C
Plastic SON
(1)
(2)
ORDERABLE
DEVICE NUMBER
TPS51206DSQR
TPS51206DSQT
PINS
OUTPUT SUPPLY
10
Tape and Reel
QUANTITY
3000
250
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
MIN
Input voltage range (2)
Output voltage range (2)
VDD, S3, S5
–0.3
7
VLDOIN, VTTSNS, VDDQSNS
–0.3
3.6
PGND
–0.3
0.3
VTT, VTTREF
–0.3
3.6
HBM QSS 009-105 (JESD22-A114A)
Electrostatic discharge
CDM QSS 009-147 (JESD22-C101B.01)
Junction temperature, TJ
–55
Operating free-air temperature, TA
(1)
(2)
MAX
UNIT
V
V
2
kV
500
V
125
˚C
150
˚C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage
Input voltage range
Output voltage
range (1)
VDD
(1)
MAX
UNIT
6.5
V
S3, S5
–0.1
6.5
V
VLDOIN, VTTSNS, VDDQSNS
–0.1
3.5
PGND
–0.1
0.1
VTT, VTTREF
–0.1
3.5
V
–40
85
°C
Operating free-air temperature, TA
(1)
TYP
3.1
All voltage values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
TPS51206
THERMAL METRIC
(1)
DSQ
UNITS
10 PINS
θJA
Junction-to-ambient thermal resistance
70.3
θJCtop
Junction-to-case (top) thermal resistance
46.3
θJB
Junction-to-board thermal resistance
33.8
ψJT
Junction-to-top characterization parameter
2.9
ψJB
Junction-to-board characterization parameter
33.5
θJCbot
Junction-to-case (bottom) thermal resistance
16.3
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VVDD=5 V, VLDOIN is connected to VDDQSNS, VS3=VS5=5 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
μA
IVDD(S0)
VDD supply current, in S0
TA = 25°C, No load, VS3 = VS5 = 5 V, VVDDQSNS = 1.8 V
IVDD(S3)
VDD supply current, in S3
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VVDDQSNS = 1.8 V
170
IVDDSDN
VDD shutdown current, in S4/S5
TA = 25°C, No load, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V
1
μA
IVLDOIN(S0)
VLDOIN supply current, in S0
TA = 25°C, No load, VS3 = VS5 = 5 V, VLDION = 1.8 V
5
μA
IVLDOIN(s3)
VLDOIN supply current, in S3
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VLDION = 1.8 V
5
μA
IVLDOINSDN
VLDOIN shutdown current, in S4/S5
TA = 25°C, No load, VS3 = VS5 = 0 V, VLDION = 1.8 V
5
μA
μA
80
VTTREF OUTPUT
VVTTREF
Output voltage
VVDDQSNS/2
VVTTREFTOL
Output voltage tolerance to
VVDDQSNS
|IVTTREF|< 10 mA, 1.5 V ≤ VVDDQSNS ≤ 1.8 V
IVTTREFSRC
Source current
VVDDQSNS = 1.8 V, VVTTREF = 0 V
10
IVTTREFSNK
Sink current
VVDDQSNS = 0 V, VVTTREF = 1.8 V
10
IVTTREFDIS
VTTREF Discharge current
TA = 25°C, VS3 = VS5 = 0V, VVTTREF = 0.5V
49%
|IVTTREF|< 10 mA, 1.2 V ≤ VVDDQSNS < 1.5 V
48.75%
50%
V
51%
51.25%
mA
mA
1.3
mA
VTT OUTPUT
VVTT
Output voltage
VVTTTOL
Output voltage tolerance to
VVDDQSNS/2
VVDDQSNS/2
V
|IVTT|≤ 10 mA, 1.4 V ≤ VVDDQSNS ≤ 1.8 V
–20
20
|IVTT|< 1 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V (1)
–30
30
|IVTT|< 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V (1)
–40
40
|IVTT|≤ 10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.4 V
–20
20
|IVTT|< 1 A, 1.2 V ≤ VVDDQSNS ≤ 1.4 V (1)
–30
30
|IVTT|< 1.5 A, 1.2 V ≤ VVDDQSNS < 1.4 V (1)
–40
40
IVTTOCLSRC
Source current limit
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V
2
IVTTOCLSNK
Sink current limit
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 1.1 V
2
IVTTLK
Leakage current
TA = 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF
IVTTSNSBIAS
VTTSNS input bias current
VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF
IVTTSNSLK
VTTSNS leakage current
VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF
IVTTDIS
VTT Discharge current
TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V, VVTT = 0.5 V
VDDQSNS input current
mV
A
A
5
μA
–0.1
0.1
μA
–0.1
0.1
μA
7
mA
VVDDQSNS = 1.8 V
30
μA
Wake up
2.9
V
Hysteresis
0.2
VDDQ INPUT
IVDDQSNS
UVLO/LOGIC THRESHOLD
VVDDUV
VDD UVLO threshold voltage
VLL
S3/S5 low-level voltage
VLH
S3/S5 high-level voltage
VLHYST
S3/S5 hysteresis voltage
ILHLK
S3/S5 input leak current
0.5
1.8
V
V
0.3
–1
V
1
μA
OVER-TEMPERATURE PROTECTION
TOTP
(1)
Over temperature protection
Shutdown temperature (1)
Hysteresis (1)
150
10
°C
Ensured by design. Not production tested.
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DEVICE INFORMATION
DSQ PACKAGE (TOP VIEW)
VDDQSNS
1
10
VLDOIN
2
9
S5
VTT
3
8
GND
PGND
4
7
S3
VTTSNS
5
6
VTTREF
Power
PAD
VDD
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
GND
8
–
Signal ground
PGND
4
–
Power GND for VTT LDO
S3
7
I
S3 signal input
S5
9
I
S5 signal input
VDD
10
I
Device power supply input (3.3 V or 5 V)
VDDQSNS
1
I
VDDQ sense input, reference input for VTTREF
VLDOIN
2
I
Power supply input for VTT/ VTTREF
VTT
3
O
Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability
VTTREF
6
O
VTTREF buffered reference output. Need to connect 0.22-µF or greater MLCC for stability
VTTSNS
5
I
VTT LDO voltage sense input
Pad
–
–
Solder to the ground plane for increased thremal performance.
4
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FUNCTIONAL BLOCK DIAGRAM
VLDOIN
2
VDDQSNS
1
+
6
VTTREF
3
VTT
4
PGND
+
GND
GND
8
VTTREF Disharge
OTP-OK
GND
VTT Disharge
OTP
GND
VDD 10
+
EN-VTTREF
2.9V/2.7 V
S5
+
9
+
EN-VTT
S3
7
VTTSNS
5
+
TPS51206
GND
UDG-11025
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TYPICAL CHARACTERISTICS
300
5
VDD Shutdown Current (µA)
VDD Supply Current (µA)
250
200
150
100
50
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
4
3
2
1
0
−40 −25 −10
110 125
Figure 1. VDD Supply Current vs. Junction Temperature
VLDOIN Shutdown Current (µA)
VLDOIN Supply Current (µA)
110 125
5
4
3
2
1
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
2
1
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
0.770
TA = −40°C
TA = 25°C
TA = 85°C
0.915
VTTREF Voltage (V)
0.905
0.900
0.895
0.890
VVDDQSNS = 1.8 V
VVDD = 5 V
−8
−6
−4
−2
0
2
4
VTTREF Current (mA)
0.760
0.755
0.750
0.745
0.740
0.735
6
8
Figure 5. VTTREF Load Regulation (0.9 V)
TA = −40°C
TA = 25°C
TA = 85°C
0.765
0.910
0.880
−10
3
Figure 4. VLDOIN Shutdown Current vs. Junction
Temperature
0.920
0.885
4
0
−40 −25 −10
110 125
Figure 3. VLDOIN Supply Current vs. Junction
Temperature
VTTREF Voltage (V)
95
Figure 2. VDD Shutdown Current vs. Junction
Temperature
5
6
5
20 35 50 65 80
Junction Temperature (°C)
10
VVDDQSNS = 1.5 V
VVDD = 5 V
0.730
−10
−8
−6
−4
−2
0
2
4
VTTREF Current (mA)
6
8
10
Figure 6. VTTREF Load Regulation (0.75 V)
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TYPICAL CHARACTERISTICS (continued)
0.690
0.615
TA = −40°C
TA = 25°C
TA = 85°C
0.610
VTTREF Voltage (V)
VTTREF Voltage (V)
0.685
0.680
0.675
0.670
0.665
−8
−6
0.605
0.600
0.595
0.590
VVDDQSNS = 1.35 V
VVDD = 5 V
0.660
−10
−4
−2
0
2
4
VTTREF Current (mA)
6
8
TA = −40°C
TA = 25°C
TA = 85°C
VVDDQSNS = 1.2 V
VVDD = 5 V
0.585
−10
10
−8
Figure 7. VTTREF Load Regulation (0.675 V)
8
10
TA = −40°C
TA = 25°C
TA = 85°C
0.790
0.780
0.920
VTT Voltage (V)
VTT Voltage (V)
0.930
0.910
0.900
0.890
0.880
0.870
0.770
0.760
0.750
0.740
0.730
0.720
VVDDQSNS = 1.8 V
VVDD = 5 V
0.850
−2.0
−1.5
−1.0
0.710
−0.5
0.0
0.5
VTT Current (A)
1.0
1.5
VVDDQSNS = 1.5 V
VVDD = 5 V
0.700
−2.0
2.0
Figure 9. VTT Load Regulation (0.9 V)
−1.5
−1.0
−0.5
0.0
0.5
VTT Current (A)
1.0
1.5
2.0
Figure 10. VTT Load Regulation (0.75 V)
0.725
0.650
TA = −40°C
TA = 25°C
TA = 85°C
0.715
0.705
TA = −40°C
TA = 25°C
TA = 85°C
0.640
0.630
0.695
VTT Voltage (V)
VTT Voltage (V)
6
0.800
TA = −40°C
TA = 25°C
TA = 85°C
0.940
0.685
0.675
0.665
0.655
0.645
0.635
−4
−2
0
2
4
VTTREF Current (mA)
Figure 8. VTTREF Load Regulation (0.6 V)
0.950
0.860
−6
0.620
0.610
0.600
0.590
0.580
0.570
VVDDQSNS = 1.35 V
VVDD = 5 V
0.625
−1.5
−1.0
−0.5
0.0
0.5
VTT Current (A)
0.560
1.0
1.5
VVDDQSNS = 1.2 V
VVDD = 5 V
0.550
−1.5
Figure 11. VTT Load Regulation (0.675 V)
−1.0
−0.5
0.0
0.5
VTT Current (A)
1.0
Figure 12. VTT Load Regulation (0.6 V)
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TYPICAL CHARACTERISTICS (continued)
VVTTREF(10 mV/div) 0.9 V offset
VVTTREF(10 mV/div) 0.75 V offset
VVTT
VVTT
(20 mV/div)
0.9 V offset
(20 mV/div)
0.75 V offset
VVDDQSNS
VVDDQSNS
(50 mV/div)
1.8 V offset
(50 mV/div)
1.5 V offset
IVTT
(2 A/div)
IVTT
(2 A/div)
Time (200 ms/div)
Time (200 ms/div)
Figure 13. VTT Load Transient Response (0.9 V)
Figure 14. VTT Load Transient Response (0.75 V)
VVTTREF(10 mV/div) 0.6 V offset
VVTTREF(10 mV/div) 0.675 V offset
VVTT
VVTT
(20 mV/div)
0.675 V offset
(20 mV/div)
0.6 V offset
VVDDQSNS
VVDDQSNS
(50 mV/div)
1.2 V offset
(50 mV/div)
1.35 V offset
IVTT
(2 A/div)
IVTT
(2 A/div)
Time (200 ms/div)
Time (200 ms/div)
80
180
135
60
135
40
90
40
90
20
45
20
45
0
0
0
0
−20
−45
−60
−80
1000
−90
Sink: −1 A
VVDD = 5 V
VVDDQSNS = 1.5 V
Gain
Phase
10000
100000
Frequency (Hz)
1000000
−135
−180
10000000
Figure 17. VTT (Sink: -1 A) Bode Plot (0.75 V)
−20
−45
−40
Phase (°)
180
60
Gain (dB)
80
−40
8
Figure 16. VTT Load Transient Response (0.6 V)
Phase (°)
Gain (dB)
Figure 15. VTT Load Transient Response (0.675 V)
−90
−60
Source: +1 A
VVDD = 5 V
VVDDQSNS = 1.5 V
Gain
Phase
−80
1000
10000
100000
Frequency (Hz)
1000000
−135
−180
10000000
Figure 18. VTT (Source: +1 A) Bode Plot (0.75V)
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TYPICAL CHARACTERISTICS (continued)
IVTTREF= 0 A
S5: Low to High
VVTTREF(500 mV/div)
VVTTREF(500 mV/div)
IVTTREF= 0 A
VVTT (500 mV/div)
IVTT = 0 A
S3: Low to High
VVTT (500 mV/div)
VS5 (5 V/div)
VS5 (5 V/div)
VS3 (5 V/div)
VS3 (5 V/div)
Time (40 ms/div)
Time (1 ms/div)
Figure 19. Start-Up Waveforms (S5: Low to High)
Figure 20. Start-Up Waveforms (S3: Low to High)
0.30
IVTTREF= 0 A
VVTT (500 mV/div)
0.25
VTT Dropout Voltage (V)
IVTT = 0 A
S3/S5: High to Low
VVTTREF (500 mV/div)
TA = 25°C
VVDD = 5 V
0.20
0.15
0.10
VOUT = 0.900 V
VOUT = 0.750 V
VOUT = 0.675 V
VOUT = 0.600 V
0.05
VS5 (5 V/div)
0.00
0.0
VS3 (5 V/div)
0.5
1.0
VTT Current (A)
1.5
2.0
Time (2 s/div)
Figure 21. Shutdown Waveforms (S3/ S5: High to Low)
Figure 22. VTT Dropout Voltage
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DETAILED DESCRIPTION
VTT SINK/SOURCE REGULATOR
The TPS51206 is a sink/source tracking termination regulator specifically designed for low input voltage, low
cost, and low external component count systems where space is a key application parameter. The TPS51206
integrates a high-performance, low-dropout (LDO) linear regulator (VTT) that has ultimate fast response to track
½ VDDQSNS within 40 mV at all conditions, and its current capability is 2 A for both sink and source directions.
A 10-µF (or greater) ceramic capacitor(s) need to be attached close to the VTT terminal for stable operation; X5R
or better grade is recommended. To achieve tight regulation with minimum effect of trace resistance, the remote
sensing terminal, VTTSNS, should be connected to the positive terminal of the output capacitor(s) as a separate
trace from the high current path from the VTT pin.
The TPS51206 has a dedicated pin, VLDOIN, for VTT power supply to minimize the LDO power dissipation on
user application. The minimum VLDOIN voltage is 0.4 V above the ½ VDDQSNS voltage.
VTTREF
The VTTREF pin includes 10 mA of sink/source current capability, and tracks ½ of VDDQSNS with ±1%
accuracy. A 0.22-µF ceramic capacitor needs to be attached close to the VTTREF terminal for stable operation;
X5R or better grade is recommended.
POWER STATE CONTROL
The TPS51206 has two input pins, S3 and S5, to provide simple control of the power state. Table 1 describes
S3/S5 terminal logic state and corresponding state of VTTREF/VTT outputs. VTT is turn-off and placed to high
impedance (High-Z) state in S3. The VTT output is floated and does not sink or source current in this state.
When both S5 and S3 pins are LOW, the power state is set to S4/S5. In S4/S5 state, all the outputs are turn-off
and discharged to GND.
Table 1. S3 and S5 Control Table
STATE
S3
S5
VTTREF
VTT
S0
HI
HI
ON
ON
S3
LO
HI
ON
OFF(High-Z)
S4/S5
LO
LO
OFF(Discharge)
OFF(Discharge)
VDD UNDERVOLTAGE LOCKOUT PROTECTION
The TPS51206 input voltage (VDD) includes undervoltage lockout protection (UVLO). When the VDD pin voltage
is lower than UVLO threshold voltage, VTT and VTTREF are shut off. This is non-latch protection.
OVER-TEMPERATURE PROTECTION
This device features internal temperature monitoring. If the temperature exceeds the threshold value, VTT and
VTTREF are shut off. This is a non-latch protection.
10
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VDD
VLDOIN
VDDQSNS
S5
VTTREF
S3
VTT
UDG-11136
Figure 23. Typical Timing Diagram
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APPLICATION INFORMATION
VDD CAPACITOR
Add a ceramic capacitor, with a value 0.1 µF (or greater) and X5R grade (or better), placed close to the VDD
terminal, to stabilize the bias supply voltage from any parasitic impedance from the power supply rail.
VLDOIN CAPACITOR
Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-µF (or greater) and
X5R grade (or better) ceramic capacitor to supply this transient charge.
VTTREF CAPACITOR
Add a ceramic capacitor, with a value 0.22 µF and X5R grade (or better), placed close to the VTTREF terminal
for stable operation.
VTT CAPACITOR
For stable operation, a 10-µF (or greater) and X5R (or better) grade ceramic capacitor(s) need to be attached
close to the VTT terminal. This capacitor is recommended to minimize any additional equivalent series resistance
(ESR) and/or equivalent series inductance (ESL) of ground trace between the PGND terminal and the VTT
capacitor(s).
VTTSNS CONNECTION
To achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, the VTTSNS pin
should be connected to the positive terminal of the VTT pin output capacitor(s) as a separate trace from the
high-current path from VTT. Consider adding a low-pass R-C filter at the VTTSNS pin in case the ESR of the
VTT output capacitor(s) is larger than 2 mΩ. The R-C filter time constant should be approximately the same or
slightly lower than the time constant of the VTT output capacitance and ESR.
TPS51206
VTT
3
VTT
RC
VTTSNS
5
CC
C3
10 mF
PGND
4
UDG-11137
Figure 24. R-C Filter for VTTSNS
VDDQSNS CONNECTION
VDDQSNS is a reference input of the VTTREF and VTT. Trace should be routed away from noise-generating
lines.
12
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THERMAL DESIGN
Because the TPS51206 is a linear regulator, the VTT current flows in both source and sink directions, thereby
dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN
and VTT times IVTT (VTT current) current becomes the power dissipation as shown in Equation 1.
PDISS(src) = (VVLDOIN - VVTT )´ IVTT(src)
(1)
In this case, if the VLDOIN pin is connected to an alternative power supply lower than the VDDQ voltage, overall
power loss can be reduced. For the sink phase, VTT voltage is applied across the internal LDO regulator, and
the power dissipation can be calculated by Equation 2.
PDISS(snk) = VVTT ´ IVTT(snk)
(2)
Maximum power dissipation allowed by the package is calculated by Equation 3.
TJ(max) - TA(max)
PPKG =
qJA
where
•
•
•
TJ(max) is +125°C
TA(max) is the maximum ambient temperature in the system
θJA is the thermal resistance from junction to ambient
(3)
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VDDQ Sense Input
VTT Power
Supply Input
LAYOUT CONSIDERATIONS
0.1 mF
0402
10 mF
0603
VDDQSNS
VDD
VLDOIN
S5
VTT
VTT Output
GND
PGND
10 mF
0603
5-V or 3.3-V Supply Input
S3
VTTSNS
VTTREF
0.22 mF
0402
VTTREF Output
Via to Ground Plane
Via for VTTSNS
Etch Beneath Component
UDG-11135
Figure 25. PCB Layout Guideline
Consider the following before beginning a TPS51206 layout design.
• The input bypass capacitor for VLDOIN should be placed as close as possible to the terminal with short and
wide connections.
• The output capacitor for VTT should be placed close to the terminals (VTT and PGND) with short and wide
connection in order to avoid additional ESR and/or ESL trace inductance.
• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high current VTT power trace. In addition, VTTSNS trace should be routed away from high current trace, on
the separate layer is recommended. This configuration is strongly recommended to avoid additional ESR
and/or ESL. If sensing the voltage at the point of the load is required, it is recommended to attach the output
capacitor(s) at that point. In addition, it is recommended to minimize any additional ESR and/or ESL of ground
trace between the GND pin and the VTT capacitor(s).
• The GND pin (and the negative node of the VTTREF output capacitor) and PGND pins (and the negative
node of the VTT output capacitor) should be connected to the internal system ground planes (for better result,
use at least two internal ground planes) with multiple vias. Use as many vias as possible to reduce the
impedance between GND/PGND and the system ground plane.
• In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the package thermal pad. The wide traces of the component and the side copper connected to the thermal
land pad help to dissipate heat. Numerous vias 0.33 mm in diameter connected from the thermal land to the
internal/solder side ground plane(s) should also be used to help dissipation. Please consult the
TPS51206-EVM User's Guide for more detailed layout recommendations.
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APPLICATION DIAGRAMS
Figure 26 shows an application diagram for a configuration where VLDOIN and VDDQ are connected.
TPS51206
VDDQ
1
VDDQSNS
2
VLDOIN
VTT
3
VTTSNS
5
VTT
C1
10 mF
C3
10 mF
S3_SLP
7
S3
S5_SLP
9
S5
PGND
4
VTTREF
6
C4
0.22 mF
10 VDD
5 V or 3.3 V
C2
0.1 mF
VTTREF
GND
8
PowerPad
UDG-11026
GND
Figure 26. VLDOIN=VDDQ Configuration
Table 2. VLDOIN=VDDQ Configuration Components
REFERENCE
DESIGNATOR
SPECIFICATION
MANUFACTURER
PART
NUMBER
C1, C3
10 µF, 6.3 V, X5R, 1608 (0603)
Taiyo Yuden
JMK107BJ106MA
C2
0.1 µF, 6.3 V, X5R, 1005 (0402)
Taiyo Yuden
JWK105BJ104MP
C4
0.22 µF, 6.3 V, X5R, 1005 (0402)
Taiyo Yuden
JMK105BJ224KV
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TPS51206
SLUSAH1 – MAY 2011
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Figure 27 shows an application diagram for a configuration where VLDOIN and VDDQ are separated.
TPS51206
VDDQ Sense
VTT Power
1
VDDQSNS
2
VLDOIN
VTT
3
VTTSNS
5
VTT
C1
10 mF
C3
10 mF
S3_SLP
7
S3
S5_SLP
9
S5
5 V or 3.3 V
Supply
PGND
4
VTTREF
6
C4
0.22 mF
10 VDD
C2
0.1 mF
VTTREF
GND
8
PowerPad
UDG-11027
GND
Figure 27. VLDOIN Separated from VDDQ Configuration
Table 3. VLDOIN Separated from VDDQ Configuration Components
REFERNCE
DESIGNATOR
16
SPECIFICATION
MANUFACTURER
PART
NUMBER
C1, C3
10 µF, 6.3V, X5R, 1608 (0603)
Taiyo Yuden
JMK107BJ106MA
C2
0.1 µF, 6.3V, X5R, 1005 (0402)
Taiyo Yuden
JWK105BJ104MP
C3
10 µF, 6.3V, X5R, 1608 (0603)
Taiyo Yuden
JMK107BJ106MA
C4
0.22 µF, 6.3V, X5R, 1005 (0402)
Taiyo Yuden
JMK105BJ224KV
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PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS51206DSQR
ACTIVE
SON
DSQ
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS51206DSQT
ACTIVE
SON
DSQ
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-May-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS51206DSQR
SON
DSQ
10
3000
330.0
12.4
2.2
2.2
1.1
8.0
12.0
Q2
TPS51206DSQT
SON
DSQ
10
250
180.0
12.4
2.2
2.2
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-May-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS51206DSQR
SON
DSQ
10
3000
346.0
346.0
29.0
TPS51206DSQT
SON
DSQ
10
250
190.5
212.7
31.8
Pack Materials-Page 2
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