LM26420 Dual 2.0A, High Frequency Synchronous Step-Down DCDC Regulator General Description Features The LM26420 regulator is a monolithic, high frequency, dual PWM step-down DC/DC converter in a 16 Pin LLP and a 20 Pin eTSSOP package. It provides all the active functions to provide local DC/DC conversion with fast transient response and accurate regulation in the smallest possible PCB area. With a minimum of external components, the LM26420 is easy to use. The ability to drive two 2.0A loads with an internal 75 mΩ PMOS top switch and an internal 50 mΩ NMOS bottom switch using state-of-the-art 0.5 µm BiCMOS technology results in the best power density available. The world-class control circuitry allows on-times as low as 30ns, thus supporting exceptionally high frequency conversion over the entire 3V to 5.5V input operating range down to the minimum output voltage of 0.8V. Switching frequency is internally set to 550 kHz or 2.2 MHz, allowing the use of extremely small surface mount inductors and chip capacitors. Even though the operating frequency is high, efficiencies up to 93% are easy to achieve. External shutdown is included, featuring an ultralow stand-by current. The LM26420 utilizes current-mode control and internal compensation to provide high-performance regulation over a wide range of operating conditions. Additional features include internal soft-start circuitry to reduce inrush current, pulse-by-pulse current limit, thermal shutdown, power good indicators, precision enables, and output over-voltage protection. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Input voltage range of 3.0V to 5.5V Output voltage range of 0.8V to 4.5V 2.0A output current per output High Switching Frequencies 2.2MHz (LM26420X) 0.55MHz (LM26420Y) 75mΩ PMOS switch 50mΩ NMOS switch 0.8V, 1.5% Internal Voltage Reference Internal soft-start Independent power good for each output Independent precision enable for each output Current mode, PWM operation Thermal Shutdown Over voltage protection Start-up into Pre-biased Output Loads Outputs are 180° out of phase Applications ■ ■ ■ ■ ■ ■ Local 5V to Vcore Step-Down Converters Core Power in HDDs Set-Top Boxes USB Powered Devices DSL Modems Powering Core and I/O voltages for FPGAs, CPLDs, and ASICs Typical Application Circuit 30069664 30069684 © 2010 National Semiconductor Corporation 300696 www.national.com LM26420 Dual 2.0A, High Frequency Step-Down DC-DC Regulator August 31, 2010 LM26420 Connection Diagrams 30069601 16-Pin LLP (TOP VIEW) 30069602 20-Pin eTSSOP (TOP VIEW) Ordering Information Order Number Frequency Option LM26420XMH LM26420XMHX LM26420XSQ LM26420YMH LM26420YSQ NSC Package Drawing Top Mark eTSSOP-20 MXA20A LM26420XMH LLP-16 SQB16A L26420X eTSSOP-20 MXA20A LM26420YMH LLP-16 SQB16A L26420Y 2.2MHz LM26420XSQX LM26420YMHX Package Type 0.55MHz LM26420YSQX NOPB versions available as well www.national.com 2 Supplied As 75 units Rail 2500 units Tape and Reel 1000 units Tape and Reel 4500 units Tape and Reel 75 units Rail 2500 units Tape and Reel 1000 units Tape and Reel 4500 units Tape and Reel LM26420 Pin Descriptions 20-Pin eTSSOP Pin Name Function 3, 4 VIND1 Power Input supply for Buck 1. 17, 18 VIND2 Power Input supply for Buck 2. 1 VINC Input supply for control circuitry. 6,7 PGND1 Power ground pin for Buck 1. 14, 15 PGND2 Power ground pin for Buck 2. 20 AGND Signal ground pin. Place the bottom resistor of the feedback network as close as possible to pin. 9 PG1 Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply (open drain output). 12 PG2 Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply (open drain output). 8 FB1 Feedback pin for Buck 1. Connect to external resistor divider to set output voltage. 13 FB2 Feedback pin for Buck 2. Connect to external resistor divider to set output voltage. 5 SW1 Output switch for Buck 1. Connect to the inductor. 16 SW2 Output switch for Buck 2. Connect to the inductor. 2 EN1 Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float or be greater than VIN + 0.3V. 19 EN2 Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float or be greater than VIN + 0.3V. 10, 11, DAP Die Attach Pad Connect to system ground for low thermal impedance, but it cannot be used as a primary GND connection. Pin Descriptions 16-Pin LLP Pin Name Function 1,2 VIND1 Power Input supply for Buck 1. 11, 12 VIND2 Power Input supply for Buck 2. 15 VINC Input supply for control circuitry. 4 PGND1 Power ground pin for Buck 1. 9 PGND2 Power ground pin for Buck 2. 14 AGND Signal ground pin. Place the bottom resistor of the feedback network as close as possible to pin. 6 PG1 Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply (open drain output). 7 PG2 Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply (open drain output). 5 FB1 Feedback pin for Buck 1. Connect to external resistor divider to set output voltage. 8 FB2 Feedback pin for Buck 2. Connect to external resistor divider to set output voltage. 3 SW1 Output switch for Buck 1. Connect to the inductor. 10 SW2 Output switch for Buck 2. Connect to the inductor. 16 EN1 Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float or be greater than VIN + 0.3V. 13 EN2 Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float or be greater than VIN + 0.3V. DAP Die Attach Pad Connect to system ground for low thermal impedance and as a primary electrical GND connection. 3 www.national.com LM26420 Junction Temperature (Note 2) Storage Temperature Soldering Information Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN FB Voltage EN Voltage SW Voltage ESD Susceptibility Human Body Model (Note 3) 150°C −65°C to +150°C Infrared or Convection Reflow (15 sec) -0.5V to 7V -0.5V to 3V -0.5V to 7V -0.5V to 7V 220°C Operating Ratings VIN Junction Temperature 3V to 5.5V −40°C to +125°C 1.5kV Electrical Characteristics Per Buck VIN = 5V unless otherwise indicated under the Conditions column. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol VFB ΔVFB/VIN IB UVLO Parameter Conditions Feedback Voltage Feedback Voltage Line Regulation Min Typ Max Units 0.788 0.800 0.812 V VIN = 3V to 5.5V 0.05 Feedback Input Bias Current Under-voltage Lockout VIN Rising Switching Frequency FFB Frequency Fold-back DMAX Maximum Duty Cycle RDSON_TOP TOP Switch On Resistance RDSON_BOT BOTTOM Switch On Resistance 2.2 2.65 LM26420-Y 0.4 0.55 0.7 LM26420-X 300 LM26420-Y 150 LM26420-X 86 91.5 LM26420-Y 90 98 135 135 LLP-16 Package 55 100 eTSSOP-20 Package 45 80 3.3 0.4 0.75 160 180 200 Enable Threshold Voltage 0.97 1.04 1.12 Enable Threshold Hysteresis Enable Pin Current Sink/Source Upper Power Good Threshold FB Pin Voltage Rising 848 Lower Power Good Threshold µA nA 925 1,008 710 40 mV mV 3.3 5.0 VINC Quiescent Current (switching) with both outputs on LM26420X/Y VFB = 0.7 4.7 6.2 VINC Quiescent Current (shutdown) All Options VEN = 0V 0.05 VIND Quiescent Current (non-switching) LM26420X/Y VFB = 0.9 0.9 1.5 LM26420X VFB = 0.7 11.0 15.0 LM26420Y VFB = 0.7 3.7 7.5 All Options VEN = 0V 0.1 4 mV mV 791 LM26420X/Y VFB = 0.9 VIND Quiescent Current (switching) V 5.0 VINC Quiescent Current (non-switching) with both outputs on VIND Quiescent Current (shutdown) www.national.com 656 ° -0.7 40 FB Pin Voltage Rising mΩ A 0.15 Switch Leakage mΩ A Phase Shift Between SW1 and SW2 Lower Power Good Hysteresis IQVIND % 70 2.4 MHz kHz 75 Upper Power Good Hysteresis IQVINC mV eTSSOP-20 Package VIN = 3.3V VPG-TH-L V LLP-16 Package BOTTOM Switch Reverse Current Limit VPG-TH-U V 2.3 330 ICL_BOT IEN 2.90 1.85 VIN = 3.3V ISW_TOP 2.628 LM26420-X TOP Switch Current Limit VEN_TH nA 2.0 ICL_TOP ΔΦ 100 VIN Falling UVLO Hysteresis FSW %/V 0.40 mA µA mA µA θJA Parameter Junction to Ambient 0 LFPM Air Flow (Note 4) θJC Junction to Case (Note 4) TSD Thermal Shutdown Temperature Conditions Min LLP-16 Typ Units 40 eTSSOP-20 35 LLP-16 6.8 eTSSOP-20 Max °C/W 3.9 165 °C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device. Note 3: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-A114. Note 4: Applies to a 4-layer standard JEDEC thermal test board or 4LJEDEC is 4"x3" in size. The board has 2 imbedded copper layers which cover roughly the same size as the board. The copper thickness for the four layers, starting from the top one, is 2 oz./1oz./1oz./2 oz. For LLP, thermal vias are placed between the die attach pad in the 1st. copper layer and 2nd. copper layer. 5 www.national.com LM26420 Symbol LM26420 Typical Performance Characteristics All curves taken at VIN = 5.0V with configuration in typical application circuit shown in Application Information section of this datasheet. TJ = 25°C, unless otherwise specified. η vs Load "X" VIN = 5V, VOUT = 3.3V η vs Load "Y" VIN = 5V, VOUT = 3.3V 30069682 30069683 η vs Load - "X" VIN = 5V & 3V, VOUT = 2.5V η vs Load "Y" VIN = 5V & 3V, VOUT = 2.5V 30069685 30069684 η vs Load "X" VIN = 5V & 3V, VOUT = 1.8V η vs Load "Y" VIN = 5V & 3V, VOUT = 1.8V 30069690 www.national.com 30069687 6 η vs Load "Y" VIN = 5V & 3V, VOUT = 1.2V 30069688 30069689 η vs Load "X" VIN = 5V & 3V, VOUT = 0.8V η vs Load "Y" VIN = 5V & 3V, VOUT = 0.8V 30069641 30069642 Load Regulation VIN = 5V, VOUT = 1.8V (All Options) Load Regulation VIN = 3V, VOUT = 1.8V (All Options) 30069643 30069645 7 www.national.com LM26420 η vs Load "X" VIN= 5V & 3V, VOUT = 1.2V LM26420 Line Regulation - "X" VOUT = 1.8V, IOUT = 1,000mA Line Regulation - "Y" VOUT = 1.8V, IOUT = 1,000mA 30069627 30069646 Oscillator Frequency vs Temperature - "X" Oscillator Frequency vs Temperature - "Y" 30069648 30069647 RDSON TOP vs Temperature (LLP-16 Package) RDSON BOTTOM vs Temperature (LLP-16 Package) 30069649 www.national.com 30069650 8 RDSON BOTTOM vs Temperature (eTSSOP-20 Package) 30069691 30069692 IQ (Quiescent Current Switching) - "X" IQ (Quiescent Current Switching) - "Y" 30069654 30069655 Load Transient Response - X Version (VOUT = 1.2V, 25-100% Load Transient) Load Transient Response - Y Version (VOUT = 1.2V, 25-100% Load Transient) 30069639 30069656 9 www.national.com LM26420 RDSON TOP vs Temperature (eTSSOP-20 Package) LM26420 Start-Up (Soft-Start) (VOUT = 1.8V @ 1A, VIN = 5V) Enable - Disable (VOUT = 1.8V @ 1A, VIN = 5V) 30069657 30069658 VFB vs Temperature Current Limit vs Temperature (VIN = 5V and 3.3V) 30069659 30069653 Reverse Current Limit vs Temperature Short Circuit Waveforms 30069698 30069680 www.national.com 10 LM26420 Simplified Block Diagram Per Buck 30069604 FIGURE 1. 11 www.national.com LM26420 Applications Information current and eliminate overshoot on VOUT. During soft-start, the error amplifier’s reference voltage ramps from 0V to its nominal value of 0.8V in approximately 600 µs. If the converter is turned on into a pre-biased condition then the feedback will begin ramping from the pre-bias voltage but at the same rate as if it had started from 0V. The two outputs startup ratiometrically if enabled at the same time, see figure below. THEORY OF OPERATION The LM26420 is a constant frequency dual PWM buck synchronous regulator IC that delivers two 2.0A load currents. The regulator has a preset switching frequency of 2.2MHz or 550kHz. This high frequency allows the LM26420 to operate with small surface mount capacitors and inductors, resulting in a DC/DC converter that requires a minimum amount of board space. The LM26420 is internally compensated, so it is simple to use and requires few external components. The LM26420 uses current-mode control to regulate the output voltage. The following operating description of the LM26420 will refer to the Simplified Block Diagram (Figure 1), which depicts the functional blocks for one of the two channels, and to the waveforms in Figure 2. The LM26420 supplies a regulated output voltage by switching the internal PMOS and NMOS switches at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by the internal clock. When this pulse goes low, the output control logic turns on the internal PMOS control switch (TOP Switch). During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (IL) increases with a linear slope. IL is measured by the current sense amplifier, which generates an output proportional to the switch current. The sense signal is summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage and VREF. When the PWM comparator output goes high, the TOP Switch turns off and the NMOS switch (BOTTOM Switch) turns on after a short delay, which is controlled by the Dead-Time-Control Logic, until the next switching cycle begins. During the top switch offtime, inductor current discharges through the BOTTOM Switch, which forces the SW pin to swing to ground. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage. OUTPUT OVER-VOLTAGE PROTECTION The over-voltage comparator compares the FB pin voltage to a voltage that is approximately 15% higher than the internal reference VREF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control switch is turned off, which allows the output voltage to decrease toward regulation. UNDER-VOLTAGE LOCKOUT Under-voltage lockout (UVLO) prevents the LM26420 from operating until the input voltage exceeds 2.628V (typ). The UVLO threshold has approximately 330 mV of hysteresis, so the part will operate until VIN drops below 2.3V (typ). Hysteresis prevents the part from turning off during power up if VIN is non-monotonic. CURRENT LIMIT The LM26420 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a current limit comparator detects if the output switch current exceeds 3.3A (typ), and turns off the switch until the next switching cycle begins. THERMAL SHUTDOWN Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the output switch does not turn on until the junction temperature drops to approximately 150°C. POWER GOOD The LM26420 features and open drain power good (PG) pin to sequence external supplies or loads and to provide fault detection. This pin requires an external resistor (RPG) to pull PG high when the output is within the PG tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ. 30069666 FIGURE 2. Typical Waveforms SOFT-START This function forces VOUT to increase at a controlled rate during start up in a controlled fashion, which helps reduce inrush www.national.com 12 13 www.national.com LM26420 with a resistor divider network. It can also be set to turn on at a specific input voltage when used in conjunction with a resistor divider network connected to the input voltage. The device is enabled when the EN pin exceeds 1.04V and has a 150mV hysteresis. PRECISION ENABLE The LM26420 features independent precision enables that allow the converter to be controlled by an external signal. This feature allows the device to be sequenced either by a external control signal or the output of another converter in conjunction LM26420 Design Guide INDUCTOR SELECTION The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (VOUT) to input voltage (VIN): Where When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating correctly. The peak current of the inductor is used to specify the maximum output current of the inductor and saturation is not a concern due to the exceptionally small delay of the internal current limit signal. For example, if the designed maximum output current is 2.0A and the peak current is 2.3A, then the inductor should be specified with a saturation current limit of > 2.3A. There is no need to specify the saturation or peak current of the inductor at the 3.25A typical switch current limit. The difference in inductor size is a factor of 5. Ferrite based inductors are preferred to minimize core losses when opperating with the frequencies used by the LM26420. This presents little restriction since the variety of ferrite-based inductors is huge. Lastly, inductors with lower series resistance (RDCR) will provide better operating efficiency. For recommended inductors see Example Circuits. The voltage drop across the internal NMOS (SW_BOT) and PMOS (SW_TOP) must be included to calculate a more accurate duty cycle. Calculate D by using the following formulas: VSW_TOP and VSW_BOT can be approximated by: VSW_TOP = IOUT x RDSON_TOP VSW_BOT = IOUT x RDSON_BOT The inductor value determines the output ripple current. Lower inductor values decrease the size of the inductor, but increase the output ripple current. An increase in the inductor value will decrease the output ripple current. One must ensure that the minimum current limit (2.4A) is not exceeded, so the peak current in the inductor must be calculated. The peak current (ILPK) in the inductor is calculated by: INPUT CAPACITOR SELECTION The input capacitors provide the AC current needed by the nearby power switch so that current provided by the upstream power supply does not carry a lot of AC content, generating less EMI. To the buck regulator in question, the input capacitor also prevents the drain voltage of the FET switch from dipping when the FET is turned on, therefore providing a healthy line rail for the LM26420 to work with. Since typically most of the AC current is provided by the local input capacitors, the power loss in those capacitors can be a concern. In the case of the LM26420 regulator, since the two channels operate 180° out of phase, the AC stress in the input capacitors is less than if they operated in phase. The measure for the AC stress is called input ripple RMS current. It is strongly recommended that at least one 10µF ceramic capacitor be placed next to each of the VIND pins. Bulk capacitors such as electrolytic capacitors or OSCON capacitors can be added to help stabilize the local line voltage, especially during large load transient events. As for the ceramic capacitors, use X7R or X5R types. They maintain most of their capacitance over a wide temperature range. Try to avoid sizes smaller than 0805. Otherwise significant drop in capacitance may be caused by the DC bias voltage. See OUTPUT CAPACITOR SELECTION section for more information. The DC voltage rating of the ceramic capacitor should be higher than the highest input voltage. Capacitor temperature is a major concern in board designs. While using a 10µF or higher MLCC as the input capacitor is a good starting point, it is a good idea to check the temperature in the real thermal environment to make sure the capacitors are not over heated. Capacitor vendors may provide curves of ripple RMS current vs. temperature rise, based on a designated thermal impedance. In reality, the thermal impedance may be very different. So it is always a good idea to check the capacitor temperature on the board. ILPK = IOUT + ΔiL 30069605 FIGURE 3. Inductor Current In general, ΔiL = 0.1 x (IOUT) → 0.2 x (IOUT) If ΔiL = 20% of 2A, the peak current in the inductor will be 2.4A. The minimum guaranteed current limit over all operating conditions is 2.4A. One can either reduce ΔiL, or make the engineering judgment that zero margin will be safe enough. The typical current limit is 3.3A. The LM26420 operates at frequencies allowing the use of ceramic output capacitors without compromising transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple. See the output capacitor section for more details on calculating output voltage ripple. Now that the ripple current is determined, the inductance is calculated by: www.national.com 14 RDC is the winding resistance of the inductor. RDS is the ON resistance of the MOSFET switch. Example: VIN = 5V, VOUT1 = 3.3V, IOUT1 = 2A, VOUT2 = 1.2V, IOUT2 = 1.5A, RDS = 170mΩ, RDC = 30mΩ. (IOUT1 is the same as I1 in the input ripple RMS current equation, IOUT2 is the same as I2). First, find out the duty cycles. Plug the numbers into the duty cycle equation and we get D1 = 0.75, and D2 = 0.33. Next, follow the decision tree in to find out the values of d1, d2 and d3. In this case, d1 = 0.5, d2 = D2 + 0.5 - D1 = 0.08, and d3 = D1 - 0.5 = 0.25. Iav = IOUT1·D1 + IOUT2·D2 = 1.995A. Plug all the numbers into the input ripple RMS current equation and the result is Iirrms = 0.77A. I1 is Channel 1's maximum output current. I2 is Channel 2's maximum output current. d1 is the non-overlapping portion of Channel 1's duty cycle D1. d2 is the non-overlapping portion of Channel 2's duty cycle D2. d3 is the overlapping portion of the two duty cycles. Iav is the average input current. Iav= I1·D1 + I2·D2. To quickly determine the values of d1, d2 and d3, refer to the decision tree in . To determine the duty cycle of each channel, use D = VOUT/VIN for a quick result or use the following equation for a more accurate result. 30069681 FIGURE 4. Determining d1, d2 and d3 switching edge noise will couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output capacitor is one of the two external components that control the stability of the regulator control loop, most applications will require a minimum of 22 µF of output capacitance. Capacitance often, but not always, can be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended multilayer ceramic capacitors are X7R or X5R types. OUTPUT CAPACITOR The output capacitor is selected based upon the desired output ripple and transient response. The initial current of a load transient is provided mainly by the output capacitor. The output ripple of the converter is: When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the availability and quality of MLCCs and the expected output voltage of designs using the LM26420, there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass high frequency noise. A certain amount of PROGRAMMING OUTPUT VOLTAGE The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and R1 is connected between VOUT and the FB pin. A good value for R2 is 10kΩ. When designing a unity gain converter (VOUT = 0.8V), R1 should be between 0Ω and 100Ω, and R2 should be on the order of 5kΩ to 50kΩ, 10kΩ is the suggested value. 15 www.national.com LM26420 Since the duty cycles of the two channels may overlap, calculation of the input ripple RMS current is a little tedious. Use the following equation. LM26420 time constant should be at least 2 µS. CF should be placed as close as possible to IC with a direct connection from VINC and AGND. USING PRECISION ENABLE AND POWER GOOD The LM26420's precision enable and power good pins address many of the sequencing requirements required today's challenging applications. Each output can be controlled independently and have independent power goods. This allows for a multitude of ways to control each output. Typically, the enables to each output are tied together to the input voltage and the outputs will ratiometrically ramp up when the input voltage reaches above UVLO rising threshold. There may be instances where it is desired that the second output (VOUT2) does not turn on until the first output (VOUT1) has reached 90% of the desired set-point. This achieved easily with an external resistor divider attached from VOUT1 to EN2, see figure . VREF = 0.80V 30069699 FIGURE 5. Programming VOUT To determine the maximum allowed resistor tolerance , use the following equation: 30069640 where TOL is the set point accuracy of the regulator, Φ is the tolerance of VFB. Example: VOUT = 2.5V, with a set point accuracy of +/- 3.5%. FIGURE 7. VOUT1 controlling VOUT2 with resistor divider. If it is not desired to have a resistor divider to control VOUT2 with VOUT1, then the PG1 can be connected to the EN2 pin to control VOUT2, see figure below. RPG1 is a pull up resistor on the range of 10kΩ to 100kΩ, 50kΩ is the suggested value. greater. This will turn on VOUT2 when VOUT1 is approximately 90% of the programmed output. NOTE, this will also turn off VOUT2 when VOUT1 is outside the +/-10% of the programmed output. Choose 1% resistors. If R2 = 10kΩ, then R1 is 21.25kΩ. VINC FILTERING COMPONENTS Additional filtering is required between VINC and AGND in order to prevent high frequency noise on VIN from disturbing the sensitive circuitry connected to VINC. A small RC filter can be used on the VINC pin as shown below. 30069697 FIGURE 8. PG1 controlling VOUT2. Another example might be that the output is not to be turned on until the input voltage reaches 90% of desired voltage setpoint. This verifies that the input supply is stable before turning on the output. Select REN1 and REN2 such that the the voltage at the EN pin is greater than 1.12V when reaching the 90% desired set-point. 30069638 FIGURE 6. RC filter on VINC In general, RF is typically between 1Ω and 10Ω so that the steady state voltage drop across the resistor due to the VINC bias current does not affect the UVLO level. CF can range from 0.22 µF to 1.0 µF in X7R or X5R dielectric, where the RC www.national.com 16 30069696 FIGURE 9. VIN controlling VOUT The LM26420's power good feature is design with hysterysis in order to insure no false power good flags are asserted during large transient. Once power good is asserted high, it will not be pulled low until the output voltage exceeds +/-14% of the setpoint for a during of ~7.5µS (typ.), see figure below. PCB LAYOUT CONSIDERATIONS When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most important consideration is the close coupling of the GND connections of the input capacitor and the PGND pin. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. Next in importance is the location of the GND connection of the output capacitor, which should be near the GND connections of VIND and PGND. There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R1 placed as close as possible to the GND of the IC. The VOUT trace to R2 should be routed away from the inductor and any other traces that are switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-1229 for further considerations and the LM26420 demo board as an example of a four-layer layout. 30069660 FIGURE 10. Power Good Hysterysis Operation OVER-CURRENT PROTECTION When the switch current reaches the current limit value, it immediately is turned off. This effectively reduces the duty cycle and therefore the output voltage dips and continues to droop until the output load matches the peak current limit inductor current. As the FB voltage drops below 480mV the operating frequency begins to decrease until it hits full on frequency 17 www.national.com LM26420 fold-back which is set to approximately 150kHz for the Y version and 300kHz for the X version. Frequency fold back helps reduce the thermal stress in the IC by reducing the switching losses and to prevent runaway of the inductor current when the output is shorted to ground. It is important to note that when recovering from a over-current condition the converter does not go through the soft-start process. There may be an over shoot due to the sudden removal of the over-current fault. The reference voltage at the non-inverting input of the error amplifier always sits at 0.8V during the over-current condition, therefore when the fault is removed the converter bring the FB voltage back to 0.8V as quickly as possible. The over-shoot depend on whether there is a load on the output after the removal of the over-current fault, the size of the inductor, and the amount of capacitance on the output. The small the inductor and the larger the capacitance on the output the small the overshoot. Note, overcurrent protection for each output is independent. LM26420 PCOND_TOP = (IOUT2 x RDSON_TOP x D) Calculating Efficiency, and Junction Temperature PCOND_BOT = (IOUT2 x RDSON_BOT x (1-D)) PCOND = PCOND_TOP + PCOND_BOT The complete LM26420 DC/DC converter efficiency can be calculated in the following manner. Switching losses are also associated with the internal FETs. They occur during the switch on and off transition periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node. Switching Power Loss is calculated as follows: Or PSWR = 1/2(VIN x IOUT x FSW x TRISE) PSWF = 1/2(VIN x IOUT x FSW x TFALL) PSW = PSWR + PSWF Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are not discussed. Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction. Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D): Another loss is the power required for operation of the internal circuitry: PQ = IQ x VIN IQ is the quiescent operating current, and is typically around 8.4mA (IQVINC = 4.7mA + IQVIND=3.7mA) for the 550 kHz frequency option. Due to Dead-Time-Control Logic in the converter, there is a small delay (~4nS) between the turn ON and OFF of the TOP and BOTTOM FET. During this time, the body diode of the BOTTOM FET is conducting with a voltage drop of VBDIODE (~.65V). This allows the inductor current to circulate to the output, until the BOTTOM FET is turned ON an the inductor current passes through the FET. There is a small amount of power loss due to this body diode conducting and it can be calculated as follows: VSW_TOP is the voltage drop across the internal PFET when it is on, and is equal to: PBDIODE = 2x(VBDIODE x IOUT x FSW x TBDIODE) VSW_TOP = IOUT x RDSON_TOP Typical Application power losses are: VSW_BOT is the voltage drop across the internal NFET when it is on, and is equal to: PLOSS = ΣPCOND + PSW + PBDIODE + PIND + PQ PINTERNAL = ΣPCOND + PSW+ PBDIODE + PQ VSW_BOT = IOUT x RDSON_BOT Power Loss Tabulation If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes: Another significant external power loss is the conduction loss in the output inductor. The equation can be simplified to: PIND = IOUT2 x RDCR The LM26420 conduction loss is mainly associated with the two internal FETs: VIN 5.0V VOUT 1.2V IOUT 2.0A POUT 2.4W PBDIODE 5.7mW FSW 550kHz VBDIODE 0.65V IQ 8.4mA PQ 42mW TRISE 1.5nS PSWR 4.1mW TFALL 1.5nS PSWF 4.1mW RDSON_TOP 75mΩ PCOND_TOP 81mW RDSON_BOT 55mΩ PCOND_BOT 167mW INDDCR 20mΩ PIND 80mW D 0.262 PLOSS 384mW η 86.2% PINTERNAL 304mW These calculations assume a junction temperature of 25°C. The RDSON values will be larger due to internal heating and therefore the internal power loss (PINTERNAL) must be first calculated to estimate the rise in junction temperature. If the inductor ripple current is fairly small, the conduction losses can be simplified to: www.national.com 18 LM26420 Thermal Definitions TJ = Chip junction temperature TA = Ambient temperature RθJC = Thermal resistance from chip junction to device case RθJA = Thermal resistance from chip junction to ambient air Heat in the LM26420 due to internal power dissipation is removed through conduction and/or convection. Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor). Heat Transfer goes as: Silicon → package → lead frame → PCB Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural convection occurs when air currents rise from the hot device to cooler air. Thermal impedance is defined as: Therefore: Tj = (RΦJC x PINTERNAL) + TC From the previous example: Tj = 20°C/W x 0.304W + TC Method 2: Thermal Shutdown Temperature Determination The second method, although more complicated, can give a very accurate silicon junction temperature. The first step is to determine RθJA of the application. The LM26420 has over-temperature protection circuitry. When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a hysteresis of about 15°C. Once the silicon temperature has decreased to approximately 150°C, the device will start to switch again. Knowing this, the RθJA for any application can be characterized during the early stages of the design one may calculate the RθJA by placing the PCB circuit into a thermal chamber. Raise the ambient temperature in the given working application until the circuit enters thermal shutdown. If the SW-pin is monitored, it will be obvious when the internal FETs stop switching, indicating a junction temperature of 165°C. Knowing the internal power dissipation from the above methods, the junction temperature, and the ambient temperature RθJA can be determined. Thermal impedance from the silicon junction to the ambient air is defined as: The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can greatly effect RθJA. The type and number of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to the ground plane. Five to eight thermal vias should be placed under the exposed pad to the ground plane if the LLP package is used. Up to 12 thermal vias should be used in the eTSSOP-20 package for optimum heat transfer from the device to the ground plane. Thermal impedance also depends on the thermal properties of the application's operating conditions (VIN, VOUT, IOUT etc), and the surrounding circuitry. Method 1: Silicon Junction Temperature Determination To accurately measure the silicon temperature for a given application, two methods can be used. The first method requires the user to know the thermal impedance of the silicon junction to top case temperature. Some clarification needs to be made before we go any further. RθJC is the thermal impedance from all six sides of an IC package to silicon junction. RΦJC is the thermal impedance from top case to the silicon junction. In this data sheet we will use RΦJC so that it allows the user to measure top case temperature with a small thermocouple attached to the top case. RΦJC is approximately 20°C/Watt for the 16-pin LLP package with the exposed pad. Knowing the internal dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically measured on the bench we have: Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be found. An example of calculating RθJA for an application using the National Semiconductor LM26420 LLP demonstration board is shown below. The four layer PCB is constructed using FR4 with 1 oz copper traces. The copper ground plane is on the bottom layer. The ground plane is accessed by eight vias. The board measures 3.0cm x 3.0cm. It was placed in an oven with no forced airflow. The ambient temperature was raised to 152°C, and at that temperature, the device went into thermal shutdown. From the previous example: PINTERNAL = 304mW If the junction temperature was to be kept below 125°C, then the ambient temperature could not go above 112°C. Tj - (RθJA x PINTERNAL) = TA 125°C - (42.8°C/W x 304mW) = 112.0°C 19 www.national.com LM26420 LLP Package 30069668 FIGURE 11. Internal LLP Connection For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 6). By increasing the size of ground plane, and adding thermal vias, the RθJA for the application can be reduced. 30069606 FIGURE 12. 20-Lead eTSSOP PCB Dog Bone Layout www.national.com 20 LM26420 LM26420X Design Example 1 30069607 FIGURE 13. LM26420X (2.2MHz): VIN = 5V, VOUT1 = 1.2V @ 2.0A and VOUT2 = 2.5V @ 2.0A Bill of Materials Part ID Part Value Manufacturer U1 2A Buck Regulator NSC Part Number LM26420X C3, C4 15µF, 6.3V, 1206, X5R TDK C3216X5R0J156M C1 33µF, 6.3V, 1206, X5R TDK C3216X5R0J336M C2 22µF, 6.3V, 1206, X5R TDK C3216X5R0J226M C5 0.47µF, 10V, 0805, X7R Vishay VJ0805Y474KXQCW1BC L1 1.0µH, 7.9A TDK RLF7030T-1R0M6R4 L2 1.5µH, 6.5A TDK RLF7030T-1R5M6R1 R3, R4 10.0kΩ, 0603, 1% Vishay CRCW060310K0F R1 4.99kΩ, 0603, 1% Vishay CRCW06034K99F R5, R6 49.9kΩ, 0603, 1% Vishay CRCW060649K9F R2 21.5kΩ, 0603, 1% Vishay CRCW060321K5F R7 4.99Ω, 0603, 1% Vishay CRCW06034R99F 21 www.national.com LM26420 LM26420X Design Example 2 30069628 FIGURE 14. LM26420X (2.2MHz): VIN = 5V, VOUT1 = 1.8V @ 2.0A and VOUT2 = 0.8V @ 2.0A Bill of Materials Part ID Part Value Manufacturer U1 2A Buck Regulator NSC Part Number LM26420X C3, C4 15µF, 6.3V, 1206, X5R TDK C3216X5R0J156M C3216X5R0J336M C1 33µF, 6.3V, 1206, X5R TDK C2, C6 22µF, 6.3V, 1206, X5R TDK C3216X5R0J226M C5 0.47µF, 10V, 0805, X7R Vishay VJ0805Y474KXQCW1BC L1 1.0µH, 7.9A TDK RLF7030T-1R0M6R4 L2 0.7µH, 3.7A Coilcraft LPS4414-701ML R3, R4 10.0kΩ, 0603, 1% Vishay CRCW060310K0F R5, R6 49.9kΩ, 0603, 1% Vishay CRCW060649K9F R1 12.7kΩ, 0603, 1% Vishay CRCW060312K7F R7, R2 4.99Ω, 0603, 1% Vishay CRCW06034R99F www.national.com 22 LM26420 LM26420X Design Example 3 30069603 FIGURE 15. LM26420X (2.2MHz): VIN = 5V, VOUT1 = 3.3V @ 2.0A and VOUT2 = 1.8V @ 2.0A Bill of Materials Part ID Part Value Manufacturer U1 2A Buck Regulator NSC Part Number LM26420X C3, C4 15µF, 6.3V, 1206, X5R TDK C3216X5R0J156M C1 22µF, 6.3V, 1206, X5R TDK C3216X5R0J226M C2 33µF, 6.3V, 1206, X5R TDK C3216X5R0J336M C5 0.47µF, 10V, 0805, X7R Vishay VJ0805Y474KXQCW1BC L1, L2 1.0µH, 7.9A TDK RLF7030T-1R0M6R4 R3, R4 10.0kΩ, 0603, 1% Vishay CRCW060310K0F R2 12.7kΩ, 0603, 1% Vishay CRCW060312K7F R5, R6 49.9kΩ, 0603, 1% Vishay CRCW060649K9F R1 31.6kΩ, 0603, 1% Vishay CRCW060331K6F R7 4.99Ω, 0603, 1% Vishay CRCW06034R99F 23 www.national.com LM26420 LM26420Y Design Example 4 30069607 FIGURE 16. LM26420Y (550kHz): VIN = 5V, VOUT1 = 1.2V @ 2.0A and VOUT2 = 2.5V @ 2.0A Bill of Materials Part ID Part Value Manufacturer U1 2A Buck Regulator NSC LM26420Y C3, C4 22µF, 6.3V, 1206, X5R TDK C3216X5R0J226M C1, C6, C7 33µF, 6.3V, 1206, X5R TDK C3216X5R0J336M C2 47µF, 6.3V, 1206, X5R TDK C3216X5R0J476M C5 0.47µF, 10V, 0805, X7R Vishay VJ0805Y474KXQCW1BC L1 3.3µH, 3.28A Coilcraft MSS7341-332NL L2 5.0µH, 2.82A Coilcraft MSS7341-502NL R3, R4 10.0kΩ, 0603, 1% Vishay CRCW060310K0F R1 4.99kΩ, 0603, 1% Vishay CRCW06034K99F R5, R6 49.9kΩ, 0603, 1% Vishay CRCW060649K9F R2 21.5kΩ, 0603, 1% Vishay CRCW060321K5F R7 4.99Ω, 0603, 1% Vishay CRCW06034R99F www.national.com 24 Part Number LM26420 LM26420Y Design Example 5 30069628 FIGURE 17. LM26420Y (550kHz): VIN = 5V, VOUT1 = 1.8V @ 2.0A and VOUT2 = 0.8V @ 2.0A Bill of Materials Part ID Part Value Manufacturer U1 2A Buck Regulator NSC Part Number LM26420Y C3, C4 22µF, 6.3V, 1206, X5R TDK C3216X5R0J226M C1, C2, C6, C7, C8 47µF, 6.3V, 1206, X5R TDK C3216X5R0J476M C5 0.47µF, 10V, 0805, X7R Vishay VJ0805Y474KXQCW1BC L1 5.0µH, 2.82A Coilcraft MSS7341-502NL L2 3.3µH, 3.28A Coilcraft MSS7341-332NL R3, R4 10.0kΩ, 0603, 1% Vishay CRCW060310K0F R5, R6 49.9kΩ, 0603, 1% Vishay CRCW060649K9F R1 12.7kΩ, 0603, 1% Vishay CRCW060312K7F R7, R2 4.99Ω, 0603, 1% Vishay CRCW06034R99F 25 www.national.com LM26420 LM26420Y Design Example 6 30069603 FIGURE 18. LM26420Y (550kHz): VIN = 5V, VOUT1 = 3.3V @ 2.0A and VOUT2 = 1.8V @ 2.0A Bill of Materials Part ID Part Value Manufacturer U1 2A Buck Regulator NSC Part Number LM26420Y C3, C4 22µF, 6.3V, 1206, X5R TDK C3216X5R0J226M C1, C2, C6 47µF, 6.3V, 1206, X5R TDK C3216X5R0J476M C5 0.47µF, 10V, 0805, X7R Vishay VJ0805Y474KXQCW1BC L1, L2 5.0µH, 2.82A Coilcraft MSS7341-502NL R3, R4 10.0kΩ, 0603, 1% Vishay CRCW060310K0F R2 12.7kΩ, 0603, 1% Vishay CRCW060312K7F R5, R6 49.9kΩ, 0603, 1% Vishay CRCW060649K9F R1 31.6kΩ, 0603, 1% Vishay CRCW060331K6F R7 4.99Ω, 0603, 1% Vishay CRCW06034R99F www.national.com 26 LM26420 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead eTSSOP Package NS Package Number MXA20A 16-Lead LLP Package NS Package Number SQB16A 27 www.national.com LM26420 Dual 2.0A, High Frequency Step-Down DC-DC Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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