FPD87208AXA +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS™ Outputs General Description Features The FPD87208AXA is a timing controller that combines an LVDS single pixel input interface with National Reduced Swing Differential Signaling (RSDS™) output driver interface for XGA and Wide XGA resolutions. It resides on the TFTLCD panel and provides the data buffering and control signal generation for XGA, and Wide XGA graphic modes. The RSDS path to the column driver contributes toward lowering radiated EMI and reducing system dynamic power consumption. This single RSDS bus conveys the 6-bit color data for XGA, and three different WXGA resolutions. n Reduced Swing Differential Signaling (RSDS) digital bus reduces dynamic power, EMI and bus-width from the timing controller n LVDS single pixel input interface system n Input clock range from 25 MHz to 85 MHz n Drives RSDS column drivers at 170 Mb/s with an 85 MHz clock (Max) n BIST Function n CMOS circuitry operates from a 2.25V–2.75V; 0˚C–70˚C n 64 TQFP package with body size 10 mm x 10 mm x 1.0 mm System Diagram 20101401 FIGURE 1. Block Diagram of the LCD Module RSDS™ is a trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS201014 www.national.com FPD87208AXA +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS Outputs July 2004 FPD87208AXA Absolute Maximum Ratings (Note 1) ESD Rating: If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. HBM: MM: Supply Voltage (VDD) MM: RZAP = 0Ω, CZAP = 200 pF) (HBM: RZAP = 1.5 kΩ, CZAP = 100 pF, −0.3V to +3.0V DC TTL Input Voltage (VIN) −0.3V to (VDD + 0.3V) DC LVDS Input Voltage (VIN) −0.3V to (VDD + 0.3V) DC Output Voltage (VOUT) −0.3V to (VDD + 0.3V) Junction Temperature 2 kV 200V Operating Conditions Min Max 2.25 2.75 V 0 70 ˚C 200 mVPP +150˚C Storage Temperature Range (TSTG) Supply Voltage (VDD) Operating Temp. Range (TA) −65˚C to +150˚C Supply Noise Voltage Lead Temperature (TL) (Soldering 10 sec.) 260˚C DC Electrical Characteristics Units Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. VDD = 2.5V ± 0.25V, TA = 0˚C to 70˚C, IPI = 100 µA (Unless otherwise specified) TTL DC Electrical Characteristics Min Typ Max VDD Symbol Supply Voltage Parameter Conditions 2.25 2.5 2.75 Units VIH Minimum Input High Voltage 1.8 VIL Maximum Input Low Voltage VOH Output High Voltage IOH = −8 mA VOL Output Low Voltage IOL = 8 mA 0.4 IIN Input Current VIN = VDD 10 µA VIN = GND 10 µA IDD Average Supply Current CLK = 85 MHz, RPI = 12.3k CL(TTL) = 50 pF, RL(RSDS) = 100Ω and CL(RSDS) = 5 pF (jig & test fixture capacitance), See Figure 3 for input conditions 120 IP = 100 µA VDD = 2.75V mA V 0.7 V 0.8 x VDD 80 IP = 100 µA VDD = 2.5V FPD-Link (LVDS) Receiver Input (RxCLKP/N; RxIN[y]P/N, y = 0,1,2) Symbol Parameter Conditions Min Typ Max Units LVDS RECEIVER DC SPECIFICATIONS Note: LVDS Receiver DC parameters are measured under Static and Steady state conditions which may not be reflective of its performance in the end application. This device is compatible with TIA644 SPEC. V0 and V2.4. VTHLVDS Differential Input High Threshold Voltage VTLLVDS Differential Input Low Threshold Voltage IIN INput Current VIN INput Voltage Range |VID| Differential Input Voltage VCM Common Mode Voltage Offset +100 −100 VIN = VDD –0.4V, VDD = 2.75V VIN = 0V, VDD = 2.75V www.national.com mV VCM = 1.2V 2 mV ± 10 µA ± 10 µA 0 VDD –0.4 V 0.100 0.600 V 0 + |VID|/2 (VDD –0.4) − |VID|/2 V |VID| and VCM Definitions 20101402 FIGURE 2. LVDS VID and VCM Allowable Operating Range FPD-Link Receiver Input Pattern Used to Measure IDD 20101403 FIGURE 3. FPD-Link Receiver IDD Pattern 3 www.national.com FPD87208AXA DC Electrical Characteristics VDD = 2.5V ±0.25V, TA = 0˚C to 70˚C, IPI = 100 µA (Unless otherwise specified) (Continued) FPD87208AXA DC Electrical Characteristics VDD = 2.5V ±0.25V, TA = 0˚C to 70˚C, IPI = 100 µA (Unless otherwise specified) (Continued) RSDS Output (CLKP/N, xyP/N; x = R, G, B; y = 0, 1, 2), VDD = 2.25V to 2.75V (Unless otherwise specified) Symbol Parameter Conditions |VODRSDS| Differential Output Voltage Typ. VOSRSDS Offset Voltage Min RL = 100Ω IPI = 100 µA Typ Max Units 200 (Figure 4) mV 1.2 V 20101404 FIGURE 4. RSDS Output Waveforms: Single Ended vs Differential 20101405 FIGURE 5. Typical RSDS VOD vs RPI Response Curve www.national.com 4 Schmitt Trigger Symbol Parameter Conditions Min Typ Max Units VH Hysteresis Voltage 0.4 V VT− Hysteresis Low Threshold Voltage 1.2 V VT+ Hysteresis High Threshold Voltage 1.6 V IINHYS Input Current VT+ – VT− VIN = VDD 20 VIN = VSS −20 0 µA µA 20101406 FIGURE 6. Hysteresis Definition 5 www.national.com FPD87208AXA DC Electrical Characteristics VDD = 2.5V ±0.25V, TA = 0˚C to 70˚C, IPI = 100 µA (Unless otherwise specified) (Continued) FPD87208AXA AC Electrical Characteristics TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) LVDS Data Input Symbol Parameter FRXCLK RxCLK Frequency (LVDS) RPLLS FPD-Link Receiver Phase Lock Loop Wake-Up Time RMS RxIN Strobe Margin (Note 2) and (Figure 7) Conditions F = 85 MHz Min Max Units 25 85 MHz 10 ms 400 ps Note 2: Receiver Strobe Margin is defined as the valid data sampling region at the receiver inputs. 20101407 FIGURE 7. FPD-Link Receiver Input Skew Margin www.national.com 6 TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) (Continued) Ring Oscillator Characteristics Symbol RESOSC Parameter Ring Oscillator Clock Frequency Conditions Min R = 14.5KΩ; VDD= 2.5V Typ Max 40 Units MHz 20101416 FIGURE 8. Application diagram of Ring Oscillator 7 www.national.com FPD87208AXA AC Electrical Characteristics FPD87208AXA AC Electrical Characteristics TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) (Continued) 20101408 FIGURE 9. FPD-Link Receiver Phase Lock Loop Wake-Up Time 20101409 Note: R/G/B[7]s are MSBs and R/G/B[0]s are LSBs FIGURE 10. FPD-Link Receiver Input Data Mapping www.national.com 8 FPD87208AXA AC Electrical Characteristics TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) (Continued) Output Timing RT = 100Ω, IPI = 100 µA, f = 85 MHz (Unless otherwise specified) Symbol Parameter Conditions RCHP RSDS Clock (RSCK) High Period CL(RSDS) = 5 pF RCLP RSDS Clock (RSCK) Low Period CL(RSDS) = 5 pF SPSTU STH Rising to RSCK Falling SPHLD STH Falling to RSCK Falling RSTU (Note 3) RSDS Setup to Falling or Rising Edge of RSCK RHLD (Note 3) RSDS Hold from Falling or Rising Edge of RSCK Min Typ Max Units 5.8 ns 5.8 CL(TTL) = 15 pF ns 4.0 ns 4.0 ns CL(RSDS) = 5 pF RSDS[2:0]=[011] 3.3 ns 2.1 ns Note 3: Refer to the table “RSDS Setup and Hold Time with Data Skew Control Values” for each skew control. RSDS Setup and Hold Time with Data Skew Control Values—Reference Only (RxCLKP/N = 85 MHz, RT = 100Ω, IPI = 100 µA, VDD = 2.5V; Duty Clock = 50%/50%, ± 2%; 25˚C) Note: Typical values on this table are measured under Static and Steady state conditions which may not be reflective of its performance in the end application. RSDS[2:0] Setup Time (RSTU, nS) Min Typ Hold Time (RHLD, nS) Max Min Typ 000 1.83 3.61 001 2.33 3.09 010 2.83 2.61 011 3.31 2.10 100 3.85 1.55 101 4.34 1.03 110 4.81 0.53 111 5.33 0.01 Units Max ns RSDS and TTL Output Tr/Tf Symbol Parameter RSTr/RSTf RSDS Output Rising/Falling Time (All RSDS Outputs) TTL Tr/Tf Conditions CL(RSDS) = 5 pF TTL Output Rising and Falling Time CL = 15 pF (20%–80%) 9 Min Typ Max Units 1.5 ns 2.0 ns www.national.com FPD87208AXA AC Electrical Characteristics TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) (Continued) 20101410 FIGURE 11. RSDS and TTL Output Timing Diagram www.national.com 10 FPD87208AXA AC Electrical Characteristics TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) (Continued) 20101411 FIGURE 12. RSDS Output Data Mapping 11 www.national.com TA = 0˚C to 70˚C, VDD = 2.5V ± 0.25V, IPI = 100 µA (Unless otherwise specified) (Continued) Input Signal Timing—Reference Only Signal Item Symbol Clock Frequency 1/Tclk F Total XGA (1024 x 768) Tv Vertical Timing Active Tvact Total Th Horizontal Timing Active Thact WXGA1 (1280 x 768) WXGA2 (1280 x 800) WXGA3 (1280 x 854) Unit MHz Typ 65 82 68 69 Min 774 774 806 860 Typ 806 806 816 880 Max 1024 1024 1024 1024 Min - - - - Typ 768 768 800 854 Max - - - - Min 1078 1334 1334 1334 Typ 1344 1688 1408 1408 Max 2047 2047 2047 2047 Min 100 100 100 100 Typ 1024 1280 1280 1280 Max - - - - Th Tclk Output Timing—TTL Display Resolution Selection Control DTM1 DTM0 Display Mode Resolution 0 0 WXGA1 1280 x 768 0 1 WXGA2 1280 x 800 1 0 XGA 1024 x 768 1 1 WXGA3 1280 x 854 TTL Timing Selection Control: RO[2:0] XGA RO[2:0] 000 001 010 011 100 101 110 T1 2 2 2 2 2 2 2 111 Unit TCLK T2 1 1 1 1 1 1 1 TCLK T3 1030 1030 1030 1030 1030 1030 1030 TCLK T4 16 24 16 24 32 48 42 TCLK T5 912 960 960 912 842 912 802 TCLK T5' 782 830 830 782 712 782 672 TCLK T6 200 160 160 130 220 220 260 TEST MODE FPD87208AXA AC Electrical Characteristics TCLK T6' 130 130 130 130 130 130 130 T7 1038 1056 1056 976 874 976 834 TCLK T8 650 650 650 650 680 680 725 T9 348 348 348 348 348 348 348 TCLK HLINE TCLK TCLK T10 1 1 1 1 1 1 1 T11 348 348 348 348 348 348 348 TCLK T12 1 1 1 1 1 1 1 HLINE T13* 567 567 567 567 567 567 567 TCLK T14* 2 2 2 2 2 2 2 HLINE *Timing based on first occurrence of STH. www.national.com 12 (Continued) WXGA 000 001 010 011 100 101 110 T1 2 2 2 2 2 2 2 111 TCLK T2 1 1 1 1 1 1 1 TCLK T3 1286 1286 1286 1286 1286 1286 1286 TCLK T4 16 24 16 24 32 48 42 TCLK T5 1168 1216 1216 1168 1098 1168 1058 TCLK T5' 1038 1086 1086 1038 968 1038 928 TCLK T6 200 160 160 130 220 220 260 T6' 130 130 130 130 130 130 130 T7 1294 1312 1312 1232 1130 1232 1090 T8 650 650 650 650 680 680 725 T9 348 348 348 348 348 348 348 TCLK T10 1 1 1 1 1 1 1 HLINE T11 348 348 348 348 348 348 348 TCLK T12 1 1 1 1 1 1 1 HLINE T13* 567 567 567 567 567 567 567 TCLK T14* 2 2 2 2 2 2 2 HLINE TEST MODE RO[2:0] Unit TCLK TCLK TCLK TCLK *Timing based on first occurrence of STH. 13 www.national.com FPD87208AXA Output Timing—TTL FPD87208AXA Output Timing—TTL (Continued) 20101412 FIGURE 13. TTL Output Timing Diagram www.national.com 14 FPD87208AXA Output Timing—TTL (Continued) 20101413 FIGURE 14. TTL Output Timing Diagram (Continued) 15 www.national.com FPD87208AXA Output Timing—Power-Up Sequence (reference only) 20101414 FIGURE 15. Power-Up Sequence www.national.com 16 FPD87208AXA Connection Diagram 20101415 FIGURE 16. Pinout Assignment Pin Descriptions LVDS Rx Inputs Pin Count Type RxIN[0]N/P 2 LVDSI LVDS Rx Data Differential Input Pairs RxIN[1]N/P 2 LVDSI LVDS Rx Data Differential Input Pairs RxIN[2]N/P 2 LVDSI LVDS Rx Data Differential Input Pairs RxCLKN/P 2 LVDSI LVDS Rx Clock Differential Input Pairs Sub-Total Pin Count 8 Symbol Function 17 www.national.com FPD87208AXA Pin Descriptions (Continued) RSDS Tx Outputs Symbol Pin Count Type Function R [2:0]P/N 6 RSO Red Reduced Swing Differential Outputs to Column Drivers G [2:0]P/N 6 RSO Green Reduced Swing Differential Outputs to Column Drivers B [2:0]P/N 6 RSO Blue Reduced Swing Differential Outputs to Column Drivers CLKP/N 2 RSO Clock Reduced Swing Differential Outputs to Column Drivers Sub-Total Pin Count 20 RSDS Tx Bias Reference Input Symbol Pin Count PI 1 Sub-Total Pin Count 1 Type Function Current Reference for RSDS Tx Output (1.23V) CMOS Input (2.75V Maximum) Symbol Pin Count Type Function RSDS[2:0] 3 I RSDS Skew/Timing Control RO[2:0] 3 I Display Timing Selection POLSET 1 I 0: Two Line Inversion; 1: One Line Inversion DTM[1:0] 2 I Display Mode Selection (XGA, WXGA1, WXGA2, WXGA3) RESOSC 1 AI RC oscillator reference for BIST function. 14.5 kΩ = ∼40 MHz IDREV 1 PU IDREV = HIGH (default, pull high): Output data is 3F during vertical blanking. IDREV = LOW: Output data is 00 during vertical blanking. BIST 1 I RESETZ 1 Schmitt I Sub-Total Pin Count 13 BIST Control Function (Active High), tied to ground for norm mode TCON Reset (Active Low) CMOS Outputs (2.75V Maximum) Pin Count Type STV 1 TO Row Driver Start Pulse CPV 1 TO Row Driver Shift Clock TP 1 TO Line Latch Signal Output to Column Drivers STH 1 TO Horizontal Start Signal Output to Column Drivers REV 1 TO Alternative Signal Output for each 1 or 2 Horizontal Line to Column Drivers OE1 1 TO Control TFT Gate Pulse Width to Row Drivers OE2 1 TO Control TFT Gate Pulse Width to Row Drivers Sub-Total Pin Count 7 Symbol www.national.com Function 18 FPD87208AXA Pin Descriptions (Continued) Power Supply Symbol Pin Count Type Function VDD 1 P Digital Power for Logic Core VSS 1 G Digital Ground for Logic Core VDDIO 4 P Digital I/O and RSDS Power VSSIO 4 G Digital I/O and RSDS Ground VDDA 1 P FPD Receiver — Power for Analog VDDD 1 P FPD Receiver — Power for Digital VSSD 1 G FPD Receiver — Ground for Digital VSSP 1 G FPD Receiver — Ground for PLL VSSA 1 G FPD Receiver — Ground for Analog Sub-Total Pin Count 15 Total Pin Count 64 System Interface = 8 RSDS Tx Out = 20 RSDS Tx Bias Reference Input = 1 CMOS Input (control) = 13 CMOS Output = 7 Power Supply = 15 Pin Types AI I TO LVDSI RSO -Analog Input -Input (LVTTL) -TTL Output (LVTTL) -Low Voltage Differential Signal Input -Reduced Swing Differential Output P G PD PU Schmitt I 19 -Power -Ground -Pull Down -Pull Up -Schmitt Triggered Input www.national.com FPD87208AXA +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS Outputs Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead TQFP Package, JEDEC Dimension in millimeters only Order Number FPD87208AXAVS NS Package Number VEC64A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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