LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start General Description Features The LP38853-ADJ is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides voltage to drive the gate of the N-MOS power transistor, while VIN is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of this device makes it suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The part is available in PSOP 8–pin, TO-220 7–pin, and TO-263 7-pin packages. Dropout Voltage: 240 mV (typical) at 3A load current. Low Ground Pin Current: 10 mA (typical) at 3A load current. Soft-Start: Programmable Soft-Start time. Precision ADJ Voltage: ±1.5% for TJ = 25°C, and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions ■ ■ ■ ■ ■ Adjustable VOUT range of 0.80V to 1.8V Wide VBIAS Supply operating range of 3.0V to 5.5V Stable with 10µF Ceramic capacitors Dropout voltage of 240 mV (typical) at 3A load current Precision VADJ across all line and load conditions: — ±1.5% VADJ for TJ = 25°C — ±2.0% VADJ for 0°C ≤ TJ ≤ +125°C — ±3.0% VADJ for -40°C ≤ TJ ≤ +125°C ■ Over-Temperature and Over-Current protection ■ Available in 8 lead PSOP, 7 lead TO-220 and 7 lead TO-263 packages ■ −40°C to +125°C Operating Junction Temperature Range Applications ■ ASIC Power Supplies in: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers ■ Server Core and I/O Supplies ■ DSP and FPGA Power Supplies ■ SMPS Post-Regulator Typical Application Circuit 20131001 © 2006 National Semiconductor Corporation 201310 www.national.com LP38853 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start December 2006 LP38853 Ordering Information VOUT ADJ Order Number Package Type Package Drawing Supplied As LP38853S-ADJ TO263-7 TS7B Rail of 45 LP38853SX-ADJ TO263-7 TS7B Tape and Reel of 500 LP38853T-ADJ TO220-7 TA07B Rail of 45 LP38853MR-ADJ PSOP-8 MR08B Rail of 95 LP38853MRX-ADJ PSOP-8 MR08B Tape and Reel of 2500 Connection Diagrams 20131002 20131003 TO263-7, Top View TO220-7, Top View 20131004 PSOP-8, Top View Pin Descriptions TO220-7 Pin # TO263-7 Pin # PSOP-8 Pin # Pin Symbol 1 1 5 SS Soft-Start capacitor connection. Used to control the rise time of VOUT at turn-on. 2 2 6 EN Device Enable, High = On, Low = Off. 3 3 7 IN The unregulated voltage input 4 4 4 GND Ground 5 5 1 ADJ The feedback connection to set the output voltage 6 6 2 OUT The regulated output voltage 7 7 3 BIAS The supply for the internal control and reference circuitry. - - 8 N/C No internal connection Pin Description TAB TAB - TAB The TO220 and TO263 TAB is a thermal and electrical connection that is physically attached to the backside of the die, and used as a thermal heat-sink connection. See the Application Information section for details. - - DAP DAP The PSOP DAP is a thermal connection only that is physically attached to the backside of the die, and used as a thermal heatsink connection. See the Application Information section for details. www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Lead Temperature Soldering, 5 seconds ESD Rating Human Body Model (Note 2) Power Dissipation (Note 3) VIN Supply Voltage (Survival) VBIAS Supply Voltage (Survival) VSS SoftStart Voltage (Survival) −0.3V to +6.0V Internally Limited −40°C to +150°C Operating Ratings −65°C to +150°C (Note 1) VIN Supply Voltage VBIAS Supply Voltage 0.8V ≤ VOUT ≤ 1.2V 1.2V < VOUT ≤ 1.8V VEN Voltage IOUT Junction Temperature Range (Note 3) 260°C ±2 kV Internally Limited −0.3V to +6.0V −0.3V to +6.0V −0.3V to +6.0V (VOUT + VDO) to VBIAS 3.0V to 5.5V 4.5V to 5.5V 0.0V to VBIAS 0 mA to 3.0A −40°C to +125°C Electrical Characteristics Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V, See (Note 7) 3.0V ≤ VBIAS ≤ 5.5V, MIN TYP MAX 492.5 485.0 500. 507.5 515.0 Units 10 mA ≤ IOUT ≤ 3A VADJ VADJ Accuracy VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V, See (Note 7) 3.0V ≤ VBIAS ≤ 5.5V, mV 490.0 500. 510.0 10 mA ≤ IOUT ≤ 3.0A, 0°C ≤ TJ ≤ +125°C VOUT VOUT Range 3.0V ≤ VBIAS ≤ 5.5V 0.80 1.20 4.5V ≤ VBIAS ≤ 5.5V 0.80 1.80 V Line Regulation, VIN (Note 4) VOUT(NOM)+1V ≤ VIN ≤ VBIAS - 0.04 - %/V ΔVOUT/ΔVBIAS Line Regulation, VBIAS (Note 4) 3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V ΔVOUT/ΔIOUT Output Voltage Load Regulation (Note 5) 10 mA ≤ IOUT ≤ 3.0A - 0.2 - %/A Dropout Voltage (Note 6) IOUT = 3.0A - 240 300 450 mV VOUT = 0.80V VBIAS = 3.0V - 7.0 8.5 9.0 mA 1 10 300 μA 3.0 3.8 4.5 mA 100 170 200 μA 2.20 2.00 2.45 2.70 2.90 V 60 50 150 300 350 mV - 5.8 - A ΔVOUT/ΔVIN VDO IGND(IN) Quiescent Current Drawn from VIN Supply 10 mA ≤ IOUT ≤ 3.0A VEN ≤ 0.5V IGND(BIAS) Quiescent Current Drawn from VBIAS Supply 10 mA ≤ IOUT ≤ 3.0A VEN ≤ 0.5V UVLO Under-Voltage Lock-Out Threshold VBIAS rising until device is functional UVLO(HYS) Under-Voltage Lock-Out Hysteresis VBIAS falling from UVLO threshold until device is non-functional Output Short-Circuit Current VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VOUT = 0.0V ISC - 3 www.national.com LP38853 VOUT Voltage (Survival) IOUT Current (Survival) Junction Temperature Absolute Maximum Ratings (Note 1) LP38853 Symbol Parameter Conditions MIN TYP MAX Units 11.0 13.5 16.0 kΩ CSS = 10 nF - 675 - μs VEN = VBIAS - 0.01 - VEN = 0.0V, VBIAS = 5.5V -19 -13 -30 -40 -51 1.00 0.90 1.25 1.50 1.55 V 50 30 100 150 200 mV Soft-Start rSS Soft-Start internal resistance tSS Soft-Start time tSS = CSS × rSS × 5 Enable IEN ENABLE pin Current VEN(ON) Enable Voltage Threshold VEN rising until Output = ON VEN(HYS) Enable Voltage Hysteresis VEN falling from VEN(ON) until Output = OFF tOFF Turn-OFF Delay Time RLOAD x COUT << tOFF - 20 - tON Turn-ON Delay Time RLOAD x COUT << tON - 15 - VIN = VOUT(NOM) + 1V, f = 120 Hz - 80 - VIN = VOUT(NOM) + 1V, f = 1 kHz - 70 - VBIAS = VOUT(NOM) + 3V, f = 120 Hz - 58 - VBIAS = VOUT(NOM) + 3V, f = 1 kHz - 58 - f = 120 Hz - 1 - BW = 10 Hz − 100 kHz - 150 - BW = 300 Hz − 300 kHz - 90 - Thermal Shutdown Junction Temperature - 160 - Thermal Shutdown Hysteresis - 10 - TO220-7 - 60 - TO263-7 - 60 - PSOP-8 - 168 - TO220-7 - 3 - TO263-7 - 3 - PSOP-8 - 11 - μA µs AC Parameters PSRR (VIN) PSRR (VBIAS) Ripple Rejection for VIN Input Voltage Ripple Rejection for VBIAS Voltage Output Noise Density en Output Noise Voltage dB µV/√Hz µVRMS Thermal Parameters TSD TSD(HYS) θJ-A θJ-C Thermal Resistance, Junction to Ambient(Note 3) Thermal Resistance, Junction to Case(Note 3) °C °C/W Note 1: Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114. Note 3: Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Note 4: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Note 5: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Note 6: Dropout voltage is defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. Note 7: VIN cannot exceed either VBIAS or 4.5V, whichever value is lower. www.national.com 4 Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature 20131087 20131061 VIN Ground Pin Current vs Temperature Load Regulation vs Temperature 20131063 20131062 Dropout Voltage (VDO) vs Temperature Output Current Limit (ISC) vs Temperature 20131065 20131066 5 www.national.com LP38853 Typical Performance Characteristics LP38853 VOUT vs Temperature VOUT vs VIN 20131067 20131072 UVLO Thresholds vs Temperature Soft-Start rSS Variation vs Temperature 20131068 20131075 VOUT vs CSS, 10 nF to 47 nF Enable Thresholds (VEN) vs Temperature 20131076 www.national.com 20131088 6 Enable Pull-Up Resistor (rEN) vs Temperature 20131089 20131090 VIN Line Transient Response VIN Line Transient Response 20131077 20131078 VBIAS Line Transient Response VBIAS Line Transient Response 20131079 20131080 7 www.national.com LP38853 Enable Pull-Down Current (IEN) vs Temperature LP38853 Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 10 µF Ceramic 20131081 20131082 Load Transient Response, COUT = 100 µF Ceramic Load Transient Response, COUT = 100 µF Ceramic 20131083 20131084 Load Transient Response, COUT = 100 µF Tantalum Load Transient Response, COUT = 100 µF Tantalum 20131085 www.national.com 20131086 8 LP38853 VBIAS PSRR VIN PSRR 20131070 20131071 Output Noise 20131069 9 www.national.com LP38853 Block Diagram 20131005 www.national.com 10 EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. FP = (1 / (2 x π x CFF x (R1 || R2) ) ) Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or Aluminum, to be added in parallel. (4) It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT = VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output voltages. For the LP38853, the practical minimum VOUT is 0.8V when a ceramic capacitor is used for COUT. Input Capacitor The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C. Bias Capacitor The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is recommended). 20131021 FIGURE 1. FZERO and FPOLE vs Gain Feed Forward Capacitor, CFF (Refer to the Typical Application Circuit) When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop. FZ = (1 / (2 x π x COUT x ESR) ) SETTING THE OUTPUT VOLTAGE (Refer to the Typical Application Circuit) The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: (5) (1) The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of VADJ is guaranteed, the use of low quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable. It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the formula: FZ = (1 / (2 x π x CFF x R1) ) (2) For optimum load transient response select CFF so the zero frequency, FZ, falls between 10 kHz and 15 kHz. (CFF = (1 / (2 x π x R1 x FZ) ( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ (6) Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give similar results. (3) 11 www.national.com LP38853 The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is because CFF also forms a pole with a frequency of: Application Information LP38853 diode clamped to ground. A Schottky diode is recommended for this diode clamp. TABLE 1. VOUT R2 CFF FZ R1 0.8V 1.07 kΩ 1.78 kΩ 12 nF 12.4 kHz 0.9V 1.0V 1.50 kΩ 1.87 kΩ 8.2 nF 12.9 kHz 1.00 kΩ 1.00 kΩ 12 nF 13.3 kHz 1.1V 1.65 kΩ 1.37 kΩ 8.2 nF 11.8 kHz 1.2V 1.40 kΩ 1.00 kΩ 10 nF 11.4 kHz 1.3V 1.15 kΩ 715 Ω 12 nF 11.5 kHz 1.4V 1.07 kΩ 590 Ω 12 nF 12.4 kHz 1.5V 2.00 kΩ 1.00 kΩ 6.8 nF 11.7 kHz 1.6V 1.65 kΩ 750 Ω 8.2 nF 11.8 kHz 1.7V 2.55 kΩ 1.07 kΩ 5.6 nF 11.1 kHz 1.8V 2.94 kΩ 1.13 kΩ 4.7 nF 11.5 kHz REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the Enable pin is held low. When VBIAS is above the UVLO threshold, and the Enable pin is above the VEN(ON) threshold, the control circuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. Please refer to Application Note AN-1378 for additional information on how resistor tolerances affect the calculated VOUT value. INPUT VOLTAGE The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. For applications where VBIAS is higher than 4.5V, VIN must be no greater than 4.5V, otherwise output voltage accuracy may be affected. SOFT-START The LP38853 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor (COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin. The soft-start timing capacitor (CSS) is internally held to ground until both VBIAS rises above the Under-Voltage Lock-Out threshold (ULVO) and the Enable pin is higher than the VEN(ON) threshold. VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in current limit. BIAS VOLTAGE The bias voltage (V BIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V , VBIAS must be between 4.5V and 5.5V to ensure proper operation of the device. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the device will be functional, but the operating parameters will not be within the guaranteed limits. Soft-Start Time = CSS × rSS × 5 Since the VOUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ), and VOUT will require four additional time constants (4τ) to reach the final value (5τ) . After achieving normal operation, should either VBIAS fall below the ULVO threshold, or the Enable pin fall below the VEN (OFF) threshold, the device output will be disabled and the SoftStart capacitor (CSS) discharge circuit will become active. The CSS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When VBIAS falls below 500 mV (typical), the CSS discharge circuit will cease to function due to a lack of sufficient biasing to the control circuitry. Since VREF appears on the SS pin, any leakage through CSS will cause VREF to fall, and thus affect VOUT. A leakage of 50 nA (about 10 MΩ) through CSS will cause VOUT to be approximately 0.1% lower than nominal, while a leakage of 500 nA (about 1 MΩ) will cause VOUT to be approximately 1% lower than nominal. Typical ceramic capacitors will have a factor of SUPPLY SEQUENCING There is no requirement for the order that VIN or VBIAS are applied or removed. One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point the benefits of Soft-Start will be compromised. In any case, the output voltage cannot be guaranteed until both VIN and VBIAS are within the range of guaranteed operating values. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be www.national.com (7) 12 The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: PD(PASS) = (VIN - VOUT) × IOUT (8) The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula: PD(BIAS) = VBIAS × IGND(BIAS) (9) where IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS. The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula: PD(IN) = VIN × IGND(IN) (10) where IGND(IN) is the portion of the operating ground current of the device that is related to VIN. The total power dissipation is then: 20131023 PD = PD(PASS) + PD(BIAS) + PD(IN) (11) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)) . FIGURE 2. Typical CSS vs COUT Values The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT. If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value is always recommended. (12) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: (13) ENABLE OPERATION The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has an internal pull-up, through a typical 180 kΩ resistor, to VBIAS. If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off. There is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity. If the Enable function is not needed this pin should be left open, or connected directly to VBIAS. If the Enable pin is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while the stray capacitance is charged through the internal resistance (rEN). Heat-Sinking The TO-220 Package The TO220-5 package has a θJA rating of 60°C/W and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. If the needed θJA, as calculated above, is greater than or equal to 60°C/W then no additional heat-sinking is required since the package can safely dissipate the heat and not exceed the operating TJ(MAX). If the needed θJA is less than 60°C/W then additional heat-sinking is needed. The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO-263 package. The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA: POWER DISSIPATION AND HEAT-SINKING Additional copper area for heat-sinking may be required depending on the maximum device dissipation (PD) and the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. (14) where θJA is the required total thermal resistance from the junction to the ambient air, θCH is the thermal resistance from the case to the surface of the heart-sink, and θJC is the thermal resistance from the junction to the surface of the case. 13 www.national.com LP38853 10X difference in leakage between 25°C and 85°C, so the maximum ambient temperature must be included in the capacitor selection process. Typical CSS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100 nF will provide soft-start, but may not be fully discharged if VBIAS falls from the UVLVO threshold to less than 500 mV in less than 100 µs. Figure 2 shows the relationship between the COUT value and a typical CSS value. LP38853 ing θJA is 35°C/W and the maximum junction temperature is 125°C. For this equation, θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details and recommendations. Heat-Sinking The PSOP-8 Package The LP38853MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W includes the device DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper, with no airflow. Heat-Sinking The TO-263 Package The TO-263 package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. The TO-263 package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the copper plane for heat sinking. Figure 3 shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat-sinking. 20131027 FIGURE 5. θJA vs Copper (1 Ounce) Area for the PSOP-8 Package Increasing the copper area soldered to the DAP to 1 square inch of 1 ounce copper, using a dog-bone type layout, will improve the θJA rating to 98°C/W. Figure 5 shows that increasing the copper area beyond 1 square inch produces very little improvement. 20131025 FIGURE 3. θJA vs Copper (1 Ounce) Area for the TO-263 package Figure 3 shows that increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 package mounted to a PCB is 32°C/W. 20131028 FIGURE 6. Maximum Power Dissipation vs Ambient Temperature for the PSOP-8 Package Figure 6 shows the maximum allowable power dissipation for the PSOP-8 package for a range of ambient temperatures, assuming θJA is 98°C/W and the maximum junction temperature is 125°C. 20131026 FIGURE 4. Maximum Power Dissipation vs Ambient Temperature for the TO-263 Package Figure 4 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assumwww.national.com 14 LP38853 Physical Dimensions inches (millimeters) unless otherwise noted TO-220 7-Lead, Stagger Bend Package (TO220-7) NS Package Number TA07B TO-263 7-Lead, Molded, Surface Mount Package (TO263-7) NS Package Number TS7B 15 www.national.com LP38853 PSOP, 8 Lead, Molded, 0.050in Pitch NS Package Number MRA08B www.national.com 16 LP38853 Notes 17 www.national.com LP38853 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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