DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer General Description The DS8908B is a PLL synthesizer designed specifically for use in AM/FM radios. It contains the reference oscillator, a phase comparator, a charge pump, an operational amplifier, a 120 MHz ECL/I2L dual modulus programmable divider, and a 19-bit shift register/latch for serial data entry. The device is designed to operate with a serial data controller generating the necesary division codes for each frequency, and logic state information for radio function inputs/outputs. A 3.96 MHz pierce oscillator and divider chain generate a 1.98 MHz external controller clock, a 20 kHz, 10 kHz, 9 kHz, and a 1 kHz reference signals, and a 50 Hz time-of-day signal. The oscillator and divider chain are sourced by the VCCM pin thus providing a low power controller clock drive and time-of-day indication when the balance of the PLL is powered down. The 21-bit serial data steram is transferred between the frequency synthesizer and the controller via a 3-wire bus system comprised of a data line, a clock line, and an enable line. The first 2 bits in the serial data stream address the synthesizer thus permitting other devices such as display drivers to share the same bus. The next 14 bits are used for the PLL(N a 1) divide code. The 15th bit is used internally to select the AM or FM local oscillator input. A high level on this bit enables the FM input and a low level enables the AM input. The 16th and 17th bits are used to select one of the 4 reference frequencies. The 18th and 19th bits are connected via latches to open collector outputs. These outputs can be used to drive radio functions such as gain, mute, AM, FM, or charge pump current source levels. The PLL consists of a 14-bit programmable I2L divider, an ECL phase comparator, an ECL dual modulus (p/p a 1) prescaler, a high speed charge pump, and an operational amplifier. The programmable divider divides by (N a 1), N being the number loaded into the shift register. The programmable divider is clocked through a d -/8 prescaler by the AM input or through a d $*/64 prescaler by the FM input. The AM input will work at frequencies up to 15 MHz, while the FM input works up to 120 MHz. The VCO can be tuned with a frequency resolution of either 1 kHz, 9 kHz, 10 kHz, or 20 kHz. The buffered AM and FM inputs are self-biased and can be driven directly by the VCO through a capacitor. The ECL phase comparator produces very accurate resolution of the phase difference between the input signal and the reference oscillator. The high speed charge pump consists of a switchable constant current source and sink. The charge pump can be programmed to deliver from 75 mA to 750 mA of constant current by connection of an external resistor from pin RPROGRAM to ground or the open collector bit outputs. Connection of programming resistors to the bit outputs enables the controller to adjust the loop gain for the particular reference frequency selected. The charge pump will source current if the VCO frequency is high and sink current if the VCO frequency is low. The low noise operational amplifier provided has a high impedance JFET input and a large output voltage range. The op amp’s negative input is common with the charge pump output and its positive input is internally biased. Features Y Y Y Y Y Y Y Y Y Uses inexpensive 3.96 MHz reference crystal FIN capability greater than 120 MHz allows direct synthesis at FM frequencies FM resolution of either 10 kHz or 20 kHz allows usage of 10.7 MHz ceramic filter distribution Serial data entry for simplified control 50 Hz output for time-of-day reference driven from separate low power VCCM 2 open collector buffered outputs for controlling various radio functions or loop gain Separate AM and FM inputs; AM input has 15 mV (typical) hysteresis Programmable charge pump current sources enable adjustment of system loop gain Operational amplifier provides high impedance load to charge pump output and a wide voltage range for the VCO input Connection Diagram Dual-In-Line Package Top View Order Number DS8908BN See NS Package Number N20A TL/F/5111 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/5111 RRD-B30M105/Printed in U. S. A. DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer June 1990 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Storage Temperature Range Lead Temperature (Soldering, 4 seconds) 260§ C Supply Voltage (VCC1) (VCCM) (VCC2) Input Voltage Output Voltage Operating Conditions 7V 17V 7V 7V VCC1 VCC2 VCCM Temperature, TA Min 4.5 Max 5.5 15.0 5.5 a 85 VCC1 a 1.5 3.5 b 40 Units V V V §C DC Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions Min VIH Logical ‘‘1’’ Input Voltage IIH Logical ‘‘1’’ Input Current VIL Logical ‘‘0’’ Input Voltage IIL Logical ‘‘0’’ Input Current Data, Clock, and ENABLE Inputs, VIN e 0V IOH Logical ‘‘1’’ Output Current All Bit Outputs, 50 Hz Output VOH e 5.5V 1.98 MHz Output VOH e 2.4V, VCCM e 4.5V Logical ‘‘0’’ Output Voltage All Bit Outputs IOL e 5 mA VOL Typ Max Units 0 10 mA 0.8 V b5 b 25 mA 50 mA b 250 mA 0.5 V 2.0 V VIN e 2.7V 50 Hz Output, 1.98 MHz Output IOL e 250 mA 0.5 V 1.98 MHz Output IOL e 20 mA, TA l 70§ C IOL e 20 mA, TA s 70§ C 0.3 0.4 V V ICC1 Supply Current (VCC1) All Bit Outputs High ICCM VCCM Supply Current VCCM e 5.5V, All Other Pins Open IOUT Charge Pump Ougtput Current 3.33k s RPROG s 33.3k IOUT Measured between Pin 17 and Pin 18 IPROG e VCC1/2 RPROG 160 mA 2.5 4.0 mA Pump Up b 20 IPROG a 20 % Pump Down b 20 IPROG a 20 % 0 11 nA 6.7 11 TRI-STATEÉ ICC2 VCC2 Supply Current VCCM e 5V, VCC1 e 5.5V, VCC2 e 15V All Other Pins Open mA OPVOH Op Amp Minimum High Level VCC1 e 4.5V, IOH e b750 mA OPVOL Op Amp Maximum Low Level VCC1 e 5.5V, IOL e 750 mA 0.6 V CPOBIAS Charge Pump Bias Voltage Delta CPO Shorted to Op Amp Output CPO e TRI-STATE Op Amp IOL: 750 mA vs b750 mA 100 mV VCC2 b0.4 V AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr s 10 ns, tf s 10 ns Symbol Parameter Conditions VIN(MIN)(F) FIN Minimum Signal Input AM and FM Inputs, b40§ C s TA s 85§ C VIN(MAX)(F) FIN Maximum Signal Input AM and FM Inputs, b40§ C s TA s 85§ C FOPERATE Operating Frequency Range (Sine Wave Input) VIN e 100 mV rms b 40§ C s TA s 85§ C Min Typ Max Units 20 100 mV(rms) 1000 1500 mV(rms) AM 0.5 15 MHz FM 80 120 MHz RIN(FM) AC Input Resistance, FM 120 MHz, VIN e 100 mV rms 600 X RIN(AM) AC Input Resistance, AM 15 MHz, VIN e 100 mV rms 1000 X CIN Input Capacitance, FM and AM VIN e 120 MHz (FM), 15 MHz (AM) tEN1 Minimum ENABLE High Pulse Width 2 3 6 10 pF 625 1250 ns AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr s 10 ns, tf s 10 ns (Continued) Typ Max Units tEN0 Symbol Minimum ENABLE Low Pulse Width 375 750 ns tCLKEN0 Minimum Time before ENABLE Goes Low That CLOCK Must Be Low b 50 0 ns Minimum Time after ENABLE Goes Low That CLOCK Must Remain Low 275 550 ns Minimum Time before ENABLE Goes High That Last Positive CLOCK Edge May Occur 300 600 ns Minimum Time after ENABLE Goes High before an Unused Positive CLOCK Edge May Occur 175 350 ns tCLKH Minimum CLOCK High Pulse Width 275 550 ns tCLKL Minimum CLOCK Low Pulse Width 400 800 ns tDS Minimum DATA Set-Up Time, Minimum Time before CLOCK That DATA Must Be Valid 150 300 ns Minimum DATA Hold Time, Minimum Time after CLOCK That DATA Must Remain Valid 400 800 ns tEN0CLK tCLKEN1 tEN1CLK tDH Parameter Conditions Min Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the b 40§ C to a 85§ C temperature range for the DS8908B. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Schematic Diagrams (DS8908B AM/FM PLL Typical Input/Output Schematics) TL/F/5111 – 4 TL/F/5111–2 TL/F/5111 – 3 3 Schematic Diagrams (Continued) TL/F/5111 – 6 TL/F/5111 – 7 TL/F/5111–5 TL/F/5111 – 8 4 Schematic Diagrams (Continued) TL/F/5111 – 9 Timing Diagrams* ENABLE vs CLOCK TL/F/5111 – 10 CLOCK vs DATA TL/F/5111 – 11 5 Timing Diagrams* (Continued) AM/FM Frequency Synthesizer (Scan Mode) TL/F/5111 – 12 *Timing diagrams are not drawn to scale. Scale within any one drawing may not be consistent, and intervals are defined positive as drawn. These data bits are interpreted as follows: Data Bit Position Data Interpretation Last Bit 19 Output (Pin 2) 2nd to Last Bit 18 Output (Pin 1) 3rd to Last Ref. Freq. Select Bit(1)17 4th to Last Ref. Freq. Select Bit(1)16 5th to Last AM/FM Select Bit 15 6th to Last (213) 7th to Last (212) 8th to Last (211) 9th to Last (210) 10th to Last (29) 11th to Last (28) 12th to Last (27) d N(2) 13th to Last (26) 5 14th to Last (2 ) 15th to Last (24) 16th to Last (23) 17th to Last (22) 18th to Last (21) 19th to Last LSB of d N(20) SERIAL DATA ENTRY INTO THE DS8908B Serial information entry into the DS8908B is enabled by a low level on the ENABLE input. One binary bit is then accepted from the DATA input with each positive transition of the CLOCK input. The CLOCK input must be low for the specified time preceding and following the negative transition of the ENABLE input. The first two bits accepted following the negative transition of the ENABLE input are interpreted as address. If these address bits are not 1,1 no further information will be accepted fromt he DATA inputs, and the internal data latches will not be changed when ENABLE returns high. If these first two bits are 1,1, then all succeeding bits are accepted as data, and are shifted successively into the internal shift register as long as ENABLE remains low. Any data bits preceding the 19th to last bit will be shifted out, and thus are irrelevant. Data bits are counted as any bits following two valid address bits (1,1) with the ENABLE low. When the ENABLE input returns high, any further serial data entry is inhibited. Upon this positive transition, the data in the internal shift register is transferred into the internal data latches. Note that until this time, the states of the internal data latches have remained unchanged. - Note 1: See Reference Frequency Select Truth Table. Note 2: The actual divide code is N a 1, ie., the number loaded plus 1. Truth Table Reference Frequency Selection Truth Table Reference Frequency Serial Data Bit 16 Bit 17 (kHz) 1 1 0 0 1 0 1 0 20 10 9 1 6 Typical Application Additional application notes are located at the back of section 11. Electronically Tuned Radio Controller System; Direct Drive LED TL/F/5111 – 13 7 8 *Sections operating from VCCM supply. **Address (1,1) AM/FM PLL/Synthesizer (Serial Data 20-Pin Package) TL/F/5111 – 14 Logic Diagram 9 DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DS8908BN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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