CLC5509 Ultra-Low Noise Preamplifier General Description Features The CLC5509 is a high performance, ultra-low noise preamplifier designed for applications requiring unconditional stability for wide ranges of complex input loads. Both input impedance and gain are externally adjustable, which make it simple to interface to peizoelectric ultrasound transducers. The CLC5509 preamplifier’s low 0.58nV total input noise makes it ideal for noise sensitive front ends. The high repeatability in group delay over voltage and temperature translates into precision edge measurements for Doppler applications. The IC consists of an emitter input, common base amplifier stage followed by a low distortion, closed loop buffer. External negative feedback creates a well controlled input impedance to allow a near noiseless active input transmission line termination. The preamp is stable against changes in source impedance of 50 to 200Ω over temperature and supply variations, with gains from 14dB to 26dB. The CLC5509 preamp architecture is also well suited for use with magneto-resistive tape or disk drive heads. In these applications the head bias current can be reused to bias the preamp. The part is packaged in an 8-pin plastic SOIC, and runs off ± 5V supplies. External biasing is required for the input signal path. The CLC5509 is constructed using an advanced complementary bipolar process and National Semiconductor’s proven high performance architectures. n n n n n n n n 0.58nV total input noise @ 12MHz < .5ns group delay repeatability High cutoff −3dB @ 33MHz Low cutoff −3dB @ 0.5MHz 2.0dB noise figure @ 50Ω −60dBc intermod for 2VPP @ 5MHz Supply current: 11mA Available in 8-pin SOIC Applications n Ultrasound preamp n Tape drive preamp n Disk drive preamp Group Delay Repeatability DS101304-1 Connection Diagram DS101304-3 Pinout SOIC © 2000 National Semiconductor Corporation DS101304 www.national.com CLC5509 Ultra-Low Noise Preamplifier January 2000 CLC5509 Typical Application DS101304-2 Ultrasound PreAmp Ordering Information Package 8-pin SOIC www.national.com Temperature Range Industrial 0˚C to 70˚C CLC5509CM Packaging Marking Transport Media NSC Drawing CLC5509CM Rails M08A 2 Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec) ESD Rating (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± 5.5V Supply Voltage Output Current ± VCC +150˚C −65˚C to +150˚C +300˚C 4000V 70mA Electrical Characteristics (Note 3) (VCC, VEE = ± 5V, RS = 50Ω, AV = 10V/V, Rg = 1kΩ, RL = 100Ω; unless specified) Symbol Parameter Ambient Temperature Conditions CLC5509 Typ Min/Max Ratings (Note 2) +25˚C +25˚C Units Frequency Domain Response -3dB Bandwidth VO < 2.0VPP High Cutoff −3dB 33 28 45 MHz Low Cutoff −3dB 0.5 0.4 0.7 MHz Gain Flatness Inband 2 < 12.5MHz, VO < 1.0VPP −1.5 +.1 dB ± 0.3 Gain Accuracy @ 5MHz dB Phase Variation 3 < 9MHz, VO < .1VPP 1 Deg Gain Variation 3 < 9MHz, VO < .1VPP .3 dB Rise and Fall Time 2V step 10 Settling Time to 0.2% 2V step 1 Overshoot 2V step 0 5 % Group Delay 2.5MHz < 10MHz, VIN 5.5 3 7.5 ns Time Domain Response = 10mVPP Group Delay Repeatability 10 15 ns µs .5 ns < 12.5MHz, VIN = 100mVPP −51 dBc −56 dBc Intermodulation Distortion @ 5MHz −65 dBc Equivalent Input Noise Voltage (eni) > 1MHz, RS = 50Ω 0.7 0.78 Noise Figure @ 50Ω 2 2.4 dB 85 80 110 Ω Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion Optimum RS nV Static, DC Performance < 1MHz RL = ∞ 40 9 11 mA Output Impedance DC < 12MHz 0.2 0.2 1 Ω Output Voltage Range RL = 100Ω ±2 ± 45 ± 1.7 ± 35 PSRR (preamp only) Supply Current (preamp only) dB Miscellaneous Performance Output Current 3 V mA www.national.com CLC5509 Absolute Maximum Ratings (Note 1) CLC5509 Electrical Characteristics (Note 3) (Continued) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: All data taken in circuit shown as typical application. Typical Performance Characteristics Frequency Response Frequency Response DS101304-4 Frequency Response DS101304-5 Group Delay DS101304-7 DS101304-6 Group Delay 3rd Harmonic Distortion DS101304-8 www.national.com DS101304-9 4 (Continued) 3rd Harmonic Distortion 2rd Harmonic Distortion DS101304-10 2rd Harmonic Distortion CLC5509 Typical Performance Characteristics DS101304-11 Intermodulation Distortion DS101304-12 DS101304-13 Total Input Referred Noise (RS = 50Ω) Intermodulation Distortion DS101304-14 DS101304-15 5 www.national.com CLC5509 Typical Performance Characteristics (Continued) Total Input Referred Noise (RS = 50Ω) Total Input Referred Noise (RS = 100Ω) DS101304-16 Total Input Referred Noise (RS = 100Ω) DS101304-17 Total Input Referred Noise (RS = 200Ω) DS101304-18 Total Input Referred Noise (RS = 200Ω) DS101304-19 Zin DS101304-20 www.national.com DS101304-21 6 (Continued) Zin ZO DS101304-22 ZO CLC5509 Typical Performance Characteristics DS101304-23 Positive PSRR (VCC) DS101304-24 Positive PSRR (VCC) DS101304-25 Negative PSRR (VEE) DS101304-26 DS101304-27 7 www.national.com CLC5509 Typical Performance Characteristics (Continued) Negative PSRR (VEE) DS101304-28 Application Information Introduction The CLC5509 is a two stage ultra-low noise preamplifier, with low distortion, and externally variable input impedance. The unusual emitter driven input stage remains stable for a wide range of transducer source loads. The input termination can be matched (for 50-200Ω source matching) to a wide range of complex loads (CS up to 5000pF and CP up to 10000pF, LS up to 1µH). The IC was designed for low cost multiple channel ultrasound applications requiring flexible configurations for a variety of transmit/receive topologies. In a typical application, the CLC5509 is connected to a single element of an ultrasound transducer through a transmit/receive switch. Theory of Operation The CLC5509 simplified circuit is shown in Figure 1. For analysis, the transmit/receive switch diode is modeled in the circuit as a series resistance RTR with a voltage drop of VRT. A piezo transducer generated, single-ended voltage signal is applied to the emitter input of the 1st stage. The voltage signal is converted to a current (i) that is passed through a high pass filter then restored back to a voltage signal at Rg. A high speed, low distortion, unity gain buffer, applies the signal to the load and feedback resistor. Negative feedback from the buffer output to the inverting input completes the signal path. DS101304-29 FIGURE 1. Simplified Circuit The input and output voltage can be expressed as shown: Vin = (RTR + re) i + VO (R1/(R1 + R2)) VO = −(i x Rg) for α = 1 The input resistance is calculated The current IBIAS1 is the input stage emitter current that sets re. IBIAS1 = (VEE - VTR)/RBIAS1 for VEE = VTR = .65V re = 26mV/IBIAS1 Combining terms, then solving for close loop gain VO/Vin results in www.national.com 8 bench setup is fairly simple using the evaluation board and a spectrum analyzer. (If a noise figure meter is available that is even easier yet.) The procedure requires calibrating out the spectrum analyzer background noise, and other noise sources from the CLC5509 noise. Since the thermal noise of a resistor is well known, add a series resistor R4 between the signal source Vin and the L1, RBIAS1 bias network for these noise measurements. Several R4 resistor values are used as ’’reference’’ noise sources. The values chosen depend on the Rs of the system. For Rs = 50Ω, resistor (R4) with values of 0, 12.5, 25, 50Ω should be used. If Rs = 200Ω, resistors (R4) with values of 0, 25, 50, 100, 200Ω should be used. Start by connecting the analyzer input to the evaluation board output. Remove R4 from the signal source and connect R4 to GND. Now take at least 10 measurements and average them for each R4 reference value. Be sure to divide the result by the analyzer and circuit gain to make the noise input referred. Subtract the R4 = 0Ω results from the data for each value. Compare the result to the theoretical noise values. They should agree closely over the Rs = 0 to Rin range. This verifies the test method. The CLC5509 noise is the Rs = 0Ω data point. A similar procedure can be used to remove the T/R switch noise by varying the T/R bias current IBIAS1. The total circuit noise performance can now be optimized for Rin as described above. Evaluation Board Evaluation boards are available for customer product evaluation for the 8-pin SOIC. Evaluation kits that contain an evaluation board and CLC5509 samples can be obtained by calling National Semiconductor’s Customer Service Center. The evaluation kit number is CLC730101. The evaluation board utilizes surface mount components. The corner frequencies are set to ∼ 0.9MHz to 12.5MHz with a passband gain set at 20dB. The highpass filter is set at Rg = 1k, C2 = 470pF to view small signal (Vin < 25mV) performance. Increasing C4 (to > 1500pF) reduces the bandwidth and improves distortion for large signals. R9, is a back match resistor that terminates the output and isolates cable capacitance, for minimum distortion, over the frequency band of interest. An Rin ∼ 50.2Ω was chosen for Rs = 50Ω (this source resistor Rs is open ) and RTR = 0, with IBIAS1 set to 3mA. The expected input referred noise based on bench measurements on similar boards is ∼ 0.6nV or a NF of 2dB. The noise can be optimized with slight variations in R2, Rg and RBIAS1. If transmit/receive switches are added to the evaluation board both the voltage drop and RTR should be compensated for. The Rin, gain and noise will be affected by the addition of the T/R switch. The VTR drop can be removed, to a first order, by adding a second switch in series with the feedback gain setting resistor R1 to ground. This will restore the input DC level to ∼ 0V. This T/R switch diode should be biased with a resistor (∼ RBIAS2) to VCC and bypassed with a 0.1µF cap to maintain the same AC performance as the evaluation board without the switches. CLC5509 Applications The signal path for a typical ultrasound transceiver is shown in Figure 3. (Continued) Choosing External Component Values There are three key parameters to consider in the design: Noise, signal bandwidth, and gain. Refer to Figure 2. The best noise performance for a given transmit/receive switch RTR is obtained by: choosing RS between 50Ω and 200Ω; selecting the matching termination resistance Rin; and by reducing IBIAS1 (by increasing RBIAS1) to increase re which optimizes the Noise Figure (NF). For this circuit, with RTR = 6Ω, the optimum NF is achieved at Rs ∼ 95Ω when Rin is set to 50Ω and Rs ∼ 145Ω when Rin is set to 200Ω. The signal bandwidth is determined by the selection of L1, L2, RBIAS1 and RBIAS2 which set the open loop gain roll-off of the first stage. Rg and C2 form a desirable signal path filter that introduces an additional highpass pole. The filter values can be chosen to create a sharper high frequency roll off of the closed loop gain. For Rg = 1k, C2 ∼ 470pF the small signal (Vin < 25mW), wide bandwidth performance can be observed. By increasing C2 (to > 1500pF) and increasing output series resistance with a small resistor, the stability and harmonic distortion performance can be improved for large signals. This filter can also be designed as a multi-pole Butterworth filter but care must be taken to ensure stability with the desired load over the operating temperature range. The passband gain is customer selected by setting Rg and Rin. Note that using R1 to reduce or increase the gain allows for minimal interaction with other parameters. Capacitor CC and resistor RC are used for local compensation of the gm input stage with values of CC = 0.1µF and RC = 1k for the applications described below. DS101304-32 FIGURE 2. Complete Circuit Calculating and Measuring the Noise The circuit input referred noise is best calculated using a SPICE model where the external components can be optimized for the transducer source impedance and transmit/receive switch impedance. The SPICE model for the CLC5509 is available on the NSC web site. Refer to the figures for total noise performance over temperature and supply at 3mA. Once the noise is modeled and circuit parameters chosen the evaluation board can be used to measure actual noise performance. To measure the CLC5509 input referred noise vs. other noise sources, several key steps should be followed. The DS101304-33 FIGURE 3. 9 www.national.com CLC5509 Application Information CLC5509 Application Information (Continued) The CLC5509 system dynamic range performance is enhanced by using the CLC5523 variable gain amplifier as a post amplifier. See Figure 4 below. The signal gain range is divided between the CLC5509 preamplifier and the post amplifier to allow wider dynamic range and better performance for high crest factor signals. There are two common ways the CLC5523 variable gain could be controlled. The first, Figure 5, uses a DAC to digitally increase the gain in discrete steps. The second Figure 6 uses an AGC loop to maintain the maximum system input signal-to-noise. Refer to the CLC5523 data sheet applications for the implementation details. DS101304-36 FIGURE 4. Low Noise Pre Amp with Variable Gain Amplifier Circuit DS101304-34 FIGURE 5. VG Controlled by DAC in Discrete Steps DS101304-35 FIGURE 6. VG Controlled by AGC Loop www.national.com 10 CLC5509 Ultra-Low Noise Preamplifier Physical Dimensions inches (millimeters) unless otherwise noted 8-pin SOIC Order Number CLC5509CM NS Product Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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