TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com COMPLETE PROTECTION SOLUTION FOR USB CHARGER PORT INCLUDING ESD PROTECTION FOR ALL LINES AND OVER-VOLTAGE PROTECTION ON VBUS Check for Samples: TPD4S014 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • Input Voltage Protection at VBUS up to 28V Low Ron nFET Switch Supports >2A charging current Over Voltage and Under Voltage Lock Out Features Low Capacitance TVS ESD Clamp for USB2.0 High speed Data Rate Internal 16ms Startup Delay Integrated Input Enable and Status Output Signal Thermal Shutdown Feature ESD Performance D+/D–/ID/VBUS Pins – ±15-kV Contact Discharge (IEC 61000-4-2) – ±15-kV Air Gap Discharge (IEC 61000-4-2) Space Saving QFN Package (2mm×2mm) Cell Phones eBook Portable Media Players Digital Camera DSQ PACKAGE (TOP SIDE/SEE-THROUGH VIEW) VBUSOUT 1 10 VBUS VBUSOUT VBUS EN GND ACK ID D+ 5 6 D- DESCRIPTION The TPD4S014 is a single-chip solution for USB charger port protection. This device offers low capacitance TVS type ESD clamps for the D+, D- and standard Capacitance for the ID pin. On the VBUS pin, this device can handle over-voltage protection up to 28V. The over voltage lock-out feature ensures that if there is a fault condition at the VBUS line, the TPD4S014 is able to isolate the VBUS line and protects the internal circuitry from damage. Similarly, the under voltage lock out feature ensures that there is no power drain from the internal VCC plane to external VBUS side in case there is short to GND. There is a 16ms turn-on delay after VBUS crosses the under voltage lockout threshold, in order to let the voltage stabilize before closing the switch. This function acts as a deglitch and prevents unnecessary switching if there is any ringing on the line during connection. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CIRCUIT SCHEMATIC DIAGRAM VBUS VBUSOUT Internal Band Gap Reference Control Logic + Charge Pump OVLO ACK UVLO EN GND D+ D- ID DEVICE OPERATION OTP UVLO OVLO EN SW ACK X X H X X OFF H X H X OFF L H L L H OFF L L L L L ON L H X X X OFF H OTP = Over temperature protection circuit active UVLO = Under voltage lock-out circuit active OVLO = Over voltage lock-out circuit active SW = Load switch CP = Charge pump X = Don’t Care H = True L = False 2 Copyright © 2011, Texas Instruments Incorporated TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com PIN FUNCTIONS PIN NAME NO. TYPE DESCRIPTION D– 6 I/O USB data– D+ 7 I/O USB data+ ID 5 I/O USB ID signal ACK 4 O Open-Drain Adapter-Voltage Indicator Output. ACOK is driven low after the VIN voltage is stable between UVLO and OVLO for 16ms (typ). Connect a pullup resistor from ACOK to the logic I/O voltage of the host system. Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the switch. EN 3 I VBUS 9, 10 USB Input Power VBUS_O UT 1, 2 GND Central PAD USB connector VBUS Power Output Connect to PCB internal PCB plane 8 Ground Central PAD Heat Sink Connect to PCB ground plane Electrically disconnected. Use as heat sink. Connect to GND plane via large PCB PAD ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VALUE MIN –0.5 Max Voltage on VBUS MAX UNIT 30 V Continuous current through NFET 2.6 A Max Current through D+, D-, ID, VBUS ESD clamps -50 mA mA Continuous current through logic output –50 50 Maximum junction temperature –40 150 °C IEC 61000-4-2 Contact Discharge D+, D–, ID, VBUS pins ±15 kV IEC 61000-4-2 Air-gap Discharge D+, D–, ID, VBUS pins ±15 kV Human-Body Model EN, ACK, VBUSOUT pins ±2 kV (1) (2) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. THERMAL INFORMATION THERMAL METRIC (1) TPD4S014 DSQ (10) PINS θJA Junction-to-ambient thermal resistance 70.3 θJCtop Junction-to-case (top) thermal resistance 46.3 θJB Junction-to-board thermal resistance 33.8 ψJT Junction-to-top characterization parameter 2.9 ψJB Junction-to-board characterization parameter 33.5 θJCbot Junction-to-case (bottom) thermal resistance 16.3 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2011, Texas Instruments Incorporated 3 TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS, EN, ACK, D+, D–, ID Pins over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage EN Load current = 50 µA VIL Low-level input voltage EN Load current = 50 µA 0.5 V IL Input Leakage Current EN, D+, D–, ID VI = 3.3 V 1.0 µA VOL Low-level output voltage ACK IOL = 2 mA 0.1 V VD Diode forward Voltage D+, D–, ID pins; lower clamp diode IO = 8 mA ΔCIO Differential Capacitance between the D+, D– lines CIO 1 V 0.95 V 0.03 pF Capacitance to GND for the D+, D– lines 1.6 pF CIO-ID Capacitance to GND for the ID line 19 pF VRS Reverse stand-off voltage of D+, D- and ID pins 5 V VBR Breakdown voltage D+, D–, ID pins Ibr = 1 mA 6 VBR VBUS Breakdown voltage on Vbus Ibr = 1 mA 28 RDYN Dynamic on resistance D+, D–, ID clamps II = 1 Amps V V Ω 1 ELECTRICAL CHARACTERISTICS OVP CIRCUITS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT UNDERVOLTAGE LOCKOUT VUVLO+ Under-voltage lock-out, input power detected threshold rising VBUS increasing from 0V to 5V, No load on OUT pin 2.65 2.8 3 V VUVLO– Under-voltage lock-out, input power detected threshold falling VBUS decreasing from 5V to 0V, No load on OUT pin 2.25 2.44 2.7 V VHYS-UVLO Hysteresis on UVLO Δ of VUVLO+ and VUVLO– 150 360 550 mV 151 200 mΩ 17.4 18 ms 8 µs INPUT TO OUTPUT CHARACTERISTICS RDS- VBUS switch resistance VBUS = 5 V, IOUT = 500 mA tON Turn-ON time RL = 36 Ω, CL = 10 uF tOFF Turn-OFF time RL = 36 Ω, CL = 10 uF VBUSSWITCH 16 INPUT OVERVOLTAGE PROTECTION (OVP) VOVP+ Input overvoltage protection threshold VBUS VBUS increasing from 5 V to 7 V, No Load 5.55 6.15 6.45 V VOVP- Input overvoltage protection threshold falling VBUS VBUS decreasing from 7V to 5V, No Load 5.75 5.98 6.24 V VHYS-OVP Hysteresis on OVP VBUS VBUS decreasing from 7 V to 5 V, No Load 25 100 275 mV td(OVP) Max Overvoltage delay 11 µs tREC Recovery time from input overvoltage condition 9 ms VBUS Time measured from VBUS 8 V ≥ 6 V, 1-µs fall-time 8 SUPPLY CURRENT CONSUMPTION over operating free-air temperature range (unless otherwise noted) TYP MAX UNIT IVBUS VBUS Operating Current Consumption PARAMETER No load on VBUS_OUT pin, VBUS = 5 V, EN = 0 V TEST CONDITIONS 147.6 160 µA IVBUS_OFF VBUS Operating Current Consumption No load on VBUS_OUT pin, VBUS = 5 V, EN = 5 V 111.8 120 µA THERMAL SHUTDOWN FEATURE TSHDN Thermal Shutdown TSHDN-HYS Thermal-Shutdown Hysteresis 4 144 °C 23 °C Copyright © 2011, Texas Instruments Incorporated TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com GENERAL OPERATION The TPD4S014 provides a single-chip protection solution for USB charger interfaces. The VBUS line is tolerant upto 28 V. A Low RDS(on) nFET switch is used to disconnect the downstream circuits in case of a fault condition. At power-up, when the voltage on VBUS is rising, the switch will close 16 ms after the input crosses the undervoltage threshold, thereby making power available to the downstream circuits. The TPD4S014 also has an ACK output, which deasserts to alert the system that a fault has occurred. The TPD4S014 offers 4 channel ESD clamps for D+, D-, ID, and VBUS pins that provide IEC61000-4-2 level 4 ESD protection. This eliminates the need for external TVS clamp circuits in the application. The TPD4S014 has an internal oscillator and charge pump that controls the turn-on of the internal nFET switch. The internal oscillator controls the timers that enable the turn-on of the charge pump and sets the state of the open-drain ACK output. If VBUS < VUVLO or if VBUS > VOVLO, the internal oscillator remains off, thus disabling the charge pump. The charge-pump at startup, after a 16ms internal delay, turns on the internal nFET switch and asserts ACK. At any time, if VBUS drops below VUVLO or rises above VOVLO, ACK is released and the nFET switch is disabled. When the input voltage rises above VOVP, or drops below the VUVLO, the internal VBUS switch is turned off, removing power to the application. The ACK signal is asserted when a fault condition is detected. If the fault was an over voltage event, the VBUS FET switch turns on 8ms after input voltage returns below VOVP – VHYS-OVP and remains above VUVLO. If the fault was an under voltage event, the switch turns on 16ms after the voltage returns above VUVLO+ (similar to start up). When the switch turns on, the ACK is asserted once again. A 16ms deglitch time has been introduced in to the turn on sequence to ensure that the input supply has stabilized before turning the switch ON. Noise on the Vbus line, could turn on the switch when the fault condition is still active. To avoid this, OVP glitch immunity allows noise on the VBUS line to be rejected. Such a glitch protection circuitry is also introduced in the turn off sequence in order to prevent the switch from turning off for voltage transients. The glitch protection circuitry integrates the glitch over time, allowing the OVP circuitry to trigger faster for larger voltage excursions above the OVP threshold and slower for shorter excursions. The protection circuitry has a maximum delay of 8 µs. When the device is ON, current flowing through the device will cause the device to heat up. Over heating can lead to permanent damage to the device. To prevent this, an over temperature protection has been designed into the device. Whenever the junction temperature exceeds 145 °C, the switch will turn off, thereby limiting the temperature. The ACK signal will be asserted for an over temperature event. Once the device cools down to below 120 °C the ACK signal will be deasserted, and the switch will turn on if the EN is active and the VBUS voltage is within the UVLO and OVP thresholds. While the over temperature protection in the device will not kick-in unless the die temperature reaches 145 °C, It is generally recommended that care is taken to keep the junction temperature below 125 °C. Operation of the device above 125 °C for extended periods of time can affect the long-term reliability of the part. The junction temperature of the device can be calculated using below formula: Tj = Ta + PD qJA Tj = Junction temperature Ta = Ambient temperature θJA = Thermal resistance PD = Power Dissipated in device PD = I2Ron I = Current through device RON = Max on resistance of device Copyright © 2011, Texas Instruments Incorporated (1) (2) 5 TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Example At 2A continuous current power dissipation is given by: PD = 22 ´ 0.2 = 0.8W If the ambient temperature is about 60oC the junction temperature will be: Tj = 60 + (0.8 ´ 70.3 ) = 116.24 This Implies that, at an ambient temperature of 60° Celcuis that TPD4S014 can pass a continuous of 2A with no problem. Conversely, the above calculation can also be used to calculate the total continuous current the TPD4S014 can handle at any given temperature. APPLICATION DIAGRAM 1.8 V - 3.3 V (from System VBUSOUT) 10KΩ TPD4S014 VBUSOUT VBUS 10 µF D+ USB Port Vbus D- To Processor ACK EN Battery Charger From Processor 10 µF ID D+ USB Transceiver DID Figure 1. tandard Implementation for Non-OTG USB System 1.8 V - 3.3 V (from System VBUSOUT) To OTG power supply (5 V) 10kΩ Current Limit Switch To Processor ACK EN VBUSOUT TPD4S014 VBUS 10 µF USB Port Vbus D+ D- Battery Charger From Processor 10 µF D+ D- ID USB Transceiver ID It is recommended the CVBUS >= CVBUS_OUT. This is necessary to ensure that the VBUS voltage doesn’t drop below the UVLO threshold when the device turns on at start up. Figure 2. Implementation for System With OTG System Support 6 Copyright © 2011, Texas Instruments Incorporated TPD4S014 www.ti.com SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS Figure 3. IEC61000-4-2 -8kV Contact Waveform Figure 4. IEC61000-4-2 +8kV Contact Waveform Figure 5. Capacitance Variation With Voltage Figure 6. Variation of On Resistance with Ambient Temperature Figure 7. Max Pulse Current Through Switch vs Pulse Duration Figure 8. UVLO Threshold Variation With Temperature Copyright © 2011, Texas Instruments Incorporated 7 TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Figure 9. OVP Threshold Variation With Temperature Figure 10. Start Up Inrush Current Characteristics Figure 11. Device Turn on Characteristics Figure 12. Device Turn OFF Characteristics (Undervoltage) Figure 13. Device Turn OFF Characteristics (Overvoltage) 8 Copyright © 2011, Texas Instruments Incorporated TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Figure 14. Eye Diagram With No EVM And No IC, Full USB2.0 Speed At 480Mbps Figure 15. Eye Diagram With EVM, No IC, Full USB2.0 Speed At 480Mbps Figure 16. Eye Diagram With EVM and IC, Full USB2.0 Speed At 480Mbps Copyright © 2011, Texas Instruments Incorporated 9 TPD4S014 SLVSAU0B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Revision A (June 2011) to Revision B Page • Changed name of VCC to VBUSOUT throughout the entire document. .................................................................................. 2 • Deleted row from Device Operation table. ............................................................................................................................ 2 • Added additional application diagram. .................................................................................................................................. 6 • Added Eye Diagrams to Typical Characteristics section. ..................................................................................................... 8 10 Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 PACKAGING INFORMATION Orderable Device TPD4S014DSQR Status (1) ACTIVE Package Type Package Drawing SON DSQ Pins Package Qty 10 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD4S014DSQR Package Package Pins Type Drawing SON DSQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 179.0 8.4 Pack Materials-Page 1 2.2 B0 (mm) K0 (mm) P1 (mm) 2.2 1.2 4.0 W Pin1 (mm) Quadrant 8.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD4S014DSQR SON DSQ 10 3000 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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