NSC MF10AJ

MF10
Universal Monolithic Dual
Switched Capacitor Filter
General Description
The MF10 consists of 2 independent and extremely easy to
use, general purpose CMOS active filter building blocks.
Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building
block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and
bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both
clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10; higher than 4th order
functions can be obtained by cascading MF10 packages.
Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed.
For pin-compatible device with improved performance refer
to LMF100 datasheet.
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Easy to use
Clock to center frequency ratio accuracy g 0.6%
Filter cutoff frequency stability directly dependent on
external clock quality
Low sensitivity to external component variation
Separate highpass (or notch or allpass), bandpass, lowpass outputs
fO c Q range up to 200 kHz
Operation up to 30 kHz
20-pin 0.3× wide Dual-In-Line package
20-pin Surface Mount (SO) wide-body package
System Block Diagram
Connection Diagram
Surface Mount and Dual-In-Line
Package
TL/H/10399 – 4
Top View
Order Number MF10AJ or MF10CCJ
See NS Package Number J20A
Order Number MF10ACWM or
MF10CCWM
See NS Package Number M20B
TL/H/10399 – 1
C1995 National Semiconductor Corporation
TL/H/10399
Order Number MF10ACN or
MF10CCN
See NS Package Number N20A
RRD-B30M115/Printed in U. S. A.
MF10 Universal Monolithic Dual Switched Capacitor Filter
December 1994
Absolute Maximum Ratings (Note 1)
Soldering Information
N Package: 10 sec.
J Package: 10 sec.
SO Package: Vapor Phase (60 Sec.)
Infrared (15 Sec.)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V a b Vb)
260§ C
300§ C
215§ C
220§ C
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ (Appendix D) for other methods of
soldering surface mount devices.
14V
Voltage at Any Pin
V a a 0.3V
Vb b 0.3V
Input Current at Any Pin (Note 2)
Package Input Current (Note 2)
Power Dissipation (Note 3)
Storage Temperature
ESD Susceptability (Note 11)
5 mA
20 mA
500 mW
150§ C
2000V
Operating Ratings (Note 1)
TMIN s TA s TMAX
0§ C s TA s 70§ C
0§ C s TA s 70§ C
Temperature Range
MF10ACN, MF10CCN
MF10CCWM, MF10ACWM
MF10CCJ
MF10AJ
b 40§ C s TA s 85§ C
b 55§ C s TA s 125§ C
Electrical Characteristics V a e a 5.00V and Vb e b5.00V unless otherwise specified. Boldface limits
apply for TMIN to TMAX; all other limits TA e TJ e 25§ C.
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Symbol
Parameter
V a b Vb Supply Voltage
Conditions
Min
9
9
V
Max
14
14
V
IS
Maximum Supply
Current
Clock Applied to Pins 10 & 11
No Input Signal
fO
Center Frequency Min
Range
Max
fO c Q k 200 kHz
fCLK
fCLK/fO
fCLK/fO
Clock Frequency
Range
12
8
0.2
0.1
12
0.2
mA
Hz
30
20
30
20
kHz
5.0
10
5.0
10
Hz
1.5
1.0
1.5
1.0
MHz
50:1 Clock to
MF10A Q e 10
Center Frequency MF10C Mode 1
Ratio Deviation
g 0.2
Vpin12 e 5V
fCLK e 250 kHz
g 0.2
g 0.6
g 0.6
g 0.2
g 1.0
%
g 1.5
g 1.5
g 0.2
g 1.5
%
100:1 Clock to
MF10A Q e 10
Center Frequency MF10C Mode 1
Ratio Deviation
g 0.2
Vpin12 e 0V
fCLK e 500 kHz
g 0.2
g 0.6
g 0.6
g 0.2
g 1.0
%
g 1.5
g 1.5
g 0.2
g 1.5
%
Clock Feedthrough
Q e 10
Mode 1
Q Error (MAX)
(Note 4)
Q e 10
Mode 1
10
Vpin12 e 5V
fCLK e 250 kHz
g2
Vpin12 e 0V
fCLK e 500 kHz
g2
0
VOS1
DC Offset Voltage (Note 5)
VOS2
DC Offset Voltage Min
(Note 5)
Max
Vpin12 e a 5V SA/B e V a
(fCLK/fO e 50)
Min
Mode 1 R1 e R2 e 10k
Vpin12 e a 5V SA/B e Vb
(fCLK/fO e 50)
Max
VOS3
8
Min
DC Lowpass Gain
VOS2
12
0.1
Max
HOLP
VOS3
MF10CCJ, MF10AJ
Tested Design
Tested Design Units
Typical
Typical
Limit
Limit
Limit
Limit
(Note 8)
(Note 8)
(Note 9) (Note 10)
(Note 9) (Note 10)
DC Offset Voltage Min
(Note 5)
Max
Vpin12 e a 5V All Modes
(fCLK/fO e 50)
DC Offset Voltage
(Note 5)
Vpin12 e 0V
SA/B e V a
(fCLK/fO e 100)
(Note 5)
Vpin12 e 0V
(fCLK/fO e 100)
DC Offset Voltage
(Note 5)
Vpin12 e 0V
All Modes
(fCLK/fO e 100)
2
g6
mV
g6
g2
g 10
g6
g6
g2
g 10
%
g 0.2
g 0.2
0
g 0.2
dB
mV
g 5.0
g 20
g 20
g 5.0
g 20
b 150
b 185
b 185
b 150
b 185
b 85
b 85
b 70
b 70
SA/B e Vb
10
b 100
b 20
b 20
mV
b 85
b 70
b 100
%
b 70
mV
b 100
mV
b 20
b 300
b 300
mV
b 140
b 140
mV
b 140
b 140
mV
Electrical Characteristics (Continued) V a e a 5.00V and Vb e b5.00V unless otherwise specified.
Boldface limits apply for TMIN to TMAX; all other limits TA e TJ e 25§ C.
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Symbol
VOUT
GBW
SR
Parameter
Minimum Output
Voltage Swing
BP, LP Pins
Typical
(Note 8)
RL e 5k
N/AP/HP Pin RL e 3.5k
Op Amp Gain BW Product
Op Amp Slew Rate
Dynamic Range
(Note 6)
ISC
Conditions
MF10CCJ, MF10AJ
Tested Design
Tested Design Units
Typical
Limit
Limit
Limit
Limit
(Note 8)
(Note 9) (Note 10)
(Note 9) (Note 10)
g 4.25
g 3.8
g 3.8
g 4.25
g 3.8
g 4.25
g 3.8
g 3.8
g 4.25
g 3.6
V
V
2.5
2.5
MHz
7
7
V/ms
Vpin12 e a 5V
(fCLK/fO e 50)
83
83
dB
Vpin12 e 0V
(fCLK/fO e 100)
80
80
dB
20
20
mA
3.0
3.0
mA
Maximum Output Short Source
Circuit Current (Note 7) Sink
Logic Input Characteristics Boldface limits apply for TMIN to TMAX; all other limits TA e TJ e 25§ C
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Parameter
Conditions
Typical
(Note 8)
CMOS Clock Min Logical ‘‘1’’ V a e a 5V, Vb e b5V,
Input Voltage Max Logical ‘‘0’’ VLSh e 0V
Min Logical ‘‘1’’
V a e a 10V, Vb e 0V,
e a 5V
V
Max Logical ‘‘0’’ LSh
TTL Clock
Min Logical ‘‘1’’ V a e a 5V, Vb e b5V,
Input Voltage Max Logical ‘‘0’’ VLSh e 0V
Min Logical ‘‘1’’
V a e a 10V, Vb e 0V,
V
Max Logical ‘‘0’’ LSh
MF10CCJ, MF10AJ
Tested
Design
Tested
Design Units
Typical
Limit
Limit
Limit
Limit
(Note 8)
(Note 9) (Note 10)
(Note 9) (Note 10)
a 3.0
a 3.0
a 3.0
V
b 3.0
b 3.0
b 3.0
V
a 8.0
a 8.0
a 8.0
V
a 2.0
a 2.0
a 2.0
V
a 2.0
a 2.0
a 2.0
V
a 0.8
a 0.8
a 0.8
V
a 2.0
a 2.0
a 2.0
V
a 0.8
a 0.8
a 0.8
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l V a ) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, iJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX e 125§ C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55§ C/W. For the MF10AJ/CCJ, this
number increases to 95§ C/W and for the MF10ACWM/CCWM this number is 66§ C/W.
Note 4: The accuracy of the Q value is a function of the center frequency (fO). This is illustrated in the curves under the heading ‘‘Typical Performance
Characteristics’’.
Note 5: VOS1, VOS2, and VOS3 refer to the internal offsets as discussed in the Applications Information Section 3.4.
Note 6: For g 5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for
the MF10 with a 50:1 CLK ratio and 280 mV rms for the MF10 with a 100:1 CLK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25§ C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.
3
Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
Positive Output Voltage Swing
vs Load Resistance
(N/AP/HP Output)
Negative Output Voltage
Swing vs Load
Resistance (N/AP/HP Output)
Negative Output
Swing vs Temperature
Positive Output Swing
vs Temperature
Crosstalk vs Clock
Frequency
Q Deviation vs
Temperature
Q Deviation vs
Temperature
Q Deviation vs
Clock Frequency
Q Deviation vs
Clock Frequency
fCLK/fO Deviation
vs Temperature
fCLK/fO Deviation
vs Temperature
TL/H/10399 – 2
4
Typical Performance Characteristics
fCLK/fO Deviation
vs Clock Frequency
(Continued)
fCLK/fO Deviation
vs Clock Frequency
fCLK
Deviation of
vs Nominal Q fO
fCLK
Deviation of
vs Nominal Q fO
TL/H/10399 – 3
Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandpass
N/AP/HP(3,18)
and notch/allpass/highpass outputs.
These outputs can typically sink 1.5 mA
and source 3 mA. Each output typically
swings to within 1V of each supply.
INV(4,17)
The inverting input of the summing opamp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making
INVA and INVB behave like summing
junctions (low impedance, current inputs).
S1(5,16)
S1 is a signal input pin used in the allpass filter configurations (see modes 4
and 5). The pin should be driven with a
source impedance of less than 1 kX. If
S1 is not driven with a signal it should be
tied to AGND (mid-supply).
SA/B(6)
This pin activates a switch that connects
one of the inputs of each filter’s second
summer to either AGND (SA/B tied to
Vb) or to the lowpass (LP) output (SA/B
tied to V a ). This offers the flexibility
needed for configuring the filter in its
various modes of operation.
VA a (7),VD a (8)
Analog positive supply and digital positive supply. These pins are internally
connected through the IC substrate and
therefore VA a and VD a should be derived from the same power supply
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and bypassed by a single capacitor.
VAb(14), VDb(13) Analog and digital negative supplies.
a
The same comments as for VA and
a
VD apply here.
5
Pin Descriptions (Continued)
1.0 Definition of Terms
LSh(9)
fCLK: the frequency of the external clock signal applied to
pin 10 or 11.
CLKA(10),
CLKB(11)
50/100/CL(12)
AGND(15)
Level shift pin; it accommodates various
clock levels with dual or single supply
operation. With dual g 5V supplies, the
MF10 can be driven with CMOS clock
levels ( g 5V) and the LSh pin should be
tied to the system ground. If the same
supplies as above are used but only TTL
clock levels, derived from 0V to a 5V
supply, are available, the LSh pin should
be tied to the system ground. For single
supply operation (0V and a 10V) the
VAb, VDb pins should be connected to
the system ground, the AGND pin
should be biased at a 5V and the LSh
pin should also be tied to the system
ground for TTL clock levels. LSh should
be biased at a 5V for CMOS clock levels in 10V single-supply applications.
Clock inputs for each switched capacitor filter building block. They should both
be of the same level (TTL or CMOS).
The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used.
This allows the maximum time for the
internal op-amps to settle, which yields
optimum filter operation.
By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained.
Tying this pin at mid-supplies (i.e, analog
ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied
low (i.e., negative supply with dual supplies), a simple current limiting circuit is
triggered to limit the overall supply current down to about 2.5 mA. The filtering
action is then aborted.
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of midsupply biasing techniques see the Applications Information (Section 3.2). For
optimum filter performance a ‘‘clean’’
ground must be provided.
fO: center frequency of the second order function complex
pole pair. fO is measured at the bandpass outputs of the
MF10, and is the frequency of maximum bandpass gain.
(Figure 1)
fnotch: the frequency of minimum (ideally zero) gain at the
notch outputs.
fz: the center frequency of the second order complex zero
pair, if any. If fz is different from fO and if QZ is high, it can be
observed as the frequency of a notch at the allpass output.
(Figure 10)
Q: ‘‘quality factor’’ of the 2nd order filter. Q is measured at
the bandpass outputs of the MF10 and is equal to fO divided
by the b3 dB bandwidth of the 2nd order bandpass filter
(Figure 1) . The value of Q determines the shape of the 2nd
order filter responses as shown in Figure 6 .
QZ: the quality factor of the second order complex zero pair,
if any. QZ is related to the allpass characteristic, which is
written:
#
HOAP s2 b
HAP(s) e
s0O
a 0O2
QZ
s0O
a 0O2
s2 a
Q
J
where QZ e Q for an all-pass response.
HOBP: the gain (in V/V) of the bandpass output at f e fO.
HOLP: the gain (in V/V) of the lowpass output as f x 0 Hz
(Figure 2) .
HOHP: the gain (in V/V) of the highpass output as f x
fCLK/2 (Figure 3) .
HON: the gain (in V/V) of the notch output as f x 0 Hz
and as f x fCLK/2, when the notch filter has equal gain
above and below the center frequency (Figure 4) . When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (Figures 11 and 8) , the two quantities
below are used in place of HON.
HON1: the gain (in V/V) of the notch output as f x 0 Hz.
HON2: the gain (in V/V) of the notch output as f x fCLK/2.
6
1.0 Definition of Terms (Continued)
HOBP
HBP(s) e
s2 a
Qe
TL/H/10399 – 6
fH e fO
(b)
(a)
S
Q
s0O
a 0O2
Q
fO
; f O e 0f Lf H
fH b fL
fL e fO
TL/H/10399–5
0O
# 2Q 0# 2Q J
2
#
2
b1
1
a
0# J
1
a
2Q
1
2Q
a1
J
a1
J
0 O e 2 q fO
FIGURE 1. 2nd-Order Bandpass Response
HOLP0O2
s0O
a 0O2
Q
HLP(s) e
s2 a
0#1
fC e fO c
fp e fO
a
b
1 2
a1
2Q2
J
0
TL/H/10399 – 8
(a)
J 0# 1
1
1b
2Q2
HOP e HOLP c
TL/H/10399–7
1
2Q2
b
(b)
1
1
Q
0
1b
1
4Q2
FIGURE 2. 2nd-Order Low-Pass Response
TL/H/10399 – 10
TL/H/10399 – 9
(b)
(a)
HHP(s) e
HOHPs2
s0O
a 0O2
Q
s2 a
fC e fO c
Ð0#1
b
fp e fO c
Ð01
b
1
2Q2
1
Q
0
HOP e HOHP c
1
2Q2
(
J 0# 1
a
b
1 2
a1
2Q2
J
(
b1
b1
1
1b
1
4Q2
FIGURE 3. 2nd-Order High-Pass Response
7
1.0 Definitions of Terms (Continued)
HON(s2 a 0O2)
s0O
a 0O2
Q
HN(s) e
s2 a
Qe
TL/H/10399–11
(a)
TL/H/10399 – 12
(b)
fO
; fO e 0fL fH
fH b fL
fL e fO
# 2Q 0# 2Q J
fH e fO
#
b1
1
a
2Q
2
a1
J
1 2
a1
2Q
J
1
a
0# J
FIGURE 4. 2nd-Order Notch Response
#
HOAP s2 b
HAP(s) e
s2 a
s0O
a 0O2
Q
s0O
a 0O2
Q
J
TL/H/10399 – 14
TL/H/10399–13
(b)
(a)
FIGURE 5. 2nd-Order All-Pass Response
(a) Bandpass
(b) Low Pass
(d) Notch
(c) High-Pass
(e) All-Pass
TL/H/10399 – 15
FIGURE 6. Response of various 2nd-order filters as a function of Q.
Gains and center frequencies are normalized to unity.
8
2.0 Modes of Operation
The MF10 is a switched capacitor (sampled data) filter. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF10 closely approximates continuous filters, the following
discussion is based on the well know frequency domain.
Each MF10 can produce a full 2nd order function. See Table I for a summary of the characteristics of the various
modes.
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
fnotch e fO (See Figure 7 )
e center frequency of the complex pole pair
fO
f
f
e CLK or CLK
100
50
fnotch e center frequency of the imaginary zero pair e fO.
R2
HOLP e Lowpass gain (as f x 0) e b
R1
R3
e
e
e
b
fO)
HOBP Bandpass gain (at f
R1
b R2
f
x
0
e
e
Notch output gain as f x f
HON
CLK/2
R1
fO
R3
e
BW
R2
e quality factor of the complex pole pair
BW e the b3 dB bandwidth of the bandpass output.
Circuit dynamics:
HOBP
or HOBP e HOLP c Q
HOLP e
Q
e HON c Q.
HOLP(peak) j Q c HOLP (for high Q’s)
Q
e
MODE 1a: Non-Inverting BP, LP (See Figure 8 )
f
f
e CLK or CLK
fO
100
50
R3
e
Q
R2
HOLP e b1; HOLP(peak) j Q c HOLP (for high Q’s)
R3
HOBP1e b
R2
HOBP2e 1 (Non-Inverting)
Circuit Dynamics: HOBP1 e Q
(
Note: VIN should be driven from a low impedance ( k 1 kX) source.
TL/H/10399 – 16
FIGURE 7. MODE 1
TL/H/10399 – 17
FIGURE 8. MODE 1a
9
2.0 Modes of Operation (Continued)
MODE 2: Notch 2, Bandpass, Lowpass: fnotch k fO
(See Figure 9 )
e center frequency
fO
f
f
R2
R2
e CLK
a 1 or CLK
a1
100 R4
50
R4
fCLK
fCLK
or
fnotch e
100
50
e quality factor of the complex pole pair
Q
0R2/R4 a 1
e
R2/R3
HOLP e Lowpass output gain (as f x 0)
R2/R1
e b
R2/R4 a 1
HOBP e Bandpass output gain (at f e fO) e bR3/R1
HON1 e Notch output gain (as f x 0)
R2/R1
e b
R2/R4 a 1
fCLK
e b R2/R1
HON2 e Notch output gain as f x
2
Filter dynamics: HOBP e Q 0HOLP HON2 e 0HON1 HON2
0
MODE 3: Highpass, Bandpass, Lowpass Outputs
(See Figure 10 )
fCLK
f
R2
R2
e CLK c
c
or
fO
100
R4
50
R4
e quality factor of the complex pole pair
Q
R2 R3
e
c
R4 R2
fCLK
R2
eb
HOHP e Highpass Gain as f x
2
R1
R3
e
e
e
b
fO
HOBP Lowpass Gain at f
R1
R4
HOLP e Lowpass Gain as f x 0 e b
R1
HOHP
R2
e
;
Circuit dynamics:
R4
HOLP
HOBP e 0HOHP c HOLP c Q
HOLP(peak) j Q c HOLP (for high Q’s)
HOHP(peak) j Q c HOHP (for high Q’s)
0
0
#
0
J
0
#
#
#
J
J
J
TL/H/10399 – 18
FIGURE 9. MODE 2
TL/H/10399 – 19
*In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a
problem, connect a small capacitor (10 pF b 100 pF) across R4 to provide some phase lead.
FIGURE 10. MODE 3
10
2.0 Modes of Operation (Continued)
MODE 4: Allpass, Bandpass, Lowpass Outputs
(See Figure 12 )
e center frequency
fO
f
f
e CLK or CLK;
100
50
fz* e center frequency of the complex zero & fO
f
R3
e O e
;
Q
BW
R2
R3
QZ e quality factor of complex zero pair e
R1
For AP output make R1 e R2
fCLK
R2
eb
e b1
HOAP* e Allpass gain at 0 k f k
2
R1
HOLP e Lowpass gain (as f x 0)
R2
eb
a 1 e b2
R1
MODE 3a: HP, BP, LP and Notch with External Op Amp
(See Figure 11 )
fCLK
f
R2
R2
e CLK c
c
or
fO
100
R4
50
R4
R2 R3
e
c
Q
R4 R2
R2
HOHP e b
R1
R3
HOBP e b
R1
R4
HOLP e b
R1
fCLK Rh
f
Rh
e notch frequency e CLK
or
fn
100
RI
50
RI
HON e gain of notch at
Rg
Rg
HOLP b
HOHP
f e fO e Q
RI
Rh
Rg
c HOLP
Hn1 e gain of notch (as f x 0) e
RI
0
0
0
0
ÀÀ #
Hn2
e gain of notch
# as f x
R
e b g c HOHP
Rh
#
0
#
JÀÀ
fCLK
2
J
J
HOBP e Bandpass gain (at f e fO)
R3
R2
R3
eb
eb2
1a
R2
R1
R2
Circuit Dynamics: HOBP e (HOLP) c Q e (HOAP a 1)Q
#
J
J
# J
*Due to the sampled data nature of the filter, a slight mismatch of fz and fO
occurs causing a 0.4 dB peaking around fO of the allpass filter amplitude
response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended.
TL/H/10399 – 20
FIGURE 11. MODE 3a
TL/H/10399 – 21
FIGURE 12. MODE 4
11
2.0 Modes of Operation (Continued)
MODE 6a: Single Pole, HP, LP Filter (See Figure 14 )
MODE 5: Numerator Complex Zeros, BP, LP
(See Figure 13 )
fO
e
0
01
1a
0
f
or
100
01
R2 fCLK
c
or
R4
100
R2
b
c CLK
R4
fz
e
Q
e 01 a R2/R4 c
R3
R2
QZ
e 01 b R1/R4 c
R3
R1
H0z1
e gain at C.Z. output (as f
b R2(R4 b R1)
R1(R2 a R4)
H0z2
e gain at C.Z. output
HOBP e b
#
J
R2
R1
# R2 R4 J
R2
a1
R1
a
R2 fCLK
c
R4
50
c
e cutoff frequency of LP or HP output
e R2 fCLK
R2 fCLK
R3 100
R1 fCLK
b
c
R4
50
or
R3 50
R3
HOLP e b
R1
HOHP e b
R2
R1
MODE 6b: Single Pole LP Filter (Inverting and Non-Inverting) (See Figure 15 )
x 0 Hz)
fc
e cutoff frequency of LP outputs
j
# as f x 2 J
fCLK
e
b R2
R1
R2 fCLK
R2 fCLK
or
R3 100
R3 50
HOLP1 e 1 (non-inverting)
R3
c
R2
a
HOLP e b
1a
fc
HOLP2 e b
R3
R2
R4
R1
TL/H/10399 – 22
FIGURE 13. MODE 5
TL/H/10399 – 23
FIGURE 14. MODE 6a
TL/H/10399 – 24
FIGURE 15. MODE 6b
12
2.0 Modes of Operation (Continued)
TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios.
Mode
BP
LP
1
*
*
1a
(2)
HOBP1 e bQ
HOBP2 e a 1
HOLP a 1
2
*
*
3
*
*
*
3a
*
*
*
4
*
*
5
*
*
6a
*
HP
N
Number of
Resistors
Adjustable
fCLK/fO
3
No
2
No
3
Yes (above fCLK/50
or fCLK/100)
4
Yes
Universal State-Variable
Filter. Best general-purpose mode.
7
Yes
As above, but also includes
resistor-tuneable notch.
*
3
No
Gives Allpass response with
HOAP e b1 and HOLP e b2.
*
4
Gives flatter allpass response
than above if R1 e R2 e 0.02R4.
3
Single pole.
2
Single Pole.
AP
*
*
*
*
Notes
May need input buffer.
Poor dynamics for
high Q.
(2)
6b
HOLP1 e a 1
b R3
R2
HOLP2 e
3.0 Applications Information
filter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
f0A e 529 Hz
QA e 0.785
The MF10 is a general-purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(fCLK). By connecting pin 12 to the appropriate DC voltage,
the filter center frequency fO can be made equal to either
fCLK/100 or fCLK/50. fO can be very accurately set (within
g 6%) by using a crystal clock oscillator, or can be easily
varied over a wide frequency range by adjusting the clock
frequency. If desired, the fCLK/fO ratio can be altered by
external resistors as in Figures 9, 10, 11, 13, 14 and 15 . The
filter Q and gain are determined by external resistors.
All of the five second-order filter types can be built using
either section of the MF10. These are illustrated in Figures 1
through 5 along with their transfer functions and some related equations. Figure 6 shows the effect of Q on the shapes
of these curves. When filter orders greater than two are
desired, two or more MF10 sections can be cascaded.
QB e 3.559
f0B e 993 Hz
For unity gain at DC, we also specify:
H0A e 1
H0B e 1
The desired clock-to-cutoff-frequency ratio for the overall
filter of this example is 100 and a 100 kHz clock signal is
available. Note that the required center frequencies for the
two second-order sections will not be obtainable with clockto-center-frequency ratios of 50 or 100. It will be necessary
fCLK
to adjust
externally. From Table I, we see that Mode 3
f0
can be used to produce a low-pass filter with resistor-adjustable center frequency.
In most filter designs involving multiple second-order
stages, it is best to place the stages with lower Q values
ahead of stages with higher Q, especially when the higher Q
is greater than 0.707. This is due to the higher relative gain
at the center frequency of a higher-Q stage. Placing a stage
with lower Q ahead of a higher-Q stage will provide some
attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage
A has the lower Q (0.785) so it will be placed ahead of the
other stage.
For the first section, we begin the design by choosing a
convenient value for the input resistance: R1A e 20k. The
absolute value of the passband gain HOLPA is made equal
3.1 DESIGN EXAMPLE
In order to design a second-order filter section using the
MF10, we must define the necessary values of three parameters: f0, the filter section’s center frequency; H0, the passband gain; and the filter’s Q. These are determined by the
characteristics required of the filter being designed.
As an example, let’s assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at DC, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections of an MF10. Many filter design texts include tables that
list the characteristics (fO and Q) of each of the second-order filter sections needed to synthesize a given higher-order
13
3.0 Applications Information (Continued)
to 1 by choosing R4A such that: R4A e bHOLPA R1A e
R1A e 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we
find R2A by:
R2A e R4A
The resistors for the second section are found in a similar
fashion:
R1B e 20k
R4B e R1B e 20k
(993)2
f0B2
e 20k
e 19.7k
R2B e R4B
(fCLK/100)2
(1000)2
f0A2
(529)2
e 2 c 104 c
e 5.6k and
(fCLK/100)2
(1000)2
R3A e QA 0R2AR4A e 0.785 05.6 c 103 c 2 c 104 e 8.3k
R3B e QB 0R2BR4B e 3.55901.97 c 104 c 2 c 104 e 70.6k
The complete circuit is shown in Figure 16 for split g 5V
power supplies. Supply bypass capacitors are highly recommended.
TL/H/10399 – 25
FIGURE 16. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1.
g 5V Power Supply. 0V–5V TTL or b 5V g 5V CMOS Logic Levels.
TL/H/10399 – 26
FIGURE 17. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1.
Single a 10V Power Supply. 0V – 5V TTL Logic Levels. Input Signals
Should be Referred to Half-Supply or Applied through a Coupling Capacitor.
14
3.0 Applications Information (Continued)
TL/H/10399 – 28
TL/H/10399–27
(a) Resistive Divider with
Decoupling Capacitor
(b) Voltage Regulator
TL/H/10399 – 29
(c) Operational Amplifier
with Divider
FIGURE 18. Three Ways of Generating
Va
for Single-Supply Operation
2
10 will have a 20 dB peak in its amplitude response at fO. If
the nominal gain of the filter HOLP is equal to 1, the gain at
fO will be 10. The maximum input signal at fO must therefore
be less than 800 mVp– p when the circuit is operated on
g 5V supplies.
Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 7) . The notch
output will be very small at fO, so it might appear safe to
apply a large signal to the input. However, the bandpass will
have its maximum gain at fO and can clip if overdriven. If
one output clips, the performance at the other outputs will
be degraded, so avoid overdriving any filter section, even
ones whose outputs are not being directly used. Accompanying Figures 7 through 15 are equations labeled ‘‘circuit
dynamics’’, which relate the Q and the gains at the various
outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given application.
3.2 SINGLE SUPPLY OPERATION
The MF10 can also operate with a single-ended power supply. Figure 17 shows the example filter with a single-ended
power supply. VA a and VD a are again connected to the
positive power supply (8V to 14V), and VAb and VDb are
connected to ground. The AGND pin must be tied to V a /2
for single supply operation. This half-supply point should be
very ‘‘clean’’, as any noise appearing on it will be treated as
an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure
18a) , or a low-impedance half-supply voltage can be made
using a three-terminal voltage regulator or an operational
amplifier (Figures 18b and 18c) . The passive resistor divider
with a bypass capacitor is sufficient for many applications,
provided that the time constant is long enough to reject any
power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency,
so at very low clock frequencies the regulator or op-amp
approaches may be preferable because they will require
smaller capacitors to filter the clock frequency. The main
power supply voltage should be clean (preferably regulated)
and bypassed with 0.1 mF.
3.4 OFFSET VOLTAGE
The MF10’s switched capacitor integrators have a higher
equivalent input offset voltage than would be found in a
typical continuous-time active filter integrator. Figure 19
shows an equivalent circuit of the MF10 from which the output DC offsets can be calculated. Typical values for these
offsets with SA/B tied to V a are:
Vos1 e opamp offset e g 5 mV
b 300 mV @ 100:1
Vos2 e b150 mV @ 50:1
b 140 mV @ 100:1
Vos3 e b70 mV @ 50:1
When SA/B is tied to Vb, Vos2 will approximately halve. The
DC offset at the BP output is equal to the input offset of the
lowpass integrator (Vos3). The offsets at the other outputs
depend on the mode of operation and the resistor ratios, as
described in the following expressions.
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF10, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF10 are able to swing to
within about 1V of the supplies, so the input signals must be
kept small enough that none of the outputs will exceed
these limits. If the MF10 is operating on g 5V, for example,
the outputs will clip at about 8 Vp – p. The maximum input
voltage multiplied by the filter gain should therefore be less
than 8 Vp – p.
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (Figure 6) . As an example, a lowpass filter with a Q of
15
3.0 Applications Information (Continued)
Mode 1 and Mode 4
VOS(N)
VOS(BP)
VOS(LP)
e VOS1
ÀÀ
ÀÀJ
Mode 2 and Mode 5
V
b OS3
Q
VOS(N)
e VOS3
e VOS(N) b VOS2
Mode 1a
VOS(N.INV.BP) e
VOS(INV.BP)
VOS(LP)
#
1
a 1 HOLP
Q
#1 QJ V
a
1
OS1 b
e
#R
R2
a1
p
a VOS2
JV
OS1 c
1
1 a R2/R4
1
VOS3
b
:
1 a R4/R2 Q01 a R2/R4
Rp e R1//R3//R4
VOS(BP) e VOS3
VOS(LP) e VOS(N) b VOS2
VOS3
Q
e VOS3
Mode 3
VOS(HP) e VOS2
VOS(BP) e VOS3
R4
b VOS2
VOS(LP) e VOS1 1 a
Rp
e VOS(N.INV.BP) b VOS2
Ð
b VOS3
(
# R2 J
R4
# R3 J
R4
Rp e R1//R2//R3
TL/H/10399 – 30
FIGURE 19. MF10 Offset Voltage Sources
TL/H/10399 – 31
FIGURE 20. Method for Trimming VOS
16
3.0 Applications Information (Continued)
was fs/2 b 100 Hz. This phenomenon is known as ‘‘aliasing’’, and can be reduced or eliminated by limiting the input
signal spectrum to less than fs/2. This may in some cases
require the use of a bandwidth-limiting filter ahead of the
MF10 to limit the input spectrum. However, since the clock
frequency is much higher than the center frequency, this will
often not be necessary.
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling period, resulting in ‘‘steps’’ in the output voltage which occur at
the clock rate (Figure 21) . If necessary, these can be
‘‘smoothed’’ with a simple R – C low-pass filter at the MF10
output.
The ratio of fCLK to fC (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however,
a ratio of 50:1 may be better as it will result in 3 dB lower
output noise. The 50:1 ratio also results in lower DC offset
voltages, as discussed in Section 3.4.
The accuracy of the fCLK/fO ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
‘‘Typical Performance Characteristics’’. As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in fCLK/fO will be small. If the error is too large
for a specific application, use a mode that allows adjustment
of the ratio with external resistors.
It should also be noted that the product of Q and fO should
be limited to 300 kHz when fO k 5 kHz, and to 200 kHz for
fO l 5 kHz.
For most applications, the outputs are AC coupled and DC
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower AC signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fO and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
fCLK/fO significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass
filter having unity gain, a Q of 20, and fCLK/fO e 250 with
pin 12 tied to ground (100:1 nominal). R4/R2 will therefore
be equal to 6.25 and the offset voltage at the lowpass output will be about a 1V. Where necessary , the offset voltage
can be adjusted by using the circuit of Figure 20 . This allows
adjustment of VOS1, which will have varying effects on the
different outputs as described in the above equations. Some
outputs cannot be adjusted this way in some modes, however (VOS(BP) in modes 1a and 3, for example).
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The MF10 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MF10’s sampling frequency is the
same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be ‘‘reflected’’ to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is fs/2 a 100 Hz will
cause the system to respond as though the input frequency
TL/H/10399 – 32
FIGURE 21. The Sampled-Data Output Waveform
17
18
Physical Dimensions inches (millimeters)
20-Lead Ceramic Dual-In-Line Package (J)
Order Number MF10AJ or MF10CCJ
NS Package Number J20A
Molded Package (Small Outline) (M)
Order Number MF10ACWM or MF10CCWM
NS Package Number M20B
19
MF10 Universal Monolithic Dual Switched Capacitor Filter
Physical Dimensions inches (millimeters) (Continued)
20-Lead Molded Dual-In-Line Package (N)
Order Number MF10ACN or MF10CCN
NS Package Number N20A
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