DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on National's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs of the DS15BR400 are internally terminated with 100Ω resistors to improve performance and minimize board space. The DS15BR401 does not have input termination resistors. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes. The DS15BR400/DS15BR401 are powered from a single 3.3V supply and consume 578 mW (typ). They operate over the full -40°C to +85°C industrial temperature range and are available in space saving LLP-32 and TQFP-48 packages. ■ DC to 2 Gbps low jitter, high noise immunity, low power operation ■ 6 dB of pre-emphasis drives lossy backplanes and cables ■ LVDS/CML/LVPECL compatible input, LVDS output ■ On-chip 100 Ω output termination, optional 100 Ω input ■ ■ ■ ■ ■ termination 15 kV ESD protection on LVDS inputs and outputs Single 3.3V supply Industrial -40 to +85°C temperature range Space saving LLP-32 or TQFP-48 packages Evaluation Kit Available Applications ■ Cable extention applications ■ Signal repeating and buffering ■ Digital routers Typical Application 20188950 © 2007 National Semiconductor Corporation 201889 www.national.com DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis May 2007 DS15BR400/DS15BR401 Block and Connection Diagrams 20188901 20188903 DS15BR400 Block Diagram DS15BR401 Block Diagram 20188912 20188902 LLP Pinout - Top View TQFP Pinout - Top View www.national.com 2 DS15BR400/DS15BR401 Pin Descriptions Pin Name TQFP Pin Number LLP Pin Number I/O, Type Description DIFFERENTIAL INPUTS IN0+ IN0− 13 14 9 10 I, LVDS Channel 0 inverting and non-inverting differential inputs. IN1+ IN1− 15 16 11 12 I, LVDS Channel 1 inverting and non-inverting differential inputs. IN2+ IN2− 19 20 13 14 I, LVDS Channel 2 inverting and non-inverting differential inputs. IN3+ IN3− 21 22 15 16 I, LVDS Channel 3 inverting and non-inverting differential inputs. DIFFERENTIAL OUTPUTS OUT0+ OUT0− 48 47 32 31 O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 2) OUT1+ OUT1− 46 45 30 29 O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 2) OUT2+ OUT2− 42 41 28 27 O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 2) OUT3+ OUT3- 40 39 26 25 O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 2) DIGITAL CONTROL INTERFACE PWDN 12 8 I, LVTTL A logic low at PWDN activates the hardware power down mode (all channels). PEM 2 2 I, LVTTL Pre-emphasis Control Input (affects all Channels) POWER VDD 3, 4, 5, 7, 10, 11, 3, 4, 6, 7, 20, 28, 29, 32, 33 21 I, Power VDD = 3.3V, ±10% GND 8, 9, 17, 18, 23, 24, 37, 38, 43, 44 I, Ground Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device in addition to the pin numbers listed. The DAP is the exposed metal contact at the bottom of the LLP-32 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. N/C 1,6, 25, 26, 27, 1, 17, 30, 31, 34, 35, 18,19,22, 23, 36 24 5 (Note 1) No Connect Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to the actual pin numbers listed. Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and DS15BR401 are optimized for point-to-point backplane and cable applications. 3 www.national.com DS15BR400/DS15BR401 LVDS pins to GND only Absolute Maximum Ratings (Note 3) Supply Voltage (VDD) CMOS Input Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Current Junction Temperature Storage Temperature Lead Temperature (Solder, 4sec) Max Pkg Power Capacity @ 25°C TQFP LLP −0.3V to +4.0V −0.3V to (VDD+0.3V) −0.3V to (VDD+0.3V) −0.3V to (VDD+0.3V) +40 mA +150°C −65°C to +150°C 260°C 250V 1000V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) (Note 4) Output Voltage (VO) Operating Temperature (TA) Industrial 1.64W 4.16W Thermal Resistance (θJA) TQFP LLP Package Derating above +25°C TQFP LLP ESD Last Passing Voltage HBM, 1.5kΩ, 100pF 15 kV EIAJ, 0Ω, 200pF Charged Device Model 3.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of products outside of recommended operation conditions. 76°C/W 30°C/W 13.2mW/°C 33.3mW/°C Note 4: VID max < 2.4V 8 kV Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 5) Max Units VDD V LVCMOS DC SPECIFICATIONS (PWDN, PEM) VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current VIN = VDD = 3.6V (PWDN pin) IIHR High Level Input Current VIN = VDD = 3.6V (PEM pin) IIL Low Level Input Current VIN = VSS, VDD = 3.6V CIN1 LVCMOS Input Capacitance Any Digital Input Pin to VSS VCL Input Clamp Voltage 2.0 ICL = −18 mA, VDD = 0V GND 0.8 V −10 +10 µA 40 200 µA −10 +10 µA −1.5 5.5 pF −0.8 V LVDS INPUT DC SPECIFICATIONS (INn±) VTH Differential Input High Threshold (Note 6) VCM = 0.8V to 3.55V, VDD = 3.6V VTL Differential Input Low Threshold (Note 6) VCM = 0.8V to 3.55V, VDD = 3.6V −100 VID Differential Input Voltage VCM = 0.8V to 3.55V, VDD = 3.6V 100 2400 mV VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.6V 0.05 3.55 V CIN2 LVDS Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.6V, VDD = 3.6V −10 +10 µA VIN = 0V, VDD = 3.6V −10 +10 µA www.national.com 0 100 0 mV 3.0 4 mV pF Parameter Conditions Min Typ (Note 5) Max Units 250 360 500 mV 35 mV 1.475 V 35 mV LVDS OUTPUT DC SPECIFICATIONS (OUTn±) RL = 100Ω external resistor between OUT+ and OUT− Figure 1 VOD Differential Output Voltage, 0% Pre-emphasis (Note 6) ΔVOD Change in VOD between Complementary States −35 VOS Offset Voltage (Note 7) 1.05 ΔVOS Change in VOS between Complementary States −35 COUT LVDS Output Capacitance OUT+ or OUT− to VSS 2.5 IOS Output Short Circuit Current OUT+ or OUT− Short to GND −21 −40 mA OUT+ or OUT− Short to VDD 6 40 mA 175 215 mA 20 200 µA 170 250 ps 170 250 ps 1.0 2.0 ns 1.0 2.0 ns 1.18 pF SUPPLY CURRENT (Static) ICC ICCZ Supply Current All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. PEM = L Supply Current - Power Down PWDN = L, PEM = L Mode SWITCHING CHARACTERISTICS—LVDS OUTPUTS tLHT Differential Low to High Transition Time (Note 12) tHLT Differential High to Low Transition Time (Note 12) tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew (Note 12) |tPLHD–tPHLD| 10 60 ps tSKCC Output Channel to Channel Skew (Note 12) Difference in propagation delay (tPLHD or tPHLD) among all output channels. 25 75 ps tSKP Part to Part Skew (Note 12) Common edge, parts at same temp and VCC 550 ps tJIT Jitter (0% Pre-emphasis) (Note 8) RJ - Alternating 1 and 0 at 750 MHz (Note 9) 0.5 1.5 ps DJ - K28.5 Pattern, 1.5 Gbps (Note 10) 14 30 ps TJ - PRBS 223-1 Pattern, 1.5 Gbps (Note 11) 14 31 ps Time from PWDN to OUT± change from TRI-STATE to active. Figures 5, 6 20 µs Time from PWDN to OUT± change from active to TRISTATE. Figures 5, 6 12 ns tON tOFF LVDS Output Enable Time LVDS Output Disable Time Use an alternating 1 and 0 pattern at 200 Mbps, measure between 20% and 80% of VOD. Figures 2, 4 Use an alternating 1 and 0 pattern at 200 Mbps, measure at 50% VOD between input to output. Figures 2, 3 Note 5: Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Note 6: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 7: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%). Note 10: Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, K28.5 pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). Note 12: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization. 5 www.national.com DS15BR400/DS15BR401 Symbol DS15BR400/DS15BR401 DC Test Circuits 20188925 FIGURE 1. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams 20188926 FIGURE 2. Differential Driver AC Test Circuit 20188927 FIGURE 3. Propagation Delay Timing Diagram 20188928 FIGURE 4. LVDS Output Transition Times www.national.com 6 DS15BR400/DS15BR401 20188929 FIGURE 5. Enable/Disable Time Test Circuit 20188930 FIGURE 6. Enable/Disable Time Diagram 7 www.national.com DS15BR400/DS15BR401 INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V. Please refer to application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information. Application Information INTERNAL TERMINATIONS The DS15BR400 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to minimize the output return loss and does not take the place of the 100 ohm termination at the inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external component count resulting in space savings. The DS15BR401 has 100Ω output terminations only. DECOUPLING Each power or ground lead of the DS15BR400 should be connected to the PCB through a low inductance path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing power plane closer to the top of the board reduces effective via length and its associated inductance. Bypass capacitors should be placed close to VDD pins. Small physical size capacitors, such as 0402, X7R, surface mount capacitors should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor. An X7R surface mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30 MHz or so, X7R capacitors behave as low impedance inductors. To extend the operating frequency range to a few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2–3 mils. With a 2 mil FR4 dielectric, there is approximately 500 pF per square inch of PCB. The center dap of the LLP package housing the DS15BR400 should be connected to a ground plane through an array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of the LLP package. OUTPUT CHARACTERISTICS The output characteristics of the DS15BRB400/DS15BR401 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. POWERDOWN MODE The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all input and output buffers and internal bias circuitry are powered off. When exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Characteristics PRE-EMPHASIS Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. One pin is used to select the preemphasis level for all outputs, off or on. The pre-emphasis boost is approximately 6 dB at 750 MHz. Pre-emphasis Control Selection Table www.national.com PEM Pre-Emphasis 0 Off 1 On 8 The DS15BR400 and DS15BR401 accept differential signals and allow simple AC or DC coupling. With a wide common mode range, the DS15BR400 and DS15BR401 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS15BR400 inputs are internally terminated with a 100Ω resistor while the DS15BR401 inputs are not, therefore the latter requires external input termination. 20188941 Typical LVDS Driver DC-Coupled Interface to DS15BR400 Input 20188942 Typical CML Driver DC-Coupled Interface to DS15BR400 Input 20188943 Typical LVPECL Driver DC-Coupled Interface to DS15BR400 Input 9 www.national.com DS15BR400/DS15BR401 INPUT INTERFACING DS15BR400/DS15BR401 OUTPUT INTERFACING The DS15BR400 and DS15BR401 output signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. 20188944 Typical DS15BR400 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver www.national.com 10 Power Supply Current vs. Data Rate Data Rate vs. Cable Length (0.25 UI Criteria) 20188920 20188923 Total Jitter vs. Ambient Temperature Data presented in this graph was collected using the DS15BR400EVK, a pair of RJ-45 to SMA adapter boards and various length Belden 1700a cables. The maximum data rate was determined based on total jitter (0.25 UI criteria) measured after the cable. The total jitter was a peak to peak value measured with a histogram including 3000 window hits. Data Rate vs. Cable Length (0.5 UI Criteria) 20188921 Total Jitter vs. Data Rate 20188924 Data presented in this graph was collected using the DS15BR400EVK, a pair of RJ-45 to SMA adapter boards and various length Belden 1700a cables. The maximum data rate was determined based on total jitter (0.5 UI criteria) measured after the cable. The total jitter was a peak to peak value measured with a histogram including 3000 window hits. 20188922 11 www.national.com DS15BR400/DS15BR401 Typical Performance Characteristics DS15BR400/DS15BR401 Physical Dimensions inches (millimeters) unless otherwise noted 48-TQFP NS Package Number VBC48a Order Number DS15BR400TVS, DS15BR401TVS (250 piece Tray) Order Number DS15BR400TVSX, DS15BR401TVSX (1000 piece Tape and Reel) 32-LLP (See AN-1187 for PCB Design and Assembly Recommendations) NS Package Number SQA32A Order Number DS15BR400TSQ, DS15BR401TSQ (1000 piece Tape and Reel) DS15BR400TSQX, DS15BR401TSQX (4500 piece Tape and Reel) www.national.com 12 DS15BR400/DS15BR401 www.national.com 13 DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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