CLC5801 High Speed Low Noise Voltage Feedback Amplifier General Description Features The CLC5801 is a low-cost, wideband voltage feedback amplifier excellent for low noise applications. It combines a wide bandwidth of 420MHz with very low noise (2nV/ , 1.8pA/ ) and low DC errors (100µV VOS) making it an excellent precision high speed op amp offering closed-loop gains of ≥ 10. The CLC5801 employs a traditional voltage-feedback topology and provides all the benefits of balanced inputs, such as low offsets and drifts, as well as 96dB open-loop gain, 95dB CMRR and a 90dB PSRR. Providing a wide 420MHz bandwidth at a gain of AV = 10, a fast 300V/µs slew rate, the CLC5801 is well suited for wide band active filters and low noise loop filters for PLLs. The low noise, wide gain-bandwidth, high slew rate and low DC errors enable applications such as medical diagnostic ultrasound, magnetic tape and disk storage, communications and optoelectronics that require maximum high-frequency signal-to-noise ratios. Low noise and offset make the CLC5801 and ideal preamplifier for CD-ROMs and receivers. The CLC5801 consumes 16mA of supply current and can be used in either dual 5V systems or single supply applications. It can easily drive a 100Ω load to within 1.6V of either rail. The CLC5801 is available in both SOIC-8 and the tiny SOT23-5. (TA = 25˚C, VS = ± 5V, RL = 100Ω Typical unless specified). n 420MHz, −3dB bandwidth (AV = 10) n 2nV/ input voltage noise n 1.8pA/ input current noise n 100µV input offset voltage n 300V/µs slew rate n 16mA supply current n 18ns settling time Applications n n n n n n Ultrasound preamplifier CD-ROM preamplifer Photo-diode transimpedance amplifier Low-noise loop filters for PLLs High-performance receivers ADC preamplifier Equivalent Input Noise DS101307-1 Connection Diagrams 5-Pin SOT23-5 8-Pin SOIC DS101307-2 Top View © 2000 National Semiconductor Corporation DS101307-3 Top View DS101307 www.national.com CLC5801 High Speed Low Noise Voltage Feedback Amplifier May 2000 CLC5801 Ordering Information Package 8-pin SOIC 5-pin SOT23-5 www.national.com Part Number Packaging Marking Transport Media NSC Drawing CLC5801IM CLC5801IMX CLC5801IM Rails M08A CLC5801IM 2.5k Tape and Reel CLC5801IM5 A50A 1k Units Tape and Reel CLC5801IM5X A50A 3k Units Tape and Reel 2 MF05A Operating Rating(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC IOUT Short Circuit protected to ground. Maximum reliability is obtained if IOUT does not exceed: Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec) ESD (human body model) CLC5801 Absolute Maximum Ratings (Note 1) Thermal Resistance (θJC) SOIC 65˚C/W SOT23-5 ± 7V 115˚C/W Thermal Resistance (θJA) 125mA ± VCC +125˚C −65˚C to +150˚C +300˚C 1000V SOIC 145˚C/W SOT23-5 185˚C/W Temperature Range −40˚C to +85˚C ± 10 to ± 1000V/V Recommended Gain Range Electrical Characteristics (TA = 25˚C, VCC = ± 5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω; unless specified). Symbol Parameter Conditions Typ +25˚C Min/Max Ratings (Note 2) −40˚C +25˚C Units +85˚C Frequency Domain Response GBW Gain Bandwidth Product VO < 0.4VPP 1.8 SSBW −3dB Bandwidth (AV = +10) VO < 0.4VPP 420 −3dB Bandwidth (AV = +20) VO < 0.4VPP 90 1.3 GHz 70 MHz LSBW −3dB Bandwidth VO < 5.0VPP 35 30 GFP Gain Flatness Peaking DC to 30MHz, VO < 0.4VPP 0.4 0.5 dB GFR Gain Flatness Rolloff DC to 30MHz, VO < 0.4VPP 0.2 0.5 dB Linear Phase Deviation DC to 30MHz, VO < 0.4VPP 0.8 1.5 Deg LPD Time Domain Response TRS Rise and Fall Time 0.4V step 4.0 4.7 ns TSS Settling Time to 0.2% 2V step 18 30 ns OS Overshoot 0.4V step 5 10 % SR Slew Rate 2V step 300 250 V/µs dBc Distortion And Noise Response HD2 2nd Harmonic Distortion 1VPP,10MHz −53 −48 HD3 3rd Harmonic Distortion 1VPP,10MHz −78 −65 IMD 3rd Order Intermod. Intercept 10MHz 34 VN Equivalent Input Noise Voltage 1MHz to 100MHz 2.0 2.7 nV/ ICN Equivalent Input Noise Current 1MHz to 100MHz 1.8 2.5 pA/ DC 96 77 86 86 dBc dBm Static, DC Performance AOL Open-Loop Gain dB VIO Input Offset Voltage (Note 3) ± 800 ± 1000 µV Offset Voltage Average Drift ± 100 ±2 ± 1000 DVIO 8 – 4 µV/˚C IB Input Bias Current (Note 3) 12 40 20 20 µA DIB Bias Current Average Drift −100 −250 – −120 µA/˚C IIO Input Offset Current 3.4 2.0 2.0 µA DIIO Offset Current Average Drift ± 0.2 ±3 ± 50 – ± 25 nA/˚C dB PSRR Power Supply Rejection Ratio DC 90 80 85 84 CMRR Common Mode Rejection Ratio DC 95 84 88 86 dB ICC Supply Current (Note 3) RL = ∞ 16 18 17 17 mA 3 www.national.com CLC5801 Electrical Characteristics (Continued) (TA = 25˚C, VCC = ± 5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω; unless specified). Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units +25˚C −40˚C +25˚C +85˚C Common-Mode 2 0.6 1.6 1.6 MΩ Differential-Mode 6 1 3 3 kΩ Miscellaneous Performance RINC Input Resistance RIND CINC Input Capacitance CIND Common-Mode 1.5 3 3 3 pF Differential-Mode 1.9 3 3 3 pF ROUT Output Resistance Closed Loop VO Output Voltage Range RL = ∞ VOL RL = 100Ω 5 50 10 10 mΩ ± 3.8 ± 3.4 ± 3.8 ± 3.5 ± 2.8 ± 3.4 ± 3.7 ± 3.2 ± 3.5 ± 3.7 ± 3.2 ± 3.5 V CMIR Input Voltage Range Common-Mode IOP Output Current Source 80 60 65 65 Sink 80 40 55 55 ION V V mA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed, Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: 100% tested at +25˚C. www.national.com 4 (TA = 25˚C, VCC = ± 5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω, unless otherwise specified). Non-Inverting Frequency Response Inverting Frequency Response DS101307-4 Frequency Response for Various RLs DS101307-5 Open Loop Gain and Phase vs. RL DS101307-6 DS101307-7 Open Loop Gain and Phase vs. Temp Gain Flatness & Linear Phase Deviation DS101307-9 DS101307-8 5 www.national.com CLC5801 Typical Performance Characteristics CLC5801 Typical Performance Characteristics (TA = 25˚C, VCC = ± 5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω, unless otherwise specified).. (Continued) Equivalent Input Noise Maximum Output Swing vs. Frequency DS101307-1 Closed-Loop Output Impedance DS101307-11 CMRR vs. Common Mode Input Voltage DS101307-13 DS101307-12 Common Mode Input Impedance Differential Input Impedance DS101307-14 www.national.com DS101307-15 6 (TA = 25˚C, VCC = ± 5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω, unless otherwise specified).. (Continued) Pulse Response (VO = 1VPP) Large Signal Pulse Response (VO = 2VPP) DS101307-16 Settling Time vs. Gain DS101307-17 Short Term Settling Time DS101307-18 Long Term Settling Time DS101307-19 Settling Time vs. CL and RS DS101307-20 DS101307-21 7 www.national.com CLC5801 Typical Performance Characteristics CLC5801 Typical Performance Characteristics (TA = 25˚C, VCC = ± 5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω, unless otherwise specified).. (Continued) 2nd & 3rd Harmonic Distortion (VO = 1VPP) Distortion vs. Gain (VO = 1VPP, fo = 3MHz) DS101307-23 DS101307-22 2-Tone, 3rd Order Intermod. Intercept. Output Voltage vs. Load DS101307-24 CMRR and PSRR DS101307-25 Typical DC Errors vs. Temperature DS101307-26 DS101307-27 www.national.com 8 CLC5801 Application Information Introduction The CLC5801 is a very wide gain-bandwidth, low noise voltage feedback operational amplifier which enables applications areas such as medical diagnostic ultrasound, magnetic tape & disk storage and fiber-optics to achieve maximum high-frequency signal-to-noise ratios. The following discussion will describe the proper selection of external components in order to achieve optimum device performance. DS101307-29 FIGURE 2. Inverting Amplifier Configuration Total Input Noise vs. Source Resistance In order to determine maximum signal-to-noise ratios from the CLC5801, an understanding of the interaction between the amplifier’s intrinsic noise sources and the noise arising from its external resistors is necessary. Figure 3 describes the noise model for the non-inverting amplifier configuration showing all noise sources. In addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in−) sources, there also exists thermal voltage noise ( ) associated with each of the external resistors. Equation (1) provides the general form for total equivalent input voltage noise density (eni). Equation (2) is a simplification of Equation (1) that assumes Rf || Rg = Rseq for bias current cancellation. Figure 4 illustrates the equivalent noise model using this assumption. Figure 5 is a plot of eni against equivalent source resistance (Rseq) with all of the contributing noise sources of Equation (2) shown. This plot gives the expected eni for a given Rseq which assumes Rf || Rg = Rseq for bias current cancellation. The total equivalent output voltage noise (eno) is eni x AV. DS101307-28 FIGURE 1. Non-Inverting Amplifier Configuration Bias Current Cancellation In order to cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain-setting (Rg) and feedback (Rf) resistors should equal the equivalent source resistance (Rseq) as defined in Figure 1. Combining this constraint with the non-inverting gain equation also seen in Figure 1, allows both Rf and Rg to be determined explicitly from the following equations: Rf = AVRseq and Rg = Rf/(AV−1). When driven from a 0Ω source, such as that from the output of an op amp, the non-inverting input of the CLC5801 should be isolated with at least a 25Ω series resistor. As seen in Figure 2, bias current cancellation is accomplished for the inverting configuration by placing a resistor (Rb) on the non-inverting input equal in value to the resistance seen by the inverting input (Rf || (Rg + Rs)). Rb is recommended to be no less than 25Ω for best CLC5801 performance. The additional noise contribution of Rb can be minimized through the use of a shunt capacitor. DS101307-30 FIGURE 3. Non-Inverting Amplifier Noise Model (1) 9 www.national.com CLC5801 Application Information (Continued) DS101307-32 FIGURE 4. Noise Model with Rf || Rg = Rseq DS101307-35 FIGURE 6. External Lag Compensation (2) Single-Supply Operation The CLC5801 can be operated with single power supply as shown in Figure 7. Both the input and output are capacitively coupled to set the DC operating point. As seen in Figure 5, eni is dominated by the intrinsic voltage noise (en) of the amplifier for equivalent source resistance below 121Ω. Between 121Ω and 5.11kΩ, eni is dominated by the thermal noise ( ) of the external resistors. Above 5.11kΩ, eni is dominated by the amplifier’s current noise ( Rseq). The point at which the CLC5801’s voltage noise and current noise contribute equally occurs for Rseq = 786Ω ( ). As an example, configured with a gain of +20V/V giving a −3dB of 90MHz and driven from an Rseq = 25Ω, the CLC5801 produces a total equivalent input noise voltage ( ) of 26µVrms. DS101307-36 FIGURE 7. Single Supply Operation Low Noise Transimpedance Amplifier Figure 8 shows a transimpedance amplifier used to amplify the small signal from a Photodiode. Using a low noise amplifier such as the CLC5801 and proper design, ensures that the amplifier noise contribution is minimal. Here Rb can be used to compensate for the input bias current of the CLC5801. Generally, Rb is selected to be equal to Rf to cancel the effect of Ib flowing in each of the Op Amp input terminals. DS101307-34 FIGURE 5. Voltage Noise Density vs. Source Resistance If bias current cancellation is not a requirement, then Rf || Rg does not need to equal Rseq. In this case, according to Equation (1), Rf || Rg should be as low as possible in order to minimize noise. Results similar to Equation (1) are obtained for the inverting configuration of Figure 2 if Rseq is replaced by Rb and Rg is replaced by Rg + Rs. With these substitutions, Equation (1) will yield eni referred to the non-inverting input. Referring eni to the inverting input is easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains. Inverting Gains Less Than 10V/V The lag compensation of Figure 6 will achieve stability for lower gains. Placing the network between the two input terminals does not affect the closed-loop nor noise gain, but is best used for the inverting configuration because of its affect on the non-inverting input impedance. DS101307-37 FIGURE 8. Transimpedance Amplifier Configuration Figure 9 shows the equivalent noise analysis schematic for this circuit. The complete expression for the amplifier stage output rms noise is shown in Equation (3). (3) www.national.com 10 High-Gain Sallen-Key Active Filters (Continued) The CLC5801 is well suited for high-gain Sallen-key type of active filters. Figure 11 shows the 2nd order Sallen-Key low pass filter topology. Using component predistortion methods as discussed in OA-21 enables the proper selection of components for these high-frequency filters. DS101307-39 FIGURE 9. Transimpedance Amplifier Noise Model Low Noise Integrator The Circuit in Figure 10 implements a deBoo integrator. Integration linearity is maintained through positive feedback. The CLC5801’s low input offset voltage and matched inputs allowing bias current cancellation provide for very precise integration. Stability is maintained through the constraint on the circuit elements. DS101307-41 FIGURE 11. Sallen-Key Active Filter Topology Low Noise Magnetic Media Equalizer The circuit in Figure 12 implements a high-performance low-noise equalizer for such applications as magnetic tape channels. The circuit combines an integrator with a bandpass filter to produce the low-noise equalization. The circuit’s simulated frequency response is illustrated in Figure 13. DS101307-40 FIGURE 10. Low Noise Integrator DS101307-42 FIGURE 12. Low Noise Magnetic Media Equalizer 11 www.national.com CLC5801 Application Information CLC5801 Application Information Low-Noise Phase-Locked Loop Filter (Continued) The CLC5801 is extremely useful as a Phase-Locked Loop filter in such applications as frequency synthesizers and data synchronizers. The circuit of Figure 14 implements one possible PLL filter with the CLC5801. DS101307-44 FIGURE 14. Phase-Locked Loop Filter DS101307-43 Printed Circuit Board Layout Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillation, see OA-15 for more information. National includes an evaluation board with samples as a guide for high frequency lay-out and as an aid in device testing and characterization. FIGURE 13. Equalizer Frequency Response www.national.com 12 CLC5801 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC Order Numbers CLC5801IM and CLC5801IMX NS Package Number MA08A 13 www.national.com CLC5801 High Speed Low Noise Voltage Feedback Amplifier Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 5-Pin SOT23-5 Order Numbers CLC5801IM5 and CLC5801IM5X NS Package Number MF05A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.