LM8342 Programmable TFT VCOM Calibrator with Non-Volatile Memory General Description Features The LM8342 is an integrated combination of a non-volatile register (7 bits EEPROM) and a DAC controlled current source. Using the LM8342, the VCOM calibration procedure is simplified by elimination of the potentiometer adjustment task. This adjustment task is currently performed at the factory using a trimmer adjustment tool and visual inspection. The VCOM adjustment can be done electronically in production, using the I2C compatible interface. The factory operator can physically view the screen head-on (frontal viewing) when performing this step, easing manufacturing especially for large TFT panels. The VCOM level is typically at half AVDD (determined by R1 and R2) and is buffered by the actual VCOM driver. By controlling the level of IOUT, the VCOM level can be tuned. The current level at the output of the LM8342 is a fraction (1/128 to 128/128) of a maximum current which is set by RSET and an analog reference (AVDD). The actual fraction is determined by the 7-bit DAC. As a result, the output current of the LM8342 has a good temperature stability yielding a very stable VCOM adjustment. Controlling the DAC setting of the LM8342 is done via its I2C compatible interface. The actual DAC setting is stored in a volatile register. Using a “Write to EE” command the data can be stored permanently in the embedded EEPROM. At power on of the device, the EEPROM data is copied to the volatile register, setting the DAC. At any time, the data in the EEPROM can be changed again via the I2C compatible interface. n I2C compatible programmable DAC to set the output current n Guaranteed monotonic DAC n Non-volatile memory to hold the setting n EEPROM in system programmable n No external programming voltage required n Maximum interface bus speed is 400 kHz n LLP-10 Package Applications n TFT panel factory calibration n Digital potentiometer n Programmable current sink Typical Application 20139201 © 2005 National Semiconductor Corporation DS201392 www.national.com LM8342 Programmable TFT VCOM Calibrator with Non-Volatile Memory November 2005 LM8342 Absolute Maximum Ratings (Note 1) Junction Temperature (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Soldering Information +150˚C Infrared or Convection (20 sec.) 235˚C Wave Soldering (10 sec.) 260˚C ESD Tolerance (Note 2) Human Body Model SCL, SDA Pins: 4 kV All Other Pins: 2.5 kV Operating Ratings (Note 1) 250V Operating Temperature Range (Note 4) −40˚C to 85˚C Digital Supply (VDD) (Note 5) 2.25V to 3.6V Machine Model Supply and Reference Voltage VDD 5V AVDD 20V Storage Temperature Range Digital Supply (VDD) @ Programming 2.6V to 3.6V Analog Reference (AVDD) (Note 5) 4.5V to 18V Package Thermal Resistance θJA (Note 3) −65˚C to +150˚C 52˚C/W Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25˚C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 7) Typ (Note 8) Max (Note 7) Units Supply and Reference Current IDD Supply Current 40 62 µA AIDD Analog Reference Current 8 13 µA Control and Programming SCL, SDA Low Voltage 0.3 * VDD High Voltage 0.7 * VDD Input Current Frequency WPP/WPN Low Level WPP/WPN High Level RON 1 µA 400 kHz 0.3 * VDD V 0.7 * VDD WPN Input Current VIH = 3.0V. (Note 9) SDA/SCL Input Capacitance SCL-S Input Capacitance SDA/SCL/SCL-S load current No Supply, VSDA, VSCL = 3.6V Programming Time (Note 4) V 100 SCL to SCL-S Switch Resistance µA 150 Ω 5 pF 3 pF 1 IDD @ Programming Programming Cycles 1000 Reading Cycles 10000 V µA 200 300 ms 10 18 mA Output Output Settling Time 95% of Final Value Start-Up Time VOUT Output Voltage IOUT Output Current µs 30 µs VRSET + 0.5V Adjustability Differential Non-Linearity Zero Scale Error AVDD 7 AVDD = 10V, VOUT = 5V. Full Scale Error Full Scale Range Voltage Drift VRSET www.national.com 10 2 V Bits −1 1 −1 1.5 −4 4 5 100 µA −1 1 LSB LSB (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics tables. Note 2: Human Body Model is 1.5 kΩ in series with 100 pF. Machine Model is 0Ω in series with 200 pF. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. Note 4: Programming temperature range 0˚C to 70˚C . Note 5: When AVDD is in the voltage range of 4.5V to 13V, the supply voltage VDD can be in 2.25V to 3.6V range. When AVDD is in the voltage range from 13V to 18V, the supply voltage VDD is limited to the 2.6V to 3.6V range Note 6: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 7: All limits are guaranteed by design or statistical analysis. Note 8: Typical values represent the parametric norm at the time of characterization. Note 9: On-Chip Pull Down Resistor of 30 kΩ. Connection Diagram 10-Pin LLP 20139202 Top View Pin Descriptions Pin Name Pin # Function OUT 1 Current sink output, adjustable in 128 steps. See Application Section for details. AVDD 2 Analog reference voltage input WPN 3 Write protect (input) READ (I2C) WRITE→Reg WRITE→EE SCL Switch WPN = Low yes yes no open WPN = High yes yes yes closed WPP 4 Inverted WPN (output) GND 5 Ground VDD 6 Supply voltage SDA 7 I2C compatible serial data input/output SCL 8 I2C compatible serial clock input SCL-S 9 Switched SCL connection. Serial clock input when WPN is set to high SET 10 Maximum output current adjustment pin (see block diagram) Ordering Information Package 10-Pin LLP Part Number LM8342SD LM8342SDX Package Marking Transport Media 1k Units Tape and Reel L8342 4.5k Units Tape and Reel 3 NSC Drawing SDA10A www.national.com LM8342 Electrical Characteristics LM8342 Block Diagram 20139203 www.national.com 4 At TJ = 25˚C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and IDD vs. VDD IDD vs. Temperature 20139228 20139227 AVDD Startup (Full Scale) VDD Startup (Full Scale) 20139220 20139219 IOUT vs. RSET IOUT vs. RSET 20139216 20139215 5 www.national.com LM8342 Typical Performance Characteristics RSET = 10 kΩ, unless otherwise specified. LM8342 Typical Performance Characteristics At TJ = 25˚C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified. (Continued) IOUT Current Step Negative (Full Scale) IOUT Current Step Positive (Full Scale) 20139207 20139208 IOUT vs. VOUT IOUT Error vs. VOUT 20139217 20139214 Differential Non-Linearity Error vs. DAC (VOUT = 18V) Gain & Offset Change vs. VOUT 20139221 20139222 www.national.com 6 IOUT Error vs. VDD IOUT Error vs. AVDD 20139210 20139226 IOUT Error vs. Temperature Total Unadjusted Error vs. DAC 20139209 20139213 Integral Non-Linearity Error vs. DAC Differential Non-Linearity Error vs. DAC 20139212 20139211 7 www.national.com LM8342 Typical Performance Characteristics At TJ = 25˚C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified. (Continued) LM8342 Typical Performance Characteristics At TJ = 25˚C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified. (Continued) RON vs. SCL-S Voltage 20139225 www.national.com 8 INTRODUCTION The LM8342 is an integrated combination of a digitally controlled current sink and a non-volatile register (7 bits EEPROM). Programming the register can be done using the I2C compatible interface. The LM8342 replaces the potentiometer adjustment, and thereby simplifies the VCOM calibration procedure. With the LM8342, the factory operator can physically view the screen head-on when performing this step, easing manufacturing especially for large TFT panel sizes. The following sections discuss the principle of operation of a TFT-LCD and, subsequently give a description of how to use the LM8342, including the I2C compatible interface and control inputs. After this, two typical LM8342 configurations are presented. Subsequently an evaluation system is introduced, including a µC-board programming using the I2C compatible interface. At the end of this application section board layout recommendations are given. PRINCIPLE OF OPERATION OF A TFT-LCD This section offers a brief overview of the principle of operation of TFT-LCD’s. It gives a detailed description of how information is presented on the display. Further an explanation of how data is written to the screen pixels and how the pixels are selected is included. 20139224 FIGURE 2. TFT Display Figure 2 shows a simplified diagram of a TFT display, showing how individual pixels are connected to the row, column and VCOM driver. Each pixel is represented by a capacitor with an NMOS transistor connected to its top plate. Pixels in a TFT panel are arranged in rows and columns. Row lines are connected to the NMOS gates, and column lines to the NMOS sources. The back plate of every pixel is connected to a common voltage called VCOM. The voltage applied to the top plates (i.e. Gamma Voltage) controls the pixel brightness. The column drivers supply this gamma voltage via the column lines, and ‘write’ this voltage to the pixels one row at a time. This is accomplished by having the row drivers selecting an individual row of pixels when the column drivers write the gamma voltage levels. The row drivers sequentially apply a large positive pulse (typically 25V to 35V) to each row line. This turns on the NMOS transistors connected to an individual row, allowing voltage from the column lines to be written to the pixels. 20139223 FIGURE 1. Individual LCD Pixel Figure 1 shows a simplified illustration of an individual LCD pixel. The top and bottom plates of a pixel consist of IndiumTin Oxide (ITO), which is a transparent, electrically conductive material. ITO is at the inner surfaces of two glass sub- 9 www.national.com LM8342 strates that are the front and back glass panels of a TFT display. Sandwiched between two ITO plates is an insulating material (liquid crystal). Liquid crystals alter the polarization of light, depending on how much voltage (VPIXEL) is applied across the two plates. Polarizers are placed on the outer surfaces of the two glass substrates. In combination with the liquid crystal, the polarizers create an electrically variable light filter that modulates light transmitted from the back to the front of a display. A pixel’s bottom plate is at the backside of a display where a light source is applied, and the top plate is at the front, facing the viewer. For most TFT displays, a pixel transmits the greatest amount of light when VPIXEL ≤ ± 0.5V, and it becomes less transparent as the voltage increases with either positive or negative polarity. Application Section LM8342 Application Section (Continued) 20139218 FIGURE 3. TFT Panel Block Diagram PRINCIPLE OF OPERATION OF THE LM8342 The LM8342 is an integrated combination of a digitally controlled current sink and a non-volatile register (7 bits EEPROM). Writing data can be done using the I2C compatible interface. Data can be written to a volatile register and can also be stored in the non-volatile EEPROM. A simplified block diagram of the LM8342 is given in Figure 4. Figure 3 shows a block diagram of a TFT panel. The VCOM buffer supplies a common voltage (VCOM) to all the pixels in a TFT panel. In general, VCOM is a DC voltage that is in the middle of the gamma voltage range. Screen performance can be optimized by tuning the VCOM voltage in the calibration procedure. Using the LM8342, the VCOM calibration procedure is simplified by elimination of the potentiometer adjustment task. This task is currently performed at the factory using a trimmer adjustment tool and visual inspection, when using a stable reference voltage and a potentiometer as a voltage divider to generate the VCOM voltage. 20139229 FIGURE 4. Block Diagram of the LM8342 www.national.com 10 (Continued) Pin name The maximum output current of the LM8342 can be defined using an external resistor RSET in combination with an analog reference voltage AVDD. This maximum current can be calculated using Equation (1). WPN “Write Protect Not” (Input) has 2 functions: 1. Prohibits programming the EEPROM, when low or left floating (Internal a pull-down resistor is connected) When WPN is set to a low level, only the volatile register is accessible. If WPN is set to a high level also the EEPROM is accessible. Actual writing to the EEPROM or the register is done using the “P-bit” in the serial communication. 2. WPN switches the SCL-S clock line. When WPN is set to a high level SCL-S is connected to SCL. The operator should turn off the original SCL clock. WPP Write Protect Signal (Output). This is the inverted WPN signal. (1) The operating range for the output current is given in the Electrical Characteristics table on page 2. Variations of the voltage reference AVDD or the external resistor RSET will affect this output current. Using a resistor with a low temperature coefficient is recommended. The relative value of IOUT with respect to the maximum current can be controlled digitally in 128 steps, using the internal DAC. This results in an output current described by Equation (2). Function I2C SERIAL INTERFACE BUS The LM8342 supports an I2C compatible communication protocol, which is a bidirectional bus oriented communication protocol. Any device that sends data on the bus is defined as a transmitter and the receiving device as a receiver. The I2C compatible communication protocol uses 2 wires: SDA (Serial Data Line) and SCL (Serial Clock Line). For both lines an external pull-up resistor, connected to the supply voltage, is required. The device controlling the bus is known as the master, and the device or devices being controlled are the slaves. Each device has its own specific address. The address of the LM8342 is 9EHEX. The master initiates the communication and provides the clock. The LM8342 always operates as a slave. A typical system using an I2C compatible interface bus is given in Figure 5. (2) Using the serial interface bus the operator can store the DAC value in the LM8342s 7-bits volatile register temporarily, or permanent in the EEPROM. During a start-up sequence the LM8342 will copy the contents of the EEPROM to the register setting the DC value. CONTROLLING THE DEVICE The LM8342s current sink can be programmed using a serial interface bus. Additional functions (e.g. storing data in the EEPROM) can be controlled in combination with external inputs. Table 1 shows the pins of the LM8342 and gives a short functional description. TABLE 1. Pin Descriptions Pin name Function SDA & SCL The LM8342 output current can be (Serial interface controlled using the serial I2C compatible interface. This 2-Wire bus) interface uses a clock and a data signal. New values can be written to the memory, or the current value can be read back from the device. The I2C compatible interface is discussed in more detail in the next chapter. AVDD Analog reference voltage for the DAC. VDD Supply voltage for both the analog and digital circuitry. SET An external resistor RSET connected to the SET pin determines the maximum output current, see Equation (1). OUT The output of the programmable current sink. SCL-S 20139231 FIGURE 5. System Using an I2C compatible Bus The LM8342 can be used in an I2C compatible system. All specifications of the LM8342, dealing with the interface bus, are guaranteed by design. Except for the bus speed, which is specified in the Electrical Characteristics table. KEY ASPECT OF I2C COMPATIBLE COMMUNICATION In this section a brief overview is presented, discussing the key aspect of I2C compatible communication. Figure 6 shows the timing aspects of the I2C compatible serial interface. For in-circuit PCB testing, the LM8342 can use the additional Switched SCL signal (SCL-S) input for applying the SCL clock signal. 11 www.national.com LM8342 Application Section LM8342 Application Section (Continued) 20139204 FIGURE 6. Timing Diagram The timing diagram shows the major aspect of the communication protocol and represents a typical data stream. In case a master wants to setup a data transfer, it tests if “the bus is busy.” If it is not busy, then the master starts the data transfer by creating a “start data transfer” situation. Accordingly the corresponding receiver is selected by sending the appropriate “slave address.” This receiver gives an “acknowledge” on recognizing its address on the bus. The master continues the data transfer by sending the data stream. Again the receiver gives an “acknowledge” after receipt. Depending on the amount of data the master will continue or create a “stop data transfer” situation. Table 2 gives a more detailed description of the I2C compatible communication. TABLE 2. Detailed Description of I2C compatible Communication Definitions Bus not busy The I2C compatible bus is not busy when both data (SDA) and clock (SCL) lines remain HIGH. The controller can initiate data transfer only when the bus is not busy. Start Data Transfer Starting from an idle state (bus not busy) a START condition consists of a HIGH to LOW transition of SDA while SCL is HIGH. All commands must start with a START condition. Slave address After generating a start condition, the master transmits a 7-bit slave address. (The LM8342 uses the 8th bit for selecting the R/W operation, but this does not affect the address.) The address for the LM8342 is 9EHEX. R/W-bit www.national.com If the value of the R/W bit is HIGH, the data is read from the register of the LM8342. Otherwise the current DAC setting is written to the LM8342. 12 Acknowledge A receive device, when addressed, is obliged to generate an “acknowledge” after the reception of each byte. The master generates an extra clock cycle that is associated with this acknowledge bit. The receiver has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of SCL, with respect to the SCL timing specifications. Data byte A data byte consists of 8 bits. 7 bits are used for the DAC setting of the LM8342. The 8th bit is known as the P-bit. P-bit The function of the P-bit depends on the Read/Write operation (R/W-bit). During a Read operation of the LM8342, the P-bit indicates the programming state of the EEPROM. During a Write operation, the register or both the register and the EEPROM of the LM8342 can be selected as destination. A more detailed description of the P-bit is given in Table 3 . Stop Data Transfer A STOP condition consists of a LOW to HIGH transition of SDA while SCL is HIGH. All operations must be ended with a STOP condition. Typical Application (Continued) The following section discusses two typical applications for the LM8342. In the first application the LM8342 is used as a programmable current sink, for example to drive a programmable bias generator. In the second application the LM8342 is used to adjust the voltage level of a VCOM driver. TABLE 3. P-bit Truth Table Operation P-bit Description Read 1 Programming Ready Read 0 Programming Busy (don’t turn off the device) Write 1 Register Write Write 0 EEPROM Write PROGRAMMABLE CURRENT SINK As described in the “Principle of Operation of the LM8342” section the LM8342 basically operates as a programmable current sink. Figure 7 shows a general current sink application. The LM8342 can be used in I2C compatible systems with clock speeds of up to 400 kbps (Fast mode). For low speed applications, an initial resistor value for the pull-up resistors is 15 kΩ is suitable. When increasing the speed of the interface bus, the user should decrease the value of the pull-up resistors. 20139233 FIGURE 7. Programmable Current Sink DRIVING A VCOM LEVEL Another typical application, given in Figure 8, is using the LM8342 to adjust the “voltage tap” of a resistive voltage divider. The VCOM driver buffers the “voltage tap” in this application. The output current of the LM8342 can be calculated using Equation (3). (3) 13 www.national.com LM8342 Application Section LM8342 Typical Application (Continued) 20139201 FIGURE 8. Typical Application Driving a VCOM Level The limits of VCOM for DAC10 = 0 (high limit) and DAC10 = 127 (low limit) are given by: The voltage level of the VCOM driver, for a general setting of (DAC10) , is calculated using Equation (4). (6) (4) For calibrating the VCOM level (see Figure 8) the tuning range of the design needs to be aligned to the required VCOM tuning range (∆VCOM). Figure 9 gives a graphical presentation of the desired voltage levels. (7) Using Equation (5),Equation (6), and Equation (7) the value for resistors R1 and R2 can be obtained, resulting in Equation (8) and Equation (9): (8) and (9) Table 4 gives an overview of resistor values for a typical value of AVDD, and 2 RSET values. All settings are for a VCOM level at VMID = 1⁄2 AVDD, and a maximum variation of ∆VCOM. 20139234 (10) FIGURE 9. VCOM Voltage Levels Assume the calibrator needs to cover the voltage range given in Equation (5). (5) www.national.com 14 (Continued) LAYOUT RECOMMENDATIONS TABLE 4. Overview Resistor Values for Different RSET Settings at AVDD = 15V A proper layout is necessary for optimum performance of the LM8342. A low impedance and proper ground plane (free of disturbances) is recommended, since a current of up to 10 mA can flow with HF contents during programming. The traces from the GND pin to the ground plane should be as short as possible. It is recommended to place decoupling capacitors close to the VDD and AVDD pins. Connections of these decoupling capacitors to the ground plane should be short. AVDD = 15V (VCOM Level = 7.5 V) RSET = 10 kΩ ∆VCOM (V) ± 0.5 ±1 ± 1.5 ±2 ± 2.5 ±3 R1 (Ω) RSET = 45 kΩ R2 (Ω) ∆VCOM (V) ± 0.5 ±1 ± 1.5 ±2 ± 2.5 ±3 25k 28.6k 47.1k 61.5k 66.7k 100k 84.2k 146k 100k 200k 114k 267k R1 (Ω) R2 (Ω) 113k 129k 212k 277k 300k 450k 379k 655k 450k 900k 514k 1.2M As SET is a sensitive input, crosstalk to that pin should be prevented. Special care should be taken when routing the interface connections. The signals on the serial interface can be more than 60 dB larger than the equivalent LSB at the SET input pin. Crosstalk between the interface bus and RSET results in disturbance of the output current IOUT of the LM8342. For applications requiring a low output current (using high values for RSET in combination with low DAC settings) special attention should be paid to the parasitic capacitance (CPAR) parallel to RSET. For CPAR larger than tens of pF, a small ( < 1 LSB) unwanted ripple at the output current might be obtained. It is recommended to place the RSET resistor close to the LM8342, in combination with a good board layout to reduce this parasitic capacitance. EVALUATION SYSTEM For the LM8342 a complete evaluation system is available, including two boards. Figure 10 gives a schematic representation. • LM8342 Evaluation Board This board demonstrates the functionality of the LM8342 using the I2C compatible interface for communication. The LM8342 can easily be demonstrated in 2 applications: • — Programmable current sink — Programmable VCOM level driver LM8342 Programmer Board This test board has dedicated functionality for communicating with the LM8342, using the I2C compatible interface. This board can operate in two different modes: — Write mode: The digitized value of a potentiometer setting is written to the LM8342. The user can select on the programmer board to write the data to the register or to store the data in the EEPROM. — Read mode: The board reads the stored values from the LM8342’s EEPROM and presents this data onto a 3-digit display. 20139232 FIGURE 10. LM8342 Evaluation System 15 www.national.com LM8342 Typical Application LM8342 Programmable TFT VCOM Calibrator with Non-Volatile Memory Physical Dimensions inches (millimeters) unless otherwise noted 10-Pin LLP NS Package Number SDA10A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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