LM2637 Motherboard Power Supply Solution with a 5-Bit Programmable Switching Controller and Two Linear Regulator Controllers General Description Both linear controllers have under voltage latch-off. The LM2637 provides a comprehensive embedded power supply solution for motherboards hosting high performance MPUs such as M II™, Pentium™ II, K6-2 and other similar high performance MPUs. The LM2637 incorporates a 5-bit programmable, synchronous buck switching controller and two high-speed linear regulator controllers in a 24-pin SO package. Features Switching Section — The switching regulator controller features a 5-bit programmable DAC, over-current and over-voltage protection, under-voltage latch-off, a power good signal, and output enable. The 5-bit DAC has a typical tolerance of 1%. There are two user-selectable over-current protection methods. One provides accurate over-current protection with the use of an external sense resistor. The other saves cost by taking advantage of the rDS_ON of the high-side FET. The over voltage protection provides two levels of protection. The first level keeps the high-side FET off and the low-side FET on. The second provides a gate signal that can be used to fire an external SCR. Linear Section — The two linear regulator controllers feature wide control bandwidth, N-FET and NPN transistor driving capability, and an adjustable output voltage. The wide control bandwidth makes meeting fast load transient response requirement such as that of the GTL+ bus an easy job. In minimum configuration, the two controllers default to 1.5V and 2.5V respectively. n Provides 3 regulated voltages n Power Good flag and output enable n Under-voltage latch-off Switching Section n Synchronous rectification n 5-bit DAC programmable from 3.5V to 1.3V n Typical 1% DAC tolerance n Switching frequency: 50 kHz to 1 MHz n Two levels of over-voltage protection n Two methods of over-current protection n Adaptive non-overlapping FET gate drives n Soft start without external capacitor Linear Section n N-FET and NPN driving capability n Ultra fast response speed n Output voltages default to 1.5V and 2.5V yet adjustable Applications n Embedded power supplies for PC motherboards n Triple DC/DC power supplies n Programmable high current DC/DC power supply Pin Configuration 24-Lead SOIC DS100848-1 Top View NS Package Number M24B M II™ is a trademark of Cyrix Corporation a wholly owned subsidiary of National Semiconductor Corporation. Pentium™ is a trademark of Intel Corporation. K6 is trademark of Advanced Micro Devices, Inc. © 1999 National Semiconductor Corporation DS100848 www.national.com LM2637 Motherboard Power Supply Solution with a 5-Bit Programmable Switching Controller and Two Linear Regulator Controllers October 1998 Absolute Maximum Ratings (Note 1) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Susceptibility 2.5 kV Soldering Time, Temperature (10 sec.) 300˚C VCC 7V VDD 17V Junction Temperature Operating Ratings (Note 1) 4.75V to 5.25V VCC 150˚C Power Dissipation (Note 2) −65˚C to +150˚C Junction Temperature Range 0˚C to +125˚C 1.6W Electrical Characteristics VCC = 5V, VDD = 12V unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the 0˚C to +70˚C range. Min Typ Max Units IEN Symbol EN Pin internal Pull-Up Current Parameter Conditions 60 90 140 µA IVID VID Pins internal Pull-Up Current 60 90 140 µA ICC Operating VCCCurrent IQ_VCC VCC Shutdown Current EN = 5V, VID = 10111 EN = 0V, VID Pins Floating 6 7.5 mA 1.5 3 mA N N+1.5% SWITCHING SECTION VDACOUT 5-Bit DAC Output Voltage IQ_VDD VDD Shutdown Current fOSC Oscillator Frequency (Note 3) EN = 0V, VID Pins Floating RT = 100 kΩ N−1.5% 4 204 RT = 25 kΩ 245 V µA 286 1000 kHz DMAX Maximum Duty Cycle 95 % DMIN Minimum Duty Cycle 0 % RSNS1 SNS1 Pin Resistance to Ground RDS_SRC Gate Driver Resistance When Sourcing Current 6 Ω RDS_SINK Gate Driver Resistance When Sinking Current 1.5 Ω VCC_TH1 Rising VCC Threshold for Power-On Reset VCC_TH2 Falling VCC Threshold for Power-On Reset 3.0 VDAC_IH DAC Input High Voltage 3.5 VDAC_IL DAC Input Low Voltage tPWGD PWGD Response Time SNS1 Rises from 0V to Rated Output Voltage 2 tPWBAD PWGD Response Time SNS1 Falls from Rated Output Voltage to 0V 2 VPWGD_HI PWGD High Trip Point % Above Rated Output Voltage when output Voltage↑ 8.5 4 % Above Rated Output Voltage when output Voltage ↓ (Note 4) VPWGD_LO PWGD Low Trip Point OVP Pin Trip Point ICS+ CS+ Pin Sink Current VOCP Over-Current Trip Point (CS+ and CS− Differential Voltage) www.national.com 5 % Below Rated Output Voltage when output Voltage↑ % Below Rated Output Voltage when output Voltage ↓ (Note 4) VOVP_TRP 10 % SNS1 Above Rated Output CS+ = 5V CS+ = 2V, CS− Drops from 2V 2 6 13 4.3 3.6 kΩ V V V 1.3 V 8.4 15 µs 3.4 10 µs 11.5 13 % 7 9 2.6 6 9.5 13 % 15 18 21 % 126 185 244 µA 41 55 69 mV Electrical Characteristics (Continued) VCC = 5V, VDD = 12V unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the 0˚C to +70˚C range. Symbol Parameter Conditions Min Typ Max Units SWITCHING SECTION OVP = 3V IOVP OVP Pin Source Current GA Error Amplifier DC Gain 10 76 mA dB BWEA Error Amplifier Unity Gain Bandwidth 5 MHz VRAMP_L Ramp Signal Valley Voltage 1.25 V VRAMP_H Ramp Signal Peak Voltage 3.25 V tSS Soft Start Time 4096 Clock Cycles DSTEP_SS Duty Cycle Step Change in Soft Start 12.5 % 1.5V LDO CONTROLLER SECTION VSNS2 SNS2 Voltage ROUT2 Output Resistance ISNS2 SNS2 Pin Bias Current VPWGD_HI PWGD High Trip Point VPWGD_LO PWGD Low Trip Point VDD = 12V, VCC = 4.75V to 5.25V, IG2 = 0 mA to 20 mA (Figure 1) 1.463 1.5 1.538 V 200 Ω 21 µA (Note 4) 0.63 V (Note 4) 0.44 V When Regulating 2.5V LDO CONTROLLER SECTION VSNS3 SNS3 Voltage ROUT3 Output Resistance ISNS3 SNS3 Pin Bias Current VPWGD_HI PWGD High Trip Point VPWGD_LO PWGD Low Trip Point VDD = 12V, VCC = 4.75V to 5.25V, IG3 = 0 mA to 20 mA (Figure 1) 2.438 2.5 2.563 V 200 Ω 21 µA (Note 4) 0.63 V (Note 4) 0.44 V When Regulating Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. Operating Ratings do not imply guaranteed performance limits. Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX − TA)/θJA. The junction-to-ambient thermal resistance, θJA, for LM2637 is 78˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 1.6W. Note 3: The letter N stands for the typical output voltages appearing in italic boldface type in Table 1. Note 4: The output level of the PWGD pin is a logic AND of the power good function of the switching section, the 1.5V section and the 2.5V section. 3 www.national.com Electrical Characteristics (Continued) TABLE 1. 5-Bit DAC Output Voltage Table (VCC = 5V, VDD = 12V ± 5%, TA = 25˚C, Test Mode) Symbol VDACOUT Parameter 5-Bit DAC Output Voltages for Different VID Codes Conditions VID4:0 = 01111 VID4:0 = 01110 Typical Units 1.30 V VID4:0 = 01101 VID4:0 = 01100 VID4:0 = 01011 1.40 VID4:0 = 01010 VID4:0 = 01001 VID4:0 = 01000 4 1.45 1.50 1.55 1.60 1.65 VID4:0 = 00111 VID4:0 = 00110 1.70 VID4:0 = 00101 VID4:0 = 00100 VID4:0 = 00011 1.80 VID4:0 = 00010 VID4:0 = 00001 VID4:0 = 00000 www.national.com 1.35 1.75 1.85 1.90 1.95 2.00 2.05 VID4:0 = 11111 VID4:0 = 11110 (shutdown) VID4:0 = 11101 VID4:0 = 11100 VID4:0 = 11011 2.2 VID4:0 = 11010 VID4:0 = 11001 VID4:0 = 11000 2.5 VID4:0 = 10111 VID4:0 = 10110 2.8 VID4:0 = 10101 VID4:0 = 10100 VID4:0 = 10011 3.0 VID4:0 = 10010 VID4:0 = 10001 VID4:0 = 10000 3.3 2.1 2.3 2.4 2.6 2.7 2.9 3.1 3.2 3.4 3.5 Block Diagram DS100848-30 Test Circuit DS100848-2 FIGURE 1. LDO Controller Test Circuit 5 www.national.com Typical Applications DS100848-3 FIGURE 2. Motherboard Power Supply for Pentium II Processor Core (1.3V - 2.8V, 14.2A), GTL+ Bus (1.5V, 4A), and Legacy I/O (2.5V, 0.3A). External sense resistor is used to provide both over-current limit and dynamic voltage positioning. www.national.com 6 Typical Applications (Continued) DS100848-4 FIGURE 3. Motherboard Power Supply for Pentium II Processor Core (1.8V - 2.8V, 14.2A), GTL+ Bus (1.5V, 4A), and Legacy I/O (2.5V, 0.3A). High side FET is used to provide the current limit. 7 www.national.com Pin Description Pin Pin Name Pin Function 1 LG Low side N-FET gate driver output. 2 PGND Ground for the two FET drivers of the switching section. 3 VDD Supply for the FET gate drivers. Usually tied to +12V. 4 SNS2 Feedback pin for the 1.5V linear regulator. 5 G2 Gate drive output for the external N-MOS of the fast 1.5V linear regulator. 6 SGND Ground for internal signal circuitry and system ground reference. 7 VCC Supply voltage. Usually +5V. 8 SNS1 Output voltage monitor input for the switching regulator. 9 CS+ Switching regulator current sense input, positive node. 10 CS− Switching regulator current sense input, negative node. 11 OVP Over-voltage protection output for the switching regulator. Can be used to fire an external SCR. 12 FREQ Switching frequency adjustment pin. An external resistor is needed to set the desired frequency. 13 EAO Output of the error amplifier. Used for compensating the switching regulator. 14 FB Inverting input of the error amplifier. Used for compensating the switching regulator. 15 PWGD Open collector Power Good signal. 16 VID4 5-Bit DAC input, MSB. 17 VID3 5-Bit DAC input. 18 VID2 5-Bit DAC input. 19 VID1 5-Bit DAC input. 20 VID0 5-Bit DAC input, LSB. 21 G3 Gate drive pin for the external N-MOS of the 2.5V linear regulator. 22 SNS3 Feedback pin for the 2.5V linear regulator. 23 EN Output Enable. A logic low shuts the whole chip down. 24 HG High side N-FET gate driver output. Linear Section — The two linear regulator controllers feature wide control bandwidth, N-FET and NPN transistor driving capability, an adjustable output voltage and a typical 2% tolerance. The wide control bandwidth makes meeting the GTL+ bus transient response requirement an easy job. When no external resistor divider is used, the two controllers default to 1.5V and 2.5V respectively. Both linear sections have under-voltage latch-off. Should the output voltage drop below 0.63V, the corresponding gate drive will be disabled and PWGD pin will be pulled low. Applications Information OVERVIEW The LM2637 provides control and protection for three voltage regulators. Namely, a synchronous buck switching controller and two linear regulator controllers that drive an external N-FET or NPN transistor. Switching Section — The switching controller features a VRM-compatible, 5-bit programmable output voltage, over-current and over-voltage protection, under-voltage latch-off, a power good signal, and an output enable. The 5-bit DAC has a typical tolerance of 1%. There are two user-selectable over-current protection methods. One provides accurate over-current protection with the use of an external sense resistor. The other saves cost by taking advantage of the rDS_ON of the high-side FET. The over-voltage protection provides two levels of protection. The first turns off the high-side FET and turns on the low-side. The second provides a gate signal that can be used to fire an external SCR. The PWM frequency is adjustable from 50 kHz to beyond 1 MHz through an external resistor. Soft start is realized through an internal digital counter. No external soft start capacitor is necessary. Dynamic positioning of the switcher output voltage reduces the number of output capacitors and can be easily realized using the same sense resistor as the over-current protection. www.national.com THEORY OF OPERATION Start Up Switching Section — The soft start circuitry starts to work when three conditions are met, i.e., EN pin is a logic high, the VID code is valid and VCC pin voltage exceeds 4.2V. The duration of the soft start is determined by an internal digital counter and the switching frequency. During soft start, the output of the error amplifier is allowed to increase gradually. When the counter has counted 4,096 clock cycles, soft start session ends and the output level of the error amplifier is released and allowed to go to a value that is determined by the feedback loop. PWRGD pin is always low during soft start and is turned over to output voltage monitoring circuitry after that. Before VCC reaches 4V, all internal logic is in a power-on-reset state and the two FET drivers are disabled. 8 Applications Information The LM2637 gate drives are of BiCMOS design. Unlike some bipolar control ICs, the gate drive has rail-to-rail swing that ensures no spurious turn-on due to capacitive coupling. Another feature of the FET gate drives is the adaptive non-overlapping mechanism. A gate drive is not turned on until the other is fully off. The dead time in between is typically 20 ns. This avoids the potential shoot-through problem and helps improve efficiency. (Continued) During normal operation, if VCC voltage drops below 3.6V, the internal circuitry will go into power-on-reset again. The hysteresis helps decrease the noise sensitivity on the VCC pin. After soft start ends and during normal operation, if the converter output voltage exceeds 118% of DAC output voltage, the LM2637 will lock into over-voltage protection mode. The high-side drive will be low, and the low-side drive will be high. There are two ways to clear the mode. One is to cycle VCC voltage once. The other is to toggle the EN level. After the over-voltage protection mode is cleared, the LM2637 will enter the soft start session and start over. Linear Section — The gate drives of the linear section can put out a maximum continuous current of about 40 mA. The typical low gate voltage is 1.2V. Load Transient Response Switching Section — In a typical modern MPU application such as the M II, Pentium II and K6-2 core power supply, load transient response is a critical issue. The LM2637 utilizes the conventional voltage feedback technology as the primary feedback control method. When the load transient happens, the error in the output voltage level is fed to the error amplifier. The output of the error amplifier is then compared with an internally generated PWM ramp signal and the result of the comparison is a series of pulses with certain duty ratios. These pulses are then used to control the on and off of the FET gate drives. In this way, the error in the output voltage gets corrected by the change in the duty ratio of the FET switches. During a large load transient, depending on the compensation design, the change in duty ratio usually begins within one switching cycle. Refer to the Design Considerations section for more details. Besides the voltage feedback control loop, the LM2637 also has a pair of fast comparators (the MIN and MAX comparators) to help maintain the output voltage during a large and fast load transient. The trip points of the comparators are set to ± 5% of the DAC output voltage. When the load transient is so large that the output voltage goes outside the ± 5% window, the MIN or MAX comparator will bypass the primary voltage control loop and immediately set the duty ratio to either 100% or 0%. This provides the fastest possible way to react to such a large load transient in a conventional buck converter. Linear Section — The linear section does not go through a soft start. Whenever the soft start of the switching section begins, the linear section immediately applies the required gate voltages or base currents for external power transistors. There is an under-voltage latch-off for the linear section. If after soft start ends, SNS2 or SNS3 is below 0.63V, the corresponding gate drive will be disabled and PWGD pin will be pulled low. Normal Operation Switching Section — In the normal operation mode, the LM2637 regulates the converter output voltage by adjusting the duty ratio. The output voltage is determined by the 5-bit VID code set by the user or MPU. The PWM frequency is set by an external resistor between FREQ pin and ground. The resistance needed for a desired PWM frequency can be determined by the following equation: (1) For example, if the desired PWM frequency is 300 kHz, the resistance should be around 84 kΩ. The minimum allowable PWM frequency is 5 kHz. Linear Section — Under steady state operation, the linear section supplies the appropriate gate voltage or base current to correctly bias the external pass transistor so that the voltage drop across the transistor is the right value. Linear Section — The linear section has a high control bandwidth. Depending on external components selected, the typical bandwidth can be as high as 1.2 MHz. The user may choose to lower this bandwidth and have a better noise immunity by adding a small capacitor (1 nF to 10 nF) between the gate output and ground. Resetting the LM2637 When the LM2637 detects an abnormal condition such as switching regulator over voltage, it will latch itself off partially or completely. To reset the LM2637, either EN or VCC voltage has to be toggled. Another more subtle way to recover is to float all the VID pins and reapply the correct code. Power Good Signal The power good signal is to indicate whether all three output voltages are within their corresponding range. The range for the switching regulator is set to a typical ± 10% window of the DAC output voltage. The range for the linear regulator is 0.63V to infinity. During soft start, the power good signal is kept low. At the completion of soft start, all three output voltages are checked and the PWGD pin will be asserted if they are all within specified range. During normal operation, whenever a voltage goes out of the specified range for more than about 3 µs, PWGD pin will be pulled low. Gate Drives Switching Section — The switching controller has two gate drives that are suitable for driving external power N-FETs in a synchronous buck topology. The voltage for the two FET drivers is supplied by the VDD pin. This VDD voltage should be at least one VGS(th) higher than converter input voltage to be able to fully enhance the high-side FET. In a typical PC motherboard application, it is recommended that 12V be applied to VDD, and 5V be used as the input voltage for the switcher. A charge pump is not recommended since the linear sections need a stable VDD voltage to minimize high frequency noise. For a VDD of 12V, the peak gate charging current is typically 2A, and the peak gate discharging current is typically 6A, well suited for high speed switching. Over-Voltage Protection Switching Section — When the output voltage exceeds 118% of the DAC output voltage any time beyond the soft start, the switching section will enter over-voltage protection mode and shuts itself down. The upper gate drive will be held low while the lower gate drive will be held high. PWGD 9 www.national.com Applications Information (Continued) will be low. There will also be a logic high signal at the OVP pin that can be used to fire an external SCR. To clear this mode, refer to the Resetting the LM2637 section. Linear Section — There is no over-voltage protection in the linear controllers. Under-Voltage Latch-Off At the completion of soft start, the controller starts to monitor all three output voltages. If any of the voltages goes below about 0.63V, the controller will latch off its corresponding section, i.e., switching or linear. The mode can be cleared by following the procedures described in the Resetting the LM2637 section. DS100848-8 FIGURE 4. Current Limit via High-Side FET VDS Sensing Current Limit Switching Section — Current limit can be realized by two methods. One method is through sensing the VDS of the high-side FET. The other is through a separate sense resistor. The first method is cheaper and more power efficient but less accurate. The second method is more accurate but dissipates additional power and is either more expensive or requires special PCB layout consideration. A side benefit of the second method is it enables implementation of a technique called dynamic voltage positioning, which helps save the number of output capacitors. The LM2637 tells in which current limit mode it is supposed to be by detecting the CS+ pin voltage. When CS+ voltage is 1.2V below VCC voltage, sense resistor method is assumed. Otherwise the VDS method is chosen. The VDS method is based on typical rDS_ON of the high-side FET and load current levels. Method 1 — High-Side FET VDS Sensing This method detects the high-side FET drain current by sensing its drain-source voltage when it is on. See Figure 4. Since the rDS_ON of a FET is a known value, current through the FET can be known by measuring its VDS. The relationship between the three parameters is: Notice however, that the rDS_ON of the FET has a positive temperature coefficient and it can increase by as much as 50% when heated up. Also the distribution of the rDS_ON can be fairly wide, a 1.25 to 1.5 ratio is not uncommon. Consult the MOSFET vendor for further information on the distribution of rDS_ON. The designer should carefully choose the value of RIMAX so that even under the extreme case (largest rDS_ON and highest temperature) the current limit will not trigger below the preset value. To provide the greatest protection over the high-side FET, cycle-by-cycle protection is implemented. The sampling of the VDS starts as early as 250 ns after the FET is turned on. Whenever an over-current condition is detected, the high-side FET is immediately turned off and the low-side FET turned on. This status remains for the rest of the cycle. The same procedure applies to the next switching cycle. The blanking time of 250 ns is to avoid the switching noise that occurs whenever the FET is turned on. The resistor between CS− pin and the switching node (source of the high-side FET) is important for minimizing the noise and negative voltage present at the CS− pin. A resistance of 100Ω to 300Ω is recommended. Method 2 — Current Sense Resistor This method uses a sense resistor in series with the output inductor to detect the load current. SeeFigure 5. The voltage across the sense resistor is proportional to load current. In the case that the sense resistor is of discrete type (i.e., not a PCB etch resistor) or the sense resistor value is optimized for dynamic voltage positioning (see the Dynamic Positioning of Load Voltage section), it may be necessary to use two signal level resistors, R1 and R2 to appropriately set the desired current limit. (2) To implement the current limit function, an external resistor RIMAX is needed. The resistor should be connected between the drain of the high-side FET and IMAX pin. A constant current of around 180 µA is forced to flow into the IMAX pin and causes a fixed voltage drop across the RIMAX resistor. This voltage drop is then compared with the VDS of the high-side FET and if the latter is higher, over current is assumed. The appropriate value of RIMAX for a pre-determined current limit level ILIM can be determined by the following equation: (3) For example, suppose that the rDS_ON of the FET is 20 mΩ, and the desired current limit is 20A, then RIMAX should be 2.2 kΩ. www.national.com 10 Applications Information buck regulator that needs to meet stringent load transient requirement such as that of processor core voltage supply, a 2-pole-1-zero compensation network should suffice, such as the one shown in Figure 6 (C1, C2, R1 and R2). This is because the ESR zero of the typical output capacitors is low enough to make the control-to-output transfer function a single-pole roll-off. As an example, let us figure out the values of the compensation network components in Figure 6. Assume the following parameters: R = 20Ω, RL = 20 mΩ, RC = 9 mΩ, L = 2 µH, C = 7.5 mF, VIN = 5V, Vm = 2V and PWM frequency = 300 kHz. Notice RL is the sum of the inductor DC resistance and the on resistance of the FET’s. The control-to-output transfer function is: (Continued) (5) The ESR zero frequency is: (6) The double pole frequency is: DS100848-9 FIGURE 5. Current Limit via Current Sense Resistor For a given current limit value, the minimum RSENSE is determined by: (7) The corresponding Bode plots are shown in Figure 7. Notice since the ESR zero frequency is so low that the phase doesn’t even go beyond −90˚. This makes the compensation easier to do. Since the DC gain and cutoff frequency (0 dB frequency) are too low, some compensation is needed. Otherwise the low DC gain will cause a poor line regulation, and the low cutoff frequency may hurt transient response performance. The transfer function for the 2-pole-1-zero compensation network shown in Figure 6 is: (4) where VOCP is the over-current trip voltage and is typically 55 mV, see the Electrical Characteristic table. For example, for a 20A current limit, the minimum RSENSE is 2.75 mΩ. If a 3 mΩ sense resistor is used instead, use appropriate values of R1 and R2 to make the voltage across R1 to be VOCP when the voltage across RSENSE is 60 mV. The discrete current sense resistor usually has a very good temperature coefficient and tolerance. A temperature coefficient of ± 30 ppm/˚C is typical. Tolerance is usually ± 1% or ± 5%. Vishay Dale and IRC offer a broad range of discrete sense resistors. A PCB etch resistor can also be used as the RSENSE. The advantage of that approach is flexible resistance, which will result in minimum power loss. R1 and R2 may also be eliminated. The drawback is too high a temperature coefficient, typically +4000 ppm/˚C, which will result in a much less accurate current limit than a discrete sense resistor. The copper thickness of a PCB is usually of 5% tolerance. (8) where (9) One of the poles is located at origin to help achieve the highest DC gain. So there are three parameters to determine, the position of the zero, the position of the second pole, and the constant A. To determine the cutoff frequency and phase margin, the loop bode plots need to be generated. The loop transfer function is: TF = −TF1 x TF2 (10) By choosing the zero close to the double pole position and the second pole to half of the switching frequency, the closed loop transfer function turns out to be very good. Linear Section — There is no current limit function in the linear controllers. However, if there is ever a severe over-load, the output voltage may drop below 0.63V, in which case the under-voltage latch-off will provide the protection. DESIGN CONSIDERATIONS Control Loop Compensation Switching Section — A switching regulator should be properly compensated to achieve a stable operation, tight regulation and good dynamic performance. For a synchronous 11 www.national.com Applications Information (Continued) That is, if fz = 1.32 kHz, fp = 153 kHz, and A = 4.8 x 10−6 ΩF, then the cutoff frequency will be 50 kHz, the phase margin will be 72˚, and the DC gain will be that of the error amplifier. See Figure 8. The compensation network component values can be determined by Equation (9), since the values of fz, fp and A are now known. To more conveniently calculate the values, Equation (9) can be rearranged as follows: (11) Notice there are three equations but four variables. So one of the variables can be chosen arbitrarily. Since the current driving capability of the error amplifier is limited to around 3 mA, it is a good idea to have a high impedance path from EAO to FB. From Equation (11) it can be told that a larger R2 will result in a smaller C1, C2 and a larger R1. Calculations show that the following combination is a good one: R2 = 51Ω, C1 = 0.022 µf, R1 = 5.6 kΩ, C2 = 820 pF. DS100848-18 FIGURE 7. Control-to-Output Bode Plots DS100848-17 FIGURE 6. Buck Converter from a Control Viewpoint For a different application or different type of output capacitors, a different compensation scheme may be necessary. The user can either follow the steps above to figure the appropriate component values or contact National for help. DS100848-19 FIGURE 8. Loop Bode Plots Linear Section — The linear section is designed for high control bandwidth operation. The phase margin and cutoff frequency depends on the external N-FET, output capacitors and their ESR. As a rule of thumb, the designer can choose any capacitance from 50 µF to 4000 µF, with a total ESR of 10 mΩ to 100 mΩ. The larger the capacitance, the lower the bandwidth. The above capacitors usually result in a control bandwidth of 250 kHz to 1.2 MHz. www.national.com 12 Applications Information thermal capacity and cost that limits the selection. As an example, consider a 3.3V to 1.5V, 4A application. The lowest input-output differential voltage is 3.3V x 95% –1.5V x 102% = 1.605V, so the maximum allowable rDS_ON is 1.605V ÷ 4A = 401 mΩ. Almost all low voltage discrete N-FET’s can meet this requirement. However, the maximum power dissipation on the FET is (3.3V x 105% –1.5V x 98%) x 4A = 8W. At least a TO-220 package with a beefy heat sink is necessary to handle the thermal dissipation. When there is a load transient requirement such as that of the GTL+ supply, make sure the rDS_ON is much lower than the value calculated from steady state operation because headroom is important for transient performance. (Continued) FET Selection Switching Section — The selection of FET switches affects both the efficiency of the whole converter and the current limit setting (if VDS sensing mode is selected). From efficiency standpoint it is suggested that for the high-side switch, only logic level FETs be used. Standard FETs can be used for the low-side switch when 12V is used to power the VDD pin. The power loss associated with the FETs is two-fold — Ohmic loss and switching loss. The Ohmic loss is relatively easy to calculate whereas the switching loss is much more difficult to estimate. The switching loss in a synchronous buck converter usually happens only in the high-side FET. When the high-side FET starts to turn on, inductor current is flowing in the low-side body diode. Since the body diode undergoes a reverse recovery before forced off, the high-side FET will experience a pulse of drain current turn on. The simultaneous presence of high drain-source voltage and high drain current in the high-side FET causes the switching loss. Apparently the switching loss is proportional to the PWM frequency. Having a Schottky diode in parallel with the low-side body diode will to a large extent alleviate the problem. This is because a Schottky diode does not undergo a reverse recovery and it has a lower forward voltage than the body diode so it will take the majority of the inductor current after the low-side FET is turned off. The low-side FET benefits from what is called zero voltage switching (ZVS). That is because every time just before the low-side FET is turned on, inductor current is already flowing in its body diode, resulting in a low drain-source voltage. When the low-side FET is turned off, current will be shifted to its body diode temporarily, again clamping the drain-source voltage to a low value. It is difficult to calculate the switching loss due to its complicated nature. Fortunately at a reasonable PWM frequency such as 300 kHz, the switching loss is usually much less than the Ohmic loss. So the designer may initially ignore the switching loss when trying to meet an efficiency specification. The Ohmic loss for the high-side FET is: Capacitor Selection Switching Section — Output Capacitors. The selection of capacitors is an extremely important step when designing a converter for a load such as the MPU core. Since the typical slew rate of the load current during a large load transient is around 20 A/µs to 30 A/µs, the switching converter has to rely on the output capacitors to take care of the first few microseconds. Under such a current slew rate, ESR of the output capacitors is more of a concern than the ESL in terms of voltage excursion. Depending on the kind of capacitors being used, total output capacitance value may or may not be an important factor. When the output capacitance is too low, the converter may have to have a small output inductor to quickly supply current to the output capacitors when the load suddenly kicks in and to quickly stop supplying current when the load is suddenly removed. Multilayer ceramic (MLC) capacitors can have very low ESR but also a low capacitance value compared to other kinds of capacitors. Low ESR aluminum electrolytic capacitors tend to have large sizes and capacitance. Tantalum electrolytic capacitors can have a fairly low ESR with a much smaller size and capacitance than the aluminum capacitors. Certain OSCON capacitors present ultra low ESR and long life span. By the time the total ESR of the output capacitor bank reaches around 9 mΩ, the capacitance of the aluminum/tantalum/OSCON capacitors is usually already in the millifarad range. For those capacitors, ESR is the only factor to consider. MLCs can have the same amount of total ESR with much less capacitance, most probably under 100 µF. A very small inductor, ultra fast control loop and a high switching frequency become necessary in such a case to deal with the fast charging/discharging rate of the output capacitor bank. From a cost savings standpoint, aluminum electrolytic capacitors are the most popular choice for output capacitors. They have reasonably long life span and they tend to have hugh capacitance to withstand the charging or discharging process during a load transient for a fairly long period. Sanyo MV-GX and MV-DX series’ give good performance when enough of the capacitors are paralleled. The 6MV1500GX capacitor has a typical ESR of 44 mΩ and a capacitance of 1500 µF at a voltage rating of 6.3V. For a detailed procedure for determining number of output capacitors, refer to the application note Using Dynamic Voltage Positioning Technique to Reduce the Cost of Output Capacitors in Advanced Microprocessor Power Supplies and the associated spreadsheet for automated design. (12) The Ohmic loss for the low-side FET is: (13) Notice when determining the rDS_ON, the gate-source voltages are usually different for the two FET’s. For the high-side FET, VGS is VDD minus drain voltage. For the low-side, VGS is VDD. This means the low-side FET may present a lower rDS_ON when the same type of FET is used for both switches. Since the rDS_ON has a positive temperature coefficient, the actual Ohmic loss may be somewhat higher than calculated. The power supply designer may target 125˚C FET operating temperature under maximum load and highest ambient temperature and then use the corresponding rDS_ON found in the FET datasheet. Linear Section — Two things need to be considered, i.e., rDS_ON and thermal capacity. Make sure that the maximum possible rDS_ON on the N-FET is lower than the lowest input-output differential voltage divided by maximum load current. In a typical motherboard 3.3V to 1.5V or 3.3V to 2.5V application, this is not an issue because the maximum allowable rDS_ON is way higher than a typical N-FET. It is the Input Capacitors. The challenge on input capacitors is the RMS ripple current. The large ripple current drawn by the high-side switch tends to generate quite some heat due to the capacitor ESR. The RMS ripple current ratings in the capacitor catalogs are usually specified under 105˚C. In the 13 www.national.com Applications Information where Vo_rip is the peak-peak output ripple voltage, f is the switching frequency. For commonly used low rDS_ON FET’s, a reasonable switching frequency is 300 kHz. Assume a peak-peak output ripple voltage is 18 mV, the total output capacitor ESR is 9 mΩ, the input voltage is 5V, and output voltage is 2.8V, then the inductance value according to the above equation will be 2 µH. The highest slew rate of the inductor current when the load changes from no load to full load can be determined as follows: (Continued) case of desktop PC applications, those ratings seem somewhat conservative. A rule-of-thumb is increase the 105˚C rating by 70% for desktop PC applications. The input RMS ripple current value can be determined by the following equation: (14) and the power loss in each input capacitor is: (17) where DMAX is the maximum allowed duty cycle, which is around 0.95 for LM2637. For a load transient from 0A to 14A, the highest current slew rate of the inductor, according to the above equation, is 0.97 A/µs, and therefore the shortest possible total recovery time is 14A/(0.97 A/µs) = 14.5 µs. Notice that output voltage starts to recover whenever the inductor starts to supply current. The highest slew rate of the inductor current when the load changes from full load to no load can be determined from the same equation but use DMIN instead of DMAX. Since the DMIN of LM2637 is at 0%, the slew rate is therefore −1.4 A/µs. So the approximate total recovery time will be 14A/(1.4 A/µs) = 10 µs. Often times the power supply designer may have to use a custom-made inductor for best performance/price ratio. Micrometals offers cost effective iron powder cores that are widely adopted by motherboard supplies and OEMs. One important rule when designing an iron power inductor is never saturate the core or else it will exhibit extremely poor dynamic performance. Useful inductor design tools can also be found on their web page, www.micrometals.com. The user of LM2637 can also contact National for a custom-made inductor. Alternatively the designer may use an open core inductor, which is lower cost due to its ease of mass production. However, the open magnetic field may cause some noise problems to nearby circuitry and may cause EMI issues. However, no negative reports have been heard so far. Coilcraft (www.coilcraft.com) offers a wide range of open core inductors. Custom-made parts are also possible. Other than low cost, the advantages of open core inductors are less board space and superior dynamic performance. Input Inductor. The input inductor is for limiting the input current slew rate during a load transient and normal operation. In the case that low ESR aluminum electrolytic capacitors are used for the input capacitor bank, input capacitor voltage change due to capacitor charging/discharging is usually negligible for the first 20 µs. ESR is by far the dominant factor in determining the amount of capacitor voltage undershoot/overshoot during a fast load transient. So the worst case is when the load changes between no load and full load. Under that condition the input inductor sees the highest voltage change across the input capacitors. Assume the input capacitor bank consists of three 16MV820GX, i.e., a total ESR of 15 mΩ. Whenever there is a sudden load change, the change in input current has to be initially supported by the input capacitor bank instead of the input inductor. So for a fast load-swing between 0A and 14A, the voltage change seen by the input inductor is a ramp from 0V to a ∆V or vice versa, whereas ∆V = 14A x 15 mΩ = 210 mV. So this situation is just as bad as operating under heaviest load. Use the following equation to determine the minimum inductance value: (15) In the case of 333 MHz Pentium II power supply, the maximum output current is around 14A. Under the worst case when duty cycle is 50%, the maximum input capacitor RMS ripple current is half of output current, i.e., 7A. Therefore three Sanyo 16MV820GX capacitors are necessary under room temperature (they are rated 1.45A at 105˚C). The maximum ESR of those capacitors is 44 mΩ. So the maximum power loss in each of them is less than (7A)2 x 44 mΩ/32 = 0.24W. Note that the power loss in each capacitor is inversely proportional to the square of the total number of capacitors, which means the power loss in each capacitor quickly drops when the number of capacitors increases. Linear Section — For applications where there is a load transient requirement such as that the GTL+ supply, low ESR capacitors should be considered. Make sure that the total ESR multiplied by the maximum load current is smaller than half the output voltage regulation window. The output voltage regulation window should exclude the tolerance of LM2637. For example, for a 3.3V to 1.5V, 2A design, the initial regulation window is ± 9%. Assume the tolerance of the LM2637 plus margin is ± 2%, then the effective window left is ± 7% or ± 105 mV. Therefore the ESR should be less than 105 mV ÷ 2A = 52 mΩ. A Sanyo 6MV1200DX is sufficient. For applications where the load is static and for control bandwidth and stability issue, refer to the guidelines in the control loop compensation section. Inductor Selection Output Inductor. The size of the output inductor is determined by a number of parameters. Basically the larger the inductor, the smaller the output ripple voltage, but the slower the converter’s response speed during a load transient. On the other hand, a smaller inductor requires higher switching frequency to maintain the same level of output ripple, and probably results in a lossier converter, but has less inertia responding to load transient. In the case of MPU core power supply, fast recovery of the load voltage from transient window back to the steady state window is important. That limits the highest inductance value that can be used. The lowest inductance value is limited by the highest switching frequency that can be practically employed. As the switching frequency increases, the switching loss in the FETs tends to increase, resulting in lower overall efficiency and larger heat sinks. A good switching frequency is probably a frequency under which the FET conduction loss is much higher than the switching loss because the cost of the FET is directly related to its rDS_ON. The inductor size can be determined by the following equation: (16) www.national.com 14 Applications Information a resistor can be connected between the FB pin and ground to increase the no-load output voltage to close to the upper limit of the window. (Continued) (18) where (di/dt)max is the maximum allowable input current slew rate, which is 0.1 A/µs in the case of Pentium II power supply and ∆V is equal to maximum load current times input capacitor ESR. So the input inductor size, according to the above equation, should be 2.1 µH. Dynamic Positioning of Load Voltage The following is just a quick overview of a technique called dynamic voltage positioning. For a detailed explanation and examples please refer to our application note Using Dynamic Voltage Positioning Technique to Reduce the Cost of Output Capacitors in Advanced Microprocessor Power Supplies. An associated spreadsheet is also available for automated design. Since the typical MPU core voltage’s steady state regulation window is fairly large, it is a good idea to dynamically position the steady state output voltage in the steady state regulation window with respect to load current level so that the output voltage has more headroom for load transient response. This needs load current information. There are at least two simple ways to implement this idea with LM2637. One is to utilize the output inductor DC resistance, see Figure 9. The average voltage across the output inductor is actually that across its DC resistance, which is proportional to load current. Since the switching node voltage VA toggles between the input voltage and ground at the switching frequency, it is impossible to choose node A as the feedback point, otherwise the dynamic performance will suffer and the system may have noise problems. Using a low pass filter network around the inductor, such as the one shown in the figure, seems to be a good idea. The feedback point is node C. DS100848-28 FIGURE 10. Dynamic Voltage Positioning by Using a Stand-Alone Resistor A possible drawback of the scheme in Figure 9 is slow transient recovery speed. Since the 5 kΩ resistor and the 0.1 µF capacitor have a large time constant, the settling of node C to its steady state value during a load transient may take a few milliseconds. Depends on the interaction between the compensation network and the 0.1 µF capacitor, VCORE may take different routes to reach its steady state value. This is undesired when the load transient happens more than 1000 times per second. Reducing the time constant will result in a more fluctuating VC, due to a less effective low pass filter. Fine tuning the parameters may generate an acceptable design. Another way to implement the dynamic voltage ppsitioning is through the use of a separate resistor, such as the 4 mΩ resistor in Figure 10 above. The advantage of this implementation over the previous one is a much faster recovery speed of VCORE from transient level to steady state level. A fine-tuned compensation network will give good response as shown in Figure 11. The disadvantage is additional power loss. The total power loss can be 0.78W at 14A of load current. The cost of the resistor can be minimized by using a PCB etch resistor. DS100848-27 FIGURE 9. Dynamic Voltage Positioning by Utilizing Output Inductor DC Resistance Since at switching frequency the impedance of the 0.1 µF is much less than 5 kΩ, so the toggling voltage at node A will mainly drop across the 5 kΩ resistor and node C will be much quieter than A. However, VCB average is still the majority of VAB average, because of the ratio of the resistor divider. So in steady state VC = IO x rL + VCORE, where rL is the inductor DC resistance. So at no load, output voltage is equal to VC, and at full load, output voltage is IO x rL lower than VC. To further utilize the steady state regulation window, DS100848-29 FIGURE 11. Load Transient Response with DVP: 0A to 14A, ESR = 9.4 mΩ, Droop Resistor = 4 mΩ PCB Layout Considerations There are several points to consider. 15 www.national.com Applications Information 5. (Continued) 1. Try to use 2 oz. copper for the ground plane if tight load regulation is desired. In the case of dynamic voltage positioning, this may not be a concern because the loose load regulation is desired anyway. However, do not forget to take into consideration the voltage drop caused by the ground plane when calculating dynamic voltage positioning parameters. 2. Try to keep gate drive traces short. However, do not make them too short or else the LM2637 may be placed too close to the FETs and get heated up by them. For the same reason, do not use wide traces, 10 mil traces should be enough. 3. When not employing dynamic voltage positioning, place the feedback point at the VRM connector pins so as to have a tight load regulation. If it is an embedded power supply, place the feedback point at Slot I connector or wherever closest to the MPU. 4. Start component placement with the power devices such as FETs, and inductors. www.national.com 6. 7. Do not place the LM2637 directly underneath the FETs (on the other side of the PCB) when surface mount FETs are used. Also try to avoid staying too close to the output inductor, especially when using an open core inductor. If possible, keep the capacitors some distance away from the inductors and FET heatsinks so that the capacitors will have a better thermal environment. Keep in mind that the input capacitors are usually much hotter than output capacitors. When implementing dynamic voltage positioning through a PCB trace, keep in mind that the PCB trace is a heat source and try to avoid placing the trace directly underneath the LM2637. 8. Try to place a ceramic capacitor as close as possible to the VDD pin. 9. If it is a MPU core supply, try to place the output bulk capacitors fairly close to the MPU for lower inductance. 16 inches (millimeters) unless otherwise noted 24-Lead Small Outline Package Order Number LM2637M NS Package Number M24B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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LM2637 Motherboard Power Supply Solution with a 5-Bit Programmable Switching Controller and Two Linear Regulator Controllers Physical Dimensions