LM4681 10 Watt Stereo CLASS D Audio Power Amplifier with Stereo Headphone Amplifier and I2C/SPI Volume Control General Description Key Specifications The LM4681 is a fully integrated single supply, CLASS D audio power amplifier solution. The LM4681 utilizes a proprietary balanced pulse-width modulation technique that lowers output noise and THD and improves PSRR when compared to conventional pulse width modulators. The LM4681 also features a stereo headphone amplifier that delivers 80mW into a 32Ω headset with less than 0.5% THD. The LM4681’s I2C/SPI (selectable) volume control has a +30dB to –48dB range when speakers are driven and a range of +13dB to –65dB when headphones are connected. All amplifiers are protected by thermal shutdown. Additionally, the high efficiency power amplifiers have output current limit. With a 8Ω load, the IC’s efficiency for a 6W power level is 85%. The IC features click and pop reduction circuitry that minimizes audible popping during device turn-on and turnoff. The LM4681 is available in a 48-lead LLP package, ideal for portable and desktop computer applications. n n n n n n PO at THD+N =10%, AV = 30dB, VDD = 14V 10W (typ) THD+N at 1kHz at 1W into 8Ω (Power Amp) 0.43% (typ) Efficiency at 7W into 8Ω 85% (min) Total quiescent power supply current 50mA (typ) THD+N 1kHz, 20mW, 32Ω (Headphone) 0.02% (typ) Single supply range 9.0V to 15.5V Features n n n n n n Pulse-width modulator. I2C/SPI (selectable) volume control Stereo headphone amplifier. “Click and pop” suppression circuitry. Micropower shutdown mode. 48 lead LLP package (No heatsink required). Applications n Flat Panel Displays n Televisions n Multimedia Monitors Block Diagram 20118922 Block Diagram for LM4681 BOOMER™ is a trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201189 www.national.com LM4681 10 Watt Stereo CLASS D Audio Power Amplifier with Stereo Headphone Amplifier and I2C/SPI Volume Control March 2006 LM4681 Connection Diagram LLP Package 20118917 Top View Order Number LM4681SQ See NS Package Number SQA048AA (LLP Package) www.national.com 2 Figure 1. Typical Application 20118918 LM4681 3 www.national.com LM4681 Absolute Maximum Ratings (Note 2) LLP Package Vapor Phase (60 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 16V Input Voltage TMIN ≤ TA ≤ TMAX −40˚C ≤ TA ≤ +85˚C 9V ≤ VDD ≤ 15.5V Supply Voltage 2000V ESD Susceptibility (Note 5) Thermal Resistance (LLP Package) 200V 150˚C θJA 28˚C/W −65˚C ≤ TA ≤ 150˚C θJC 20˚C/W Junction Temperature (Note 6) Storage Temperature Temperature Range Internally Limited ESD Susceptibility(Note 4) 220˚C Operating Ratings (Notes 1, 2) −0.3V to VDD +0.3V Power Dissipation (Note 3) 215˚C Infrared (15 sec.) Soldering Information Electrical Characteristics (Notes 1, 2, 7) The following specifications apply for VDD = 12V, I2CVDD = 5V, RL = 8Ω, LC filter values as shown in Figure 1, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4681 Units Typical Limit 12 15.5 9 V (max) V (min) VDD Operating Supply Voltage Range IS Quiescent Power Supply Current, Class D Mode VIN = 0VRMS, VHPSEL = 0V 50 70 mA (max) IS Quiescent Power Supply Current, Headphone Mode VIN = 0VRMS, VHPSEL = VDD 22 30 mA (max) ISD Quiescent Power Supply Current, Shutdown Mode VSD = 5V 0.1 RIN Input Resistance in Both Modes I2CVDD I2C / SPI Logic Supply Voltage VIH Minimum High Level Input Voltage mA 8 I2C/SPI Interface pins kΩ 5.5 3 V (max) V (min) 0.7 x I2CVDD V (min) 0.3 x I2CVDD V (max) VIL Maximum Low Level Input Voltage VHPIH HP Sense High Input Voltage VDD – 1 V (min) VHPIL HP Sense Low Input Voltage VDD/2 V (max) 5.3 W (min) Power Amplifiers PO Maximum Output Power, Per Channel PD1 Power Dissipation THD+N ≤ 1%, fIN = 1kHz 6.0 THD+N ≤ 10%, VDD = 14V, fIN = 1kHz 10 W PO = 6W/Chan, fIN = 1kHz 1.17 W EFF1 Efficiency PO = 6W/Chan, fIN = 1kHz 85 % THD+N Harmonic Distortion + Noise PO = 1W/Chan, fIN = 1kHz 0.11 % Output Noise Voltage RSOURCE = 50Ω, CIN = 1µF, BW = 8Hz to 22kHz, A-weighted, input referred 10 µV VNOISE www.national.com 4 (Continued) The following specifications apply for VDD = 12V, I2CVDD = 5V, RL = 8Ω, LC filter values as shown in Figure 1, unless otherwise specified. Limits apply for TA = 25˚C. Symbol PSRR Parameter Power Supply Rejection Ratio Conditions VRIPPLE = 200mVP-P, CBYPASS1 = 10µF, input referred f = 50Hz f = 60Hz f = 100Hz f = 120Hz f = 1kHz LM4681 Typical Limit 82 84 92 95 95 Units dB Headphone Amplifiers PO Maximum Power Output Per Channel THD+N ≤ 1%, RL = 32Ω, fIN = 1kHz THD+N Distortion + Noise PO = 20mW, RL = 32Ω, fIN = 1kHz VNOISE Output Noise Voltage, RMS PSRR Power Supply Rejection Ratio (Referred to Input) 94 70 mW (min) 0.02 % RIN = 50Ω, CIN = 1µF, BW = 20Hz to 20kHz, RL = 32Ω A-weighted, Input referred 22 µV 200mV, 1kHz, VIN = 0, RL = 32Ω 77 dB Electrical Characteristics for Volume Control (Notes 1, 2) The following specifications apply for VDD = 12V. Limits apply for TA = 25˚C. LM4681 Symbol CRANGE AM Parameter Gain Range Mute Gain Conditions Units (Limits ) Typical (Note 8) Limit (Note 7) Digital Code = Full Scale, No Load Power Amplifier Headphone Amplifier 30 13 29 12 dB (min) dB (min) Digital Code = +1LSB, No Load Power Amplifier Headphone Amplifier –48 –65 –46 –63 dB (min) dB (min) Digital Code = 0, No Load Power Amplifier Headphone Amplifier –76 –74 –74 dB (max) dB (max) Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. “Operating Ratings” indicate conditions for which the device is functional, but do not guarantee specific performance limits. “Electrical Characteristics” state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: For operating at case temperatures above 25˚C, the device must be derated based on a 150˚C maximum junction temperature and a thermal resistance of θJA = 80˚C/W (junction to ambient). Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 5: Machine Model 220pF − 240pF discharged through all pins. Note 6: The operating junction temperature maximum is 150˚C. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Typicals are measured at 25˚C and represent the parametric norm. 5 www.national.com LM4681 Electrical Characteristics (Notes 1, 2, 7) LM4681 I2C/SPI Interface Controls B7 B6 B5 B4 B3 B2 B1 B0 I2C Address 1 1 0 1 1 0 ADR 0 Mode Control Register 0 X 0 X X X 0 Mute Active 0 Shutdown Active Volume Control Register (See Table 4 ) 1 0 0 V4 V3 V2 V1 V0 Headphone Control HP Sense Pin (HPSEL, pin 22) Output Stage Configuration 0 Class D Amps Active 1 (VDD) Class D Amps inactive Logic Controls Logic Level (SEL, pin 21) I2C/SPI Select 0 I2C mode 1 SPI mode www.national.com 6 LM4681 Typical Performance Characteristics (Volume control at maximum, unless otherwise stated.) Class D Amplifier THD+N vs Frequency VDD = 12V, RL = 8Ω, PO = 1W Class D Amplifier THD+N vs Frequency VDD = 9V, RL = 8Ω, PO = 1W 20118936 20118969 Class AB Headphone Amplifier THD+N vs Frequency VDD = 9V, RL = 32Ω, PO = 20mW Class D Amplifier THD+N vs Frequency VDD = 15.5V, RL = 8Ω, PO = 1W 20118970 20118939 Class AB Headphone Amplifier THD+N vs Frequency VDD = 15.5V, RL = 32Ω, PO = 20mW Class AB Headphone Amplifier THD+N vs Frequency VDD = 12V, RL = 32Ω, PO = 20mW 20118940 20118941 7 www.national.com LM4681 Typical Performance Characteristics (Continued) Class D Amplifier THD+N vs Output Power VDD = 9V, RL = 8Ω Both channel driven, both measured Class D Amplifier THD+N vs Output Power VDD = 12V, RL = 8Ω Both channel driven, both measured 20118942 20118943 Class D Amplifier THD+N vs Output Power VDD = 15.5V, RL = 8Ω Both channel driven, both measured Class AB Headphone Amplifier THD+N vs Output Power VDD = 9V, RL = 32Ω 20118944 20118945 Class AB Headphone Amplifier THD+N vs Output Power VDD = 15.5V, RL = 32Ω Class AB Headphone Amplifier THD+N vs Output Power VDD = 12V, RL = 32Ω 20118947 20118946 www.national.com 8 (Continued) Class AB Headphone Amplifier Output Power vs Supply Voltage Class D Amplifier Output Power vs Supply Voltage 20118972 20118971 Class D Amplifier Magnitude vs Frequency VDD = 9V, RL = 8Ω, PO = 1W Class D Amplifier Magnitude vs Frequency VDD = 12V, RL = 8Ω, PO = 1W 20118950 20118951 Class AB Headphone Amplifier Magnitude vs Frequency VDD = 9V, RL = 32Ω, PO = 20mW Class D Amplifier Magnitude vs Frequency VDD = 15.5V, RL = 8Ω, PO = 1W 20118952 20118953 9 www.national.com LM4681 Typical Performance Characteristics LM4681 Typical Performance Characteristics (Continued) Class AB Headphone Amplifier Magnitude vs Frequency VDD = 12V, RL = 32Ω, PO = 20mW Class AB Headphone Amplifier Magnitude vs Frequency VDD = 15.5V, RL = 32Ω, PO = 20mW 20118954 20118955 PSRR vs Frequency VDD = 12V PSRR vs Frequency VDD = 9V 20118956 20118957 Class D Amplifier Dissipation vs Load Dissipation VDD = 9V, RL = 8Ω Both channels driven and measured PSRR vs Frequency VDD = 15.5V 20118958 20118959 www.national.com 10 (Continued) Class D Amplifier Dissipation vs Load Dissipation VDD = 12V, RL = 8Ω Both channels driven and measured Class D Amplifier Dissipation vs Load Dissipation VDD = 15.5V, RL = 8Ω Both channels driven and measured 20118960 20118961 Class D Amplifier Efficiency vs Total Output Power VDD = 12V, RL = 8Ω Both channels driven and measured Class D Amplifier Efficiency vs Total Output Power VDD = 9V, RL = 8Ω Both channels driven and measured 20118962 20118963 Output Power vs Load Resistance VDD = 9V, Upper curve = 10% THD+N, Lower curve = 1% THD+N Class D Amplifier Efficiency vs Total Output Power VDD = 15.5V, RL = 8Ω Both channels driven and measured 20118965 20118964 11 www.national.com LM4681 Typical Performance Characteristics LM4681 Typical Performance Characteristics (Continued) Output Power vs Load Resistance VDD = 12V, Upper curve = 10% THD+N, Lower curve = 1% THD+N Output Power vs Load Resistance VDD = 15.5V, Upper curve = 10% THD+N, Lower curve = 1% THD+N 20118966 20118967 Power Supply Current vs Power Supply Voltage 20118973 www.national.com 12 SYSTEM FUNCTIONAL INFORMATION Modulation Technique Unlike typical Class D amplifiers that use single-ended comparators to generate a pulse-width modulated switching waveform and RC timing circuits to set the switching frequency, the LM4681 uses a balanced differential floating modulator. Oscillation is a result of injecting complimentary currents onto the respective plates of a floating, on-die capacitor. The value of the floating capacitor and value of the components in the modulator’s feedback network set the nominal switching frequency at 450kHz. Modulation results from imbalances in the injected currents. The amount of current imbalance is directly proportional to the applied input signal’s magnitude and frequency. Using a balanced, floating modulator produces a Class D amplifier that is immune to common mode noise sources such as substrate noise. This noise occurs because of the high frequency, high current switching in the amplifier’s output stage. The LM4681 is immune to this type of noise because the modulator, the components that set its switching frequency, and even the load all float with respect to ground. The balanced modulator’s pulse width modulated output drives the gates of the LM4681’s H-bridge configured output power MOSFETs. The pulse-train present at the power MOSFETs’ output is applied to an LC low pass filter that removes the 450kHz energy component. The filter’s output signal, which is applied to the driven load, is an amplified replica of the audio input signal. Under Voltage Proctection The under voltage protection disables the output driver section of the LM4681 while the supply voltage is below 8V. This condition may occur as power is first applied or during low line conditions, changes in load resistance, or when power supply sag occurs. The under voltage protection ensures that all of the LM4681’s power MOSFETs are off. This action eliminates shoot-through current and minimizes output transients during turn-on and turn-off. The under voltage protection gives the digital logic time to stabilize into known states, further minimizing turn output transients. Power Supply Sequencing To ensure best performance, please observe the following power-up sequence. The I2CVDD supply voltage should be applied first. Do not send any data to the LM4681’s internal registers until the VDD is applied. This takes advantage of the LM4681’s power-on reset, which activates the amplifier’s shutdown and mute. Once I2CVDD is applied, apply the VDD supply voltage. Prior to removing the two supply voltages, activate shutdown and mute. Turn-On Time The LM4681 has an internal timer that determines the amplifier’s turn-on time. After power is first applied or the part returns from shutdown, the nominal turn-on time is 600ms. This delay allows all externally applied capacitors to charge to a final value of VDD/2. Further, during turn-on, the outputs are muted. This minimizes output transients that may occur while the part settles into is quiescent operating mode. Shutdown Function The LM4681’s digitally controlled shutdown function allows the user to place the amplifier in a shutdown mode while the system power supply remains active. Activating shutdown deactivates the output switching waveform and minimizes the quiescent current. Through the SPI/I2C digital interface, the Mode control register’s Bit 0 is used to control the LM4681’s shutdown function. A logic “0” activates shutdown, whereas a logic “1” returns the amplifier to its operational quiescent state. When the power supply voltage is first applied, the LM4681 is operating in the shutdown mode. For more information on the digital interface, see the section titled “SPI/I2C Serial Digital Interface.” Output Stage Current Limit and Fault Detection Protection The output stage MOSFETs are protected against output conditions that could otherwise compromise their operational status. The first stage of protection is output current limiting. When conditions that require high currents to drive a load, the LM4681’s current limit circuitry clamps the output current at a nominal value of 2.5A. The output waveform is present, but may be clipped or its amplitude reduced. The same 2.5A nominal current limit also occurs if the amplifier outputs are shorted together or either output is shorted to VDD or GND. The second stage of protection is an onboard fault detection circuit that continuously monitors the signal on each output MOSFET’s gate and compares it against the respective drain voltage. When a condition is detected that violates a MOSFET’s Safe Operating Area (SOA), the drive signal is disconnected from the output MOSFETs’ gates. The fault detect circuit maintains this protective condition for approximately 600ms, at which time the drive signal is reconnected. If the fault condition is no longer present, normal operation resumes. If the fault condition remains, however, the drive signal is again disconnected. Mute Function The LM4681’s digitally-controlled mute function allows the user to place the amplifier outputs in a muted mode while the amplifier’s analog input signals remain active. Activating mute internally removes the analog input signal from the Class D and headphone amplifier inputs. While muted, the amplifier inputs and outputs retain their VDD/2 operational bias. Through the SPI/I2C digital interface, the Mode control register’s Bit 1 is used to control the LM4681’s audio mute function. A logic “0” activates mute, whereas a logic “1” deactivates mute. When the power supply voltage is first applied, the LM4681’s headphone and Class D amplifier outputs are muted. More information on the digital interface is found in the section titled “SPI/I2C Serial Digital Interface.” Stereo Headphone Amplifier The LM4681’s stereo headphone amplifier operates continuously, even while the Class D amplifiers are active. When using headphones to listen to program material, it is usually 13 www.national.com LM4681 desirable to stop driving external speakers. This is easily achieved by using the active low HPSEL input. As shown in typical application schematic in Figure 1, with no headphones connected to the headphone jack the input voltage applied to the HPSEL pin is a logic low. In this state, the Class D amplifiers are active and able to drive external speakers. When headphones are plugged into the headphone jack, the switch internal to the jack is opened. This changes the voltage applied to the HPSEL pin to a logic high, shutting off the LM4681’s Class D amplifiers. General Features LM4681 General Features The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is high. (Continued) Thermal Protection The LM4681 has thermal shutdown circuitry that monitors the die temperature. Once the LM4681 die temperature reaches 170˚C, the LM4681 disables the output switching waveform and remains disabled until the die temperature falls below 140˚C (typ). After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM4681 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4681. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high. Over-Modulation Protection The LM4681’s over-modulation protection is a result of the preamplifier’s (AMP1 and AMP2, Figure 1) inability to produce signal magnitudes that equal the power supply voltages. Since the preamplifier’s output magnitude will always be less than the supply voltage, the duty cycle of the amplifier’s switching output will never reach zero. Peak modulation is limited to a nominal 95%. After the data byte is sent, the master must check for another acknowledge to see if the LM4681 received the data. If the master has more data bytes to send to the LM4681, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The data line should be held high when not in use. I2C Compatible Interface The LM4681 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4681. The I2C address for the LM4681 is determined using the ADR pin. The LM4681’s two possible I2C chip addresses are of the form 110110X10 (binary), where X1 = 0, if ADR is logic low, and X1 = 1, if ADR is a logic high. If the I2C interface is used to address a number of chips in a system, the LM4681’s chip address can be changed to avoid possible address conflicts. The bus format for the I2C interface is shown in Figure 5. The bus format diagram is broken up into six major sections: SPI Interface The LM4681’s serial control interface is compatible with SPI signals and protocols. When using SPI signals, the ADR pin is the input for the SPI ENABLE signal, the SDA pin is the input for the SPI CLOCK signal, and the SDA pin is the SPI DATA input. I2C/SPI Interface Power Supply Pin (I2C VDD) The LM4681’s I2C/SPI interface is powered up through the I2C/SPI VDD pin. The LM4681’s I2C/SPI interface operates at a voltage level set by the I2C/SPI VDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C/SPI interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. www.national.com 14 LM4681 General Features (Continued) I2C Timing Diagrams 20118919 FIGURE 1. I2C Bus Format 20118920 FIGURE 2. I2C Timing Diagram SPI Timing Diagram 20118921 FIGURE 3. the rising edge of CLK. Also, any transition on DATA must occur at least 50ns (tDH) after the rising edge of CLK and stabilize before the next rising edge of CLK. 5. ENABLE should be logic-low only during serial data transmission. 6. ENABLE must be logic-low at least 50ns (tES ) before the first rising edge of CLK, and ENABLE has to remain logiclow at least 50ns (tEH ) after the eighth rising edge of CLK. 7. If ENABLE remains logic-high for more than 50ns before all 8 bits are transmitted then the data latch will be aborted. SPI Operational Requirements 1. The maximum clock rate is 5MHz for the CLK pin. 2. CLK must remain logic-high for at least 100ns (tCH ) after the rising edge of CLK, and CLK must remain logic-low for at least 100ns (tCL ) after the falling edge of CLK. 3. Data bits are written to the DATA pin with the most significant bit (MSB) first. 4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 50ns (tDS) before 15 www.national.com LM4681 General Features transmission, the falling edge of CLK must occur at least 50ns (tCS ) before ENABLE transitions to logic-low for the next set of data. (Continued) 8. If ENABLE is logic-low for more than 8 CLK pulses then only the first 8 data bits will be latched and activated at rising edge of eighth CLK. 9. ENABLE must remain logic-high for at least 50ns (tEL ). Volume Control The internal Stereo Volume Control is set by changing bits 0 through 4 in the SPI interface, as shown in table 3 below. 10. Coincidental rising or falling edges of CLK and ENABLE are not allowed. If CLK is to be held logic-high after the data TABLE 1. Volume Control Settings Gain (dB) HP Outputs Class D Outputs Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 –64.94 –48.03 0 0 0 0 0 –64.94 –48.03 0 0 0 0 1 –56.94 –36.03 0 0 0 1 0 –47.94 –31.03 0 0 0 1 1 –42.94 –26.03 0 0 1 0 0 –37.94 –21.03 0 0 1 0 1 –33.94 –17.03 0 0 1 1 0 –31.94 –15.03 0 0 1 1 1 –28.94 –12.03 0 1 0 0 0 –25.94 –9.03 0 1 0 0 1 –22.94 –6.03 0 1 0 1 0 –20.94 –4.03 0 1 0 1 1 –18.94 –2.03 0 1 1 0 0 –16.94 –0.03 0 1 1 0 1 –14.94 1.97 0 1 1 1 0 –12.94 3.97 0 1 1 1 1 –10.94 5.97 1 0 0 0 0 –8.94 7.97 1 0 0 0 1 –6.94 9.97 1 0 0 1 0 –4.94 11.97 1 0 0 1 1 –2.94 13.97 1 0 1 0 0 –0.94 15.97 1 0 1 0 1 1.06 17.97 1 0 1 1 0 3.06 19.97 1 0 1 1 1 6.06 22.97 1 1 0 0 0 7.07 23.97 1 1 0 0 1 8.06 24.97 1 1 0 1 0 9.06 25.97 1 1 0 1 1 10.06 26.97 1 1 1 0 0 11.06 27.97 1 1 1 0 1 12.06 28.97 1 1 1 1 0 13.06 29.97 1 1 1 1 1 www.national.com 16 SUPPLY BYPASSING Correct power supply bypassing has two important goals. The first is to reduce noise on the power supply lines and minimize deleterious effects that the noise may cause to the amplifier’s operation. The second is to help stabilize an unregulated power supply and to improve the supply’s transient response under heavy current demands. These two goals require different capacitor value ranges. Therefore, various types and values are recommended for supply bypassing. For noise de-coupling, generally small ceramic capacitors (0.01µF to 0.1µF) are recommended. Larger value (1µF to 10µF) tantalum capacitors are needed for the transient current demands. These two capacitors in parallel will do an adequate job of removing most noise from the supply rails and providing the necessary transient current. These capacitors should be placed as close as possible to each IC’s supply pin(s) using leads as short as possible. The LM4681 has two different set of VDD pins: a set for power VDD (PVDD) and a set for signal VDD (SVDD). The parallel combination of the low value ceramic (0.1µF) and high value tantalum (10µF) should be used to bypass the PVDD pin. A small value (0.1µF) ceramic or tantalum can be used to bypass the SVDD pin. THD+N MEASUREMENTS AND OUT OF AUDIO BAND NOISE THD+N (Total Harmonic Distortion plus Noise) is a very important parameter by which all audio amplifiers are measured. Often it is shown as a graph where either the output power or frequency is changed over the operating range. A very important variable in the measurement of THD+N is the bandwidth-limiting filter at the input of the test equipment. Class D amplifiers, by design, switch their output power devices at a much higher frequency than the accepted audio range (20Hz - 20kHz). Alternately switching the output voltage between VDD and GND allows the LM4681 to operate at much higher efficiency than that achieved by traditional Class AB amplifiers. Switching the outputs at high frequency also increases the out-of-band noise. Under normal circumstances the output lowpass filter significantly reduces this out-of-band noise. If the low pass filter is not optimized for a given switching frequency, there can be significant increase in out-of-band noise. THD+N measurements can be significantly affected by out-of-band noise, resulting in a higher than expected THD+N measurement. To achieve a more accurate measurement of THD, the test equipment’s input bandwidth of the must be limited. Some common upper filter points are 22kHz, 30kHz, and 80kHz. The input filter limits the noise component of the THD+N measurement to a smaller bandwidth resulting in a more real-world THD+N value. OUTPUT STAGE FILTERING The LM4681 requires a low pass filter connected between the amplifier’s bridge output and the load. Figure 1 shows the recommended LC filter. A minimum value of 27µH is recommended. As shown in Figure 1, using the values of the 17 www.national.com LM4681 components connected between the amplifier BTL outputs and the load achieves a 2nd-order lowpass filter response with a -3dB cutoff frequency of 25kHz. Application Hints LM4681 Revision History www.national.com Rev Date Description 1.0 2/09/06 Initial release. 1.1 2/10/06 Edited the PSRR Typical values in the Elect. Char table. 1.2 3/08/06 Did few texts (Gen Desc section) clean-up, then re-released D/S to the WEB. 1.3 3/17/06 Changed the typo under PSRR (Conditions-Vripple from 20mVp-p to 200mVp-p) in the EC Char table, then re-released D/S to the WEB (per KH). 18 inches (millimeters) unless otherwise noted Order Number LM4681SQ NS Package Number SQA048AA National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 LM4681 10 Watt Stereo CLASS D Audio Power Amplifier with Stereo Headphone Amplifier and I2C/SPI Volume Control Physical Dimensions