MM54C240/MM74C240 Inverting MM54C244/MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATEÉ Outputs General Description Features These octal buffers and line drivers are monolithic complementary MOS (CMOS) integrated circuits with TRI-STATE outputs. These outputs have been specially designed to drive highly capacitive loads such as bus-oriented systems. These devices have a fan out of 6 low power Schottky loads. A high logic level on the output disable control input G makes the outputs go into the high impedance state. For improved TTL input compatibility see MM74C941. Y Y Y Y Y Y Y Y Y Wide supply voltage range (3V to 15V) High noise immunity (0.45 VCC typ) Low power consumption High capacitive load drive capability TRI-STATE outputs Input protection TTL compatibility 20-pin dual-in-line package High speed 25 ns (typ.) @ 10V, 50 pF (MM74C244) Logic and Connection Diagrams MM54C240/MM74C240 MM54C240/MM74C240 Dual-In-Line Package TL/F/5905 – 2 TL/F/5905 – 1 Top View Order Number MM54C240 or MM74C240 MM54C244/MM74C244 Dual-In-Line Package MM54C244/MM74C244 TL/F/5905 – 4 TL/F/5905 – 3 Top View Order Number MM54C244 or MM74C244 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/5905 RRD-B30M105/Printed in U. S. A. MM54C240/MM74C240 Inverting, MM54C244/MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATE Outputs February 1988 Absolute Maximum Ratings (Note 1) Voltage at Any Pin b 0.3V to VCC a 0.3V Operating Temperature Range MM54C240, MM54C244 MM74C240, MM74C244 b 65§ C to a 150§ C Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Operating VCC Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 3V to 15V 18V 260§ C Absolute Maximum VCC Lead Temperature (Soldering, 10 seconds) DC Electrical Characteristics Min/Max limits apply across temperature range, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V 3.5 8.0 VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V, IO e 10 mA VCC e 10V, IO e 10 mA IOZ TRI-STATE Output Current VCC e 10V, OD e VIH IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V, VIN e 0V ICC Supply Current VCC e 15V V V 1.5 2.0 4.5 9.0 V V 0.005 b 1.0 V V 0.5 1.0 V V g 10 mA 1.0 b 0.005 0.05 mA mA 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e 4.5V, IO e b450 mA 74C, VCC e 4.75V, IO e b450 mA VCC b 0.4 VCC b 0.4 V V 54C, VCC e 4.5V, IO e b2.2 mA 74C, VCC e 4.75V, IO e b2.2 mA 2.4 2.4 V V VOUT(0) Logical ‘‘0’’ Output Voltage VCC b 1.5 VCC b 1.5 V V 0.8 0.8 54C, VCC e 4.5V, IO e 2.2 mA 74C, VCC e 4.75V, IO e 2.2 mA 0.4 0.4 V V V V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISINK Output Source Current (P-Channel) Output Sink Current (N-Channel) VCC e 5V, VOUT e 0V TA e 25§ C b 14 b 30 mA VCC e 10V, VOUT e 0V TA e 25§ C b 36 b 70 mA VCC e 5V, VOUT e VCC TA e 25§ C 12 20 mA VCC e 10V, VOUT e VCC TA e 25§ C 48 70 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise specified Symbol tPD(1), tPD(0) Parameter Propagation Delay (Data In to Out) MM54C240/MM74C240 MM54C244/MM74C244 t1H, t0H Conditions Min Typ Max Units VCC VCC VCC VCC e e e e 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF 60 40 80 60 90 70 110 90 ns ns ns ns VCC VCC VCC VCC e e e e 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF 45 25 60 40 70 50 90 70 ns ns ns ns Propagation Delay Output Disable to High Impedance State (from a Logic Level) RL e 1k, CL e 50 pF VCC e 5V VCC e 10V 45 35 80 60 ns ns Propagation Delay Output Disable to Logic Level (from High Impedance State) RL e 1k, CL e 50 pF VCC e 5V VCC e 10V 50 30 90 60 ns ns tT(HL), tT(LH) Transition Time VCC VCC VCC VCC 45 30 75 50 80 60 140 100 ns ns ns ns CPD Power Dissipation Capacitance (Output Enabled per Buffer) MM54C240/MM74C240 MM54C244/MM74C244 (Note 3) tH1, tH0 e e e e 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF (Output Disabled per Buffer) MM54C240/MM74C240 MM54C244/MM74C244 100 100 pF pF 10 0 pF pF CIN Input Capacitance (Any Input) VIN e 0V, f e 1 MHz, TA e 25§ C 10 pF CO Output Capacitance (Output Disabled) VIN e 0V, f e 1 MHz, TA e 25§ C 10 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note, AN-90. Typical Application TL/F/5905 – 5 3 Truth Tables MM54C240/MM74C240 ODA IA OA ODB IB OB 1 1 0 0 X X 0 1 Z Z 1 0 1 1 0 0 X X 0 1 Z Z 1 0 MM54C244/MM74C244 ODA IA OA ODB IB OB 1 1 0 0 X X 0 1 Z Z 0 1 1 1 0 0 X X 0 1 Z Z 0 1 1 e High 0 e Low X e Don’t Care Z e TRI-STATE Typical Performance Characteristics N-Channel Output Drive at 25§ C P-Channel Output Drive at 25§ C TL/F/5905 – 7 TL/F/5905 – 6 MM54C240/MM74C240 Propagation Delay vs. Load Capacitance MM54C244/MM74C244 Propagation Delay vs. Load Capacitance TL/F/5905 – 8 TL/F/5905 – 9 4 AC Test Circuits and Switching Time Waveforms tpd0, tpd1 CMOS to CMOS TL/F/5905–10 TL/F/5905 – 11 t1H and tH1 t1H tH1 TL/F/5905–12 TL/F/5905 – 13 Note: VOH is defined as the DC output high voltage when the device is loaded with a 1 kX resistor to ground. t0H and tH0 t0H tH0 TL/F/5905–14 TL/F/5905 – 15 Note: VOL is defined as the DC output low voltage when the device is loaded with a 1 kX resistor to VCC. Note: Delays measured with input tr, tf s 20 ns. 5 MM54C240/MM74C240 Inverting, MM54C244/MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATE Outputs Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C240J, MM54C244J, MM74C240J or MM74C244J See NS Package Number J20A Molded Dual-In-Line Package (N) Order Number MM54C240N, MM54C244N, MM74C240N or MM74C244N See NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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