LF6197 160 ns Monolithic Sample-and-Hold Amplifier General Description Features The LF6197 is a monolithic sample-and-hold (S/H) amplifier that uses a proprietary ‘‘current-multiplexed sample-andhold’’ technique to offer extremely high speed while maintaining 12 bits or higher accuracy. The device is built using National’s advanced junction-isolated VIPTM (Vertically Integrated PNP) and BI-FETTM process technologies. The LF6197 acquires a 10V step input to within g 0.01% in 160 ns and has 10 mV hold step error when going from sample to hold mode. The input offset voltage in the sample mode is typically 3 mV. Even at extremely fast acquisition speeds, no compromises are made in the droop rate, which is 0.6 mV/ms. When configured for unity gain, the DC gain error is 0.03%. The feedthrough attenuation in the hold mode is 83 dB at DC and 77 dB at 100 kHz. The LF6197 can be externally configured for either inverting or non-inverting gains, thus offering additional flexibility to the user. The device includes an internal 10 pF hold capacitor. Y Y Y Y Y Key Specifications Y Y Y Y Y Y Y Y and VIPTM Acquisition time (10V step to 0.01%) 160 ns Hold mode settling time (10V step to 0.01%) 50 ns Droop rate 0.6 mV/ms Hold step 10 mV Aperture jitter 8 psrms Feedthrough attenuation at DC 83 dB Small signal bandwidth 25 MHz Applications Y BI-FETTM Operates with supply voltages from g 5V to g 18V CMOS, TTL and ECL compatible logic input Adjustable inverting or non-inverting gain Internal hold capacitor High power-supply rejection in both sample and hold modes are trademarks of National Semiconductor Corporation. Y Y High-speed data acquisition systems Automatic test equipment High-speed instrumentation Replaces expensive hybrid sample-and-hold amplifiers Block Diagram Connection Diagram TL/H/11381 – 2 Top View Ordering Information Industrial (0§ C k TAk a 70§ C) LF6197CCJ Package J14A Ceramic DIP TL/H/11381 – 1 C1995 National Semiconductor Corporation TL/H/11381 RRD-B30M115/Printed in U. S. A. LF6197 160 ns Monolithic Sample-and-Hold Amplifier September 1992 Absolute Maximum Ratings (Notes 1, 2) Positive Supply Voltage (V a ) Negative Supply Voltage (Vb) Analog Input Voltage a 18V Operating Ratings (Notes 1, 2) b 18V V a or Vb or g 12.5V, whichever is less Logic Input to LR1 Differential Voltage g 5V 1.2W (Note 4) Power Dissipation (Note 3) Duration of Output Short Circuit to GND ESD Susceptibility All Pins except Pin 13 (Note 5) Pin 13 only (Note 5) Lead Temperature (Soldering, 10 sec.) J Package Storage Temperature TMIN s TA s TMAX 0§ C s TA s a 70§ C a 4.75V s V a s a 15.75V b 15.75V s V b s b 4.75V Temperature Range LF6197CCJ Positive Supply Voltage Negative Supply Voltage 2000V 1500V 300§ C b 65§ C to a 150§ C Electrical Characteristics Unless otherwise specified, the following specifications apply for V a e a 15V, Vb e b15V, b12V s VIN s a 12V, RL l 1 kX, CL s 40 pF, Logic Reference 2 (LR2) voltage e 0V and Logic Input Voltage k 1.4V threshold, (Unit is in ‘‘sample’’ mode). VS refers to the supply voltages, V a and Vb. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e 25§ C. Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units (Limit) g 3.0 g 6.0 g 3.0 mV (max) mV (max) INPUT CHARACTERISTICS VOS Input Offset Voltage VS e g 5V, (Note 8) DVOS/DT Input Offset Drift 15 mV/§ C RIN, com Input Resistance (common mode) 10 MX RIN, dif Input Resistance (differential) CMRR Common Mode Rejection Ratio IB a Positive Input Bias Current IB b Negative Input Bias Current 300 VCM e g 10V 100 kX 80 dB (min) 7 17 mA (max) 1 7.5 mA (max) TRANSFER CHARACTERISTICS DC Open Loop Gain VOUT e g 12V, RL e 1 kX 70 65 dB (min) DC Open Loop Gain (Note 8) VS e g 5V, VOUT e g 2.5V 55 49 dB (min) 0.003 0.0045 % (max) 25 14 MHz (min) Gain Error (Note 9) Gain Linearity Error fu 0.03 VOUT e g 10V Gain Bandwidth Product % (max) OUTPUT CHARACTERISTICS ROUT Output Resistance 0.02 X SR Slew Rate 145 V/ms Short Circuit Source Current b 63 b 25 mA (min) 70 25 mA (min) Short Circuit Sink Current CL Maximum Capacitive Load No Oscillation 2 200 pF Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for V a e a 15V, Vb e b15V, b12V s VIN s a 12V, RL l 1 kX, CL s 40 pF, Logic Reference 2 (LR2) voltage e 0V and Logic Input Voltage k 1.4V threshold, (Unit is in ‘‘sample’’ mode). VS refers to the supply voltages, V a and Vb. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e 25§ C. Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units (Limit) 240 260 240 260 ns ns (max) ns (max) ns (max) ns (max) SAMPLE/HOLD CHARACTERISTICS tACQ Acquisition Time to 0.1% (Note 10) to 0.01% (Note 10) tAD Aperture Delay Time tAJ Aperture Jitter 10V step a 10V step 130 145 b 10V step 160 4 ns 8 Droop Rate 0.6 psrms 10 mV/ms (max) VHS Hold Step (Note 11) g 10 mV (max) tHMS Hold Mode Settling Time to 0.01% 10V step 50 ns Feedthrough Attenuation (Note 12) f e 1 kHz, VIN e 20 Vp-p f e 100 kHz, VIN e 20 Vp-p 83 77 Total Harmonic Distortion f e 10 kHz, VIN e 20 Vp-p f e 150 kHz, VIN e 20 Vp-p b 83 b 78 dB dB Full Power Bandwidth (Note 13) VIN e 20 Vp– p 2.3 MHz 25 MHz 80 dB (min) dB DYNAMIC CHARACTERISTICS THD FPBW Small Signal Bandwidth DIGITAL LOGIC CHARACTERISTICS VIN(1) Logical ‘‘1’’ Input Voltage 2.0 V (min) VIN(0) Logical ‘‘0’’ Input Voltage 0.8 V (max) Logic Input Current 6 20 mA (max) Logic Reference 2 Input Current 3 5 mA (max) 1.4 1.1 1.6 V(min) V(max) Differential Logic Threshold (Logic Input to LR1) POWER SUPPLY CHARACTERISTICS IS a Positive Supply Current IS a Positive Supply Current 20 30 mA (max) VS e g 5V (Note 8) 18.2 27 mA (max) IS b Negative Supply Current IS b 20 30 mA (max) Negative Supply Current VS e g 5V (Note 8) 17.5 27 mA (max) PSRR Power Supply Rejection Ratio VS e g 12V to g 16V 84 74 dB (min) 3 Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, HJA, and the ambient temperature TA. The maximum allowable power dissipation is PD e (TJmax b TA)/HJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax e 150§ C and iJA e 125§ C/W. The Power Derating Curve shows the safe thermal operating area for this device. Note 4: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150§ C. Note 5: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor. Note 6: Typicals are at TA e 25§ C and represent the most likely parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Operation at g 5V requires that pin 14 be forced to 2.5V. Note 9: Gain error is calculated from the measured open loop gain. Note 10: The acquisition time of the LF6197 has been measured when the device has been configured as an inverting amplifier with a gain of b 1, feedback resistor of 2 kX, feedback capacitor of 1 pF, and a total load resistor of 1 kX. Note 11: Hold step is measured with the LF6197 configured as a unity gain follower and input connected to ground. A TTL pulse with 4 ns rise and fall times is applied to the logic input; the hold step is dependent on the slew rate of the logic input pulse. Note 12: See test circuit, Figure 1 . Note 13: Full power bandwidth is calculated using FPBW e SR/(2qVP); where SR is the measured slew rate and VP is the peak voltage. 4 Typical Performance Characteristics Acquisition Time (to 0.01%) vs Capacitive Load Acquisition Time (to 0.01%) vs Capacitive Load Acquisition Time (to 0.01%) vs Temperature Acquisition Time (to 0.01%) vs Supply Voltage Signal Feedthrough vs Frequency Signal Feedthrough vs Frequency Power Supply Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Common Mode Rejection Ratio vs Frequency Common Mode Rejection Ratio vs Frequency Input Noise Voltage vs Frequency Open Loop Frequency Response TL/H/11381 – 3 5 Typical Performance Characteristics (Continued) Hold Step vs Logic Input Rise Time TL/H/11381 – 15 Power Derating Curve TL/H/11381 – 16 6 Test Circuit TL/H/11381 – 4 FIGURE 1. Circuit configuration for the measurement of feedthrough attenuation. Input is connected to ground in sample mode and is connected to 20 VPP, 100 kHz sine wave in hold mode. Pin Descriptions V a (12) This is the positive power supply pin. A a 5V to a 15V supply voltage should be applied to this pin and bypassed to ground with a 0.1 mF ceramic capacitor in parallel with a 4.7 mF tantalum capacitor. Vb (4) This is the negative power supply pin. A b 5V to b 15V supply voltage should be applied to this pin and bypassed to ground with a 0.1 mF ceramic capacitor in parallel with a 4.7 mF tantalum capacitor. This is the ground reference pin. All signals are referenced to the potential at this pin. GND (9) b Input (1) This is the inverting input of the ‘‘sample’’ amplifier. Connecting this pin through a resistor to the output will configure the sample-and-hold amplifier for unity gain. Other inverting and non-inverting gains can be set by applying the familiar op amp feedback topologies. For stability reasons, stray capacitance from the inverting input to ground should be minimized. a Input (2) This is the non-inverting input of the ‘‘sample’’ amplifier. This pin should be driven from a low impedance source. This is the output of the sample-andhold amplifier. Output (5) LR1 (10) This is the Logic Reference 1 input. By applying the appropriate logic threshold at this pin, the sample-and-hold amplifier’s logic input can be made either CMOS or ECL compatible. For TTL logic levels, this pin should remain unconnected. LR2 (13) This is the Logic Reference 2 input. For TTL logic levels, this pin should be connected to ground; this sets the logic threshold at the logic comparator’s inverting pin at 1.4V. For CMOS or ECL logic levels this pin should either remain unconnected or connected to pin 10. Logic Input (11) This is the logic control input pin. A logic low at this pin will configure the amplifier in the ‘‘sample’’ mode while a logic high will configure the amplifier in the ‘‘hold’’ mode. The TTL, CMOS, or ECL logic compatibility will be determined by the voltage threshold set at the logic comparator’s inverting input. Zener Reference For optimum acquisition and settling Output (14) times, this pin must be bypassed to ground with a 0.01 mF capacitor. Furthermore, for g 5V supply operation, this pin must be biased at 2.5V from a low impedance source. NC (3,6,7,8) No connection. 7 Functional Description booster in the output stage rapidly charges the hold capacitor. A wide-bandwidth amplifier, high-current output stage and fast current-switched hold-to-sample mode selection allows for a slew rate of 145 V/ms and acquisition time of under 200 ns. When there is a change to the Hold mode, switches S2 and S3 are quickly opened and switch S1 is effectively connected to the output of gm2 while input stage gm1 is disconnected. The composite amplifier is now comprised of gm2 and A3 and the loop around the amplifier is closed by the hold capacitor. Note that the opening of switch S3 causes charge injection into the hold capacitor. However, an equal amount of charge is injected into the dummy capacitor due to the opening of a matched switch S2. The net effect is a differential cancellation of charge and thus the pedestal error (hold step) is greatly reduced. Meanwhile, excellent feedthrough attenuation is achieved because the input signal is isolated from the output by the inactive input stage gm1. The LF6197 uses a proprietary ‘‘current-multiplexed sample-and-hold’’ technique as depicted in the simplified block diagram (Figure 2) . The amplifier consists of two transconductance input stages gm1 and gm2 and a common gain and output buffer stage A3. In the sample mode, internal current switching is employed to connect the input stage gm1 to the common output stage A3 while input stage gm2 is disconnected. Additionally, switches S2 and S3 are closed, thereby shorting the internal dummy capacitor and connecting one end of the hold capacitor to a low impedance ground. Although the simplified schematic shows the switches S1 and S2 connected to ground, the switches are in fact connected to a reference potential which appears as a common mode voltage at the two inputs of gm2. For unity gain, the inverting input of gm1 is externally connected to the output through a resistor, thus closing the loop around the amplifier. Conventional op-amp feedback topologies may be employed to configure the amplifier for inverting and non-inverting gains. In the sample mode, a current TL/H/11381 – 5 FIGURE 2. Simplified Block Diagram of LF6197 Sample-and-Hold Amplifier, Connected for Unity Gain and TTL Logic 8 Application Hints cations. Familiar op-amp feedback topologies are employed to configure the LF6197 for non-inverting (Figure 8) or inverting (Figure 9) gains. Note that a feedback resistor of value 1 kX or larger must be used for all gain settings, including non-inverting unity gain. The feedback resistor is required to limit the current through LF6197’s internal clamp diodes when the device is in the hold mode. 1.0 LOGIC CONFIGURATIONS The LF6197 can be configured to interface with TTL, CMOS, or ECL logic. The device is configured for the desired logic using the two Logic Reference pins (LR1 and LR2). 1.1 TTL Logic To configure the device to operate with TTL logic, the LR1 pin should be left open and the LR2 pin should be grounded (Figure 4) . This will set the threshold of the logic comparator at 1.4V. 4.0 POWER SUPPLY SEQUENCING When power supply to the LF6197 is turned on, the negative supply must come on before the positive supply. Meanwhile, when the power supply is turned off, the positive supply must turn off before the negative supply. Improper power supply sequencing may destroy the device. To protect the device against improper power supply sequencing, anti-reversal diodes may be used across the supply pins (Figure 10) . 1.2 CMOS Logic To configure the device to operate with CMOS logic (with a 2.5V threshold at the comparator), several options are available. The LR1 and LR2 pins can be tied together and connected to a 2.5V reference (Figure 5) ; or LR2 can be set to 1.1V with a resistor diode network and LR1 can be bypassed to ground with a 0.01 mF capacitor (Figure 6) . 1.3 ECL Logic To operate with ECL logic (threshold at b1.3V), set LR2 at b 2.7V with a voltage divider from the negative supply and bypass LR1 with a 0.01 mF capacitor (Figure 7) . 2.0 ZENER REFERENCE OUTPUT The LF6197 includes an internal zener diode to bias various sections of the chip. The zener diode output is brought out at pin 14; the voltage at this pin is typically 6.25V when the device is powered from g 15V supplies. For optimum device performance, pin 14 must be bypassed to ground with a 0.01 mF capacitor. If the device is powered from g 5V supplies, then pin 14 must be biased at 2.5V from a low impedance source (Figure 3) . TL/H/11381 – 7 Threshold e 1.4V FIGURE 4. TTL Logic TL/H/11381 – 6 FIGURE 3. Biasing Pin 14 to 2.5V for Operation from g 5V Supplies 3.0 ADJUSTING GAIN The LF6197 allows the user to amplify as well as to sampleand-hold an input signal. This feature eliminates the need for an amplifier preceding the S/H amplifier in many appli- TL/H/11381 – 8 Threshold e 2.5V FIGURE 5. CMOS Logic 9 Application Hints (Continued) TL/H/11381–9 TL/H/11381 – 10 Threshold e 2.5V Threshold e 1.3V FIGURE 6. Another Circuit for CMOS Logic FIGURE 7. ECL Logic TL/H/11381–12 TL/H/11381 – 13 FIGURE 8. LF6197 with Non-Inverting Gain FIGURE 9. LF6197 with Inverting Gain TL/H/11381–11 TL/H/11381 – 14 FIGURE 10. Using Anti-Reversal Diodes to Protect LF6197 from Improper Power Supply Sequencing FIGURE 11. Increasing Linearity to 16 Bits Using a Negative Impedance Load at the Output of LF6197 10 11 LF6197 160 ns Monolithic Sample-and-Hold Amplifier Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number LF6197CCJ NS Package Number J14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.