93L08 Dual 4-Bit Latch General Description The 93L08 is a dual 4-bit D-type latch designed for general purpose storage applications in digital systems. Each latch contains both an active LOW Master Reset input and active LOW Enable inputs. Connection Diagram Logic Symbol Dual-In-Line Package TL/F/9594 – 2 VCC e Pin 24 GND e Pin 12 TL/F/9594 – 1 Order Number 93L08DMQB or 93L08FMQB See NS Package Number J24A or W24C Pin Names ( D0a–D3a D0b–D3b E0a, E1a, E0b, E1b, MRa, MRb Q0a–Q3a Q0b–Q3b ( C1995 National Semiconductor Corporation TL/F/9594 Description Parallel Latch Inputs AND Enable Inputs (Active LOW) Master Reset Inputs (Active LOW) Parallel Latch Outputs RRD-B30M105/Printed in U. S. A. 93L08 Dual 4-Bit Latch June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C MIL b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage Min Nom Max 4.5 5 5.5 Units V 2 V 0.7 V IOH High Level Output Current b 400 IOL Low Level Output Current 4.8 TA Free Air Operating Temperature ts (H) Setup Time HIGH, Dn to En 8 ns th (H) Hold Time HIGH, Dn to En 1 ns ts (L) Setup Time LOW, Dn to En 18 ns th (L) Hold Time LOW, Dn to En 4 ns tw (L) En Pulse Width LOW 32 ns tw (L) MR Pulse Width LOW 30 ns trec Recovery Time, MR to En 10 ns b 55 125 mA mA §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b10 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max, VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V IIL Low Level Input Current VCC e Max, VI e 0.3V IOS Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max (Note 3) Min Units b 1.5 V V 0.3 V 1 mA Inputs 20 Dn 30 Inputs b 400 Dn b 640 b 2.5 Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. 2 Max 2.4 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 3: ICC is measured with all outputs open and all inputs grounded. Typ (Note 1) mA mA b 25 mA 29 mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 3 for waveforms and load configurations) Symbol CL e 15 pF Parameter Min Units Max tPLH tPHL Propagation Delay En to Qn 45 38 ns tPLH tPHL Propagation Delay Dn to Qn 27 29 ns tPHL Propagation Delay MR to Qn 30 Functional Description ns Truth Table Data can be entered into the latch when both of the enable inputs are LOW. As long as this logic condition exists, the output of the latch will follow the input. If either of the enable inputs goes HIGH, the data present in the latch at that time is held in the latch and is no longer affected by data input. The master reset overrides all other input conditions and forces the outputs of all the latches LOW when a LOW signal is applied to the Master Reset input. E0 E1 D Qn Operation H H H MR L L L L L H L H X L L Qnb1 Data Entry Data Entry Hold H H L H H X L H X X X X Qnb1 Qnb1 L Hold Hold Reset Qnb1 e Previous Output State Qn e Present Output State H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Logic Diagram TL/F/9594 – 3 3 93L08 Dual 4-Bit Latch Physical Dimensions inches (millimeters) 24-Lead Ceramic Dual-In-Line Package (J) Order Number 93L08DMQB NS Package Number J24A 24-Lead Ceramic Flat Package (W) Order Number 93L08FMQB NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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