NSC LM5025AMTCX

LM5025A
Active Clamp Voltage Mode PWM Controller
General Description
Features
The LM5025A is a functional variant of the LM5025 active
clamp PWM controller. The functional differences of the
LM5025A are: The CS1 and CS2 current limit thresholds
have been increased to 0.5V. The internal CS2 filter discharge device has been disabled and no longer operates
each clock cycle. The internal VCC and VREF regulators
continue to operate when the line UVLO pin is below threshold.
n Internal Start-up Bias Regulator
n 3A Compound Main Gate Driver
n Programmable Line Under-Voltage Lockout (UVLO) with
Adjustable Hysteresis
n Voltage Mode Control with Feed-Forward
n Adjustable Dual Mode Over-Current Protection
n Programmable Overlap or Deadtime between the Main
and Active Clamp Outputs
n Volt x Second Clamp
n Programmable Soft-start
n Leading Edge Blanking
n Single Resistor Programmable Oscillator
n Oscillator UP / DOWN Sync Capability
n Precision 5V Reference
n Thermal Shutdown
The LM5025A PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp / Reset technique. With the active clamp technique,
higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp
/ reset techniques. Two control outputs are provided, the
main power switch control (OUT_A) and the active clamp
switch control (OUT_B). The two internal compound gate
drivers parallel both MOS and Bipolar devices, providing
superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense
propagation delays less than 100ns. The LM5025A includes
a high-voltage start-up regulator that operates over a wide
input range of 13V to 90V. Additional features include: Line
Under Voltage Lockout (UVLO), softstart, oscillator UP/
DOWN sync capability, precision reference and thermal
shutdown.
Packages
n TSSOP-16
n LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
20107401
Simplified Active Clamp Forward Power Converter
© 2004 National Semiconductor Corporation
DS201074
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LM5025A Active Clamp Voltage Mode PWM Controller
December 2004
LM5025A
Connection Diagram
20107416
16-Lead TSSOP, LLP
Ordering Information
Order Number
Package Type
NSC Package Drawing
Supplied As
LM5025AMTC
TSSOP-16
MTC-16
92 Units per anti-static tube
LM5025AMTCX
TSSOP-16
MTC-16
2500 Units on Tape and Reel
LM5025ASD
LLP-16
SDA-16A
Available Soon
LM5025ASDX
LLP-16
SDA-16A
Available Soon
Pin Description
PIN
NAME
1
VIN
Source Input Voltage
Input to start-up regulator. Input range 13V to 90V,
with transient capability to 105V.
2
RAMP
Modulator ramp signal
An external RC circuit from Vin sets the ramp slope.
This pin is discharged at the conclusion of every
cycle by an internal FET, initiated by either the
internal clock or the V*Sec Clamp comparator.
3
CS1
Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.5V the outputs will go into
Cycle-by-Cycle current limit. CS1 is held low for
50ns after OUT_A switches high providing leading
edge blanking.
4
CS2
Current sense input for soft restart
If CS2 exceeds 0.5V the outputs will be disabled and
a softstart commenced. The soft-start capacitor will
be fully discharged and then released with a pull-up
current of 1µA. After the first output pulse (when SS
=1V), the SS charge current will revert back to 20µA.
5
TIME
Output overlap/Deadtime control
An external resistor (RSET) sets either the overlap
time or dead time for the active clamp output. An
RSET resistor connected between TIME and GND
produces in-phase OUT_A and OUT_B pulses with
overlap. An RSET resistor connected between TIME
and REF produces out-of-phase OUT_A and OUT_B
pulses with deadtime.
6
REF
Precision 5 volt reference output
Maximum output current: 10mA Locally decouple
with a 0.1µF capacitor. Reference stays low until the
VCC UV comparator is satisfied.
7
VCC
Output from the internal high voltage start-up If an auxiliary winding raises the voltage on this pin
regulator. The VCC voltage is regulated to
above the regulation setpoint, the internal start-up
7.6V.
regulator will shutdown, reducing the IC power
dissipation.
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DESCRIPTION
APPLICATION INFORMATION
2
LM5025A
Pin Description
(Continued)
PIN
NAME
8
OUT_A
Main output driver
DESCRIPTION
Output of the main switch PWM output gate driver.
Output capability of 3A peak sink current.
APPLICATION INFORMATION
9
OUT_B
Active Clamp output driver
Output of the Active Clamp switch gate driver.
Capable of 1.25A peak sink current..
10
PGND
Power ground
Connect directly to analog ground.
11
AGND
Analog ground
Connect directly to power ground. For the LLP
package option the exposed pad is electrically
connected to AGND.
12
SS
Soft-start control
An external capacitor and an internal 20µA current
source set the softstart ramp. The SS current source
is reduced to 1uA initially following a CS2
over-current event or an over temperature event.
13
COMP
Input to the Pulse Width Modulator
An internal 5KΩ resistor pull-up is provided on this
pin. The external opto-coupler sinks current from
COMP to control the PWM duty cycle.
14
RT
Oscillator timing resistor pin
An external resistor connected from RT to ground
sets the internal oscillator frequency.
15
SYNC
Oscillator UP/DOWN synchronization input
The internal oscillator can be synchronized to an
external clock with a frequency 20% lower than the
internal oscillator’s free running frequency. There is
no constraint on the maximum sync frequency.
16
UVLO
Line Under-Voltage shutdown
An external voltage divider from the power source
sets the shutdown comparator levels. The
comparator threshold is 2.5V. Hysteresis is set by an
internal current source (20µA) that is switched on or
off as the UVLO pin potential crosses the 2.5V
threshold.
-
EP
Exposed PAD, underside of the LLP package Internally bonded to the die substrate. Connect to
option
GND potential for low thermal impedance.
3
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LM5025A
Block Diagram
Simplified Block Diagram
20107402
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4
Human Body Model
2kV
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
-55˚C to 150˚C
Junction Temperature
150˚C
VIN to GND
-0.3V to 105V
VCC to GND
-0.3V to 16V
Operating Ratings (Note 1)
CS1, CS2 to GND
-0.3 to 1.00V
All other inputs to GND
-0.3 to 7V
VIN Voltage
ESD Rating (Note 2)
13 to 90V
External Voltage Applied to VCC
8 to 15V
Operating Junction Temperature
-40˚C to +125˚C
Electrical Characteristics
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
7.9
Units
Startup Regulator
VCC Reg
I-VIN
VCC Regulation
No Load
7.3
7.6
VCC Current Limit
(Note 4)
20
25
Startup Regulator
Leakage (external Vcc
Supply)
VIN = 100V
165
V
mA
500
µA
VCC Supply
VCC Under-voltage
Lockout Voltage
(positive going Vcc)
VCC Reg 220mV
VCC Reg 120mV
VCC Under-voltage
Hysteresis
1.0
1.5
VCC Supply Current
(ICC)
Cgate = 0
V
2.0
V
4.2
mA
Reference Supply
VREF
Ref Voltage
IREF = 0 mA
Ref Voltage
Regulation
IREF = 0 to 10mA
4.85
Ref Current Limit
10
5
5.15
V
25
50
mV
20
mA
Current Limit
CS1 Prop
CS1 Delay to Output
CS1 Step from 0 to 0.6V
Time to onset of OUT
Transition (90%)
Cgate = 0
40
ns
CS2 Prop
CS2 Delay to Output
CS2 Step from 0 to 0.6V
Time to onset of OUT
Transition (90%)
Cgate = 0
50
ns
Cycle by Cycle
Threshold Voltage
(CS1)
Cycle Skip Threshold
Voltage (CS2)
Resets SS capacitor; auto
restart
Leading Edge
Blanking Time (CS1)
0.45
0.5
0.55
V
0.45
0.5
0.55
V
50
ns
CS1 Sink Impedance
(clocked)
CS1 = 0.4V
30
50
Ω
CS1 Sink Impedance
(Post Fault Discharge)
CS1 = 0.6V
15
30
Ω
5
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LM5025A
Absolute Maximum Ratings (Note 1)
LM5025A
Electrical Characteristics
(Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
CS2 Sink Impedance
(Post Fault Discharge)
CS2 = 0.6V
CS1 and CS2
Leakage Current
CS = CS Threshold 100mV
Min
Typ
Max
Units
55
85
Ω
1
µA
Soft-Start
Soft-start Current
Source Normal
17
22
27
µA
Soft-start Current
Source following a
CS2 event
0.5
1
1.5
µA
Oscillator
Frequency1
TA = 25˚C
TJ = Tlow to Thigh
180
175
200
220
225
kHz
Frequency2
RT = 10.4KΩ
510
580
650
kHz
100
ns
Sync threshold
2
Min Sync Pulse Width
Sync Frequency
Range
V
160
kHz
PWM Comparator
Delay to Output
COMP step 5V to 0V
Time to onset of OUT_A
transition low
40
Duty Cycle Range
0
COMP to PWM Offset
0.7
COMP Open Circuit
Voltage
4.3
COMP Short Circuit
Current
1
ns
80
%
1.3
V
5.9
V
COMP = 0V
0.6
1
1.4
mA
Delta RAMP measured
from onset of OUT_A to
Ramp peak.
COMP = 5V
2.4
2.5
2.6
V
Undervoltage
Shutdown Threshold
2.44
2.5
2.56
V
Undervoltage
Shutdown Hysteresis
16
20
24
µA
10
Ω
Volt x Second Clamp
Ramp Clamp Level
UVLO Shutdown
Output Section
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OUT_A High
Saturation
MOS Device @ Iout =
-10mA,
5
OUTPUT_A Peak
Current Sink
Bipolar Device @ Vcc/2
3
OUT_A Low
Saturation
MOS Device @ Iout =
10mA,
6
A
9
Ω
OUTPUT_A Rise Time
Cgate = 2.2nF
20
ns
OUTPUT_A Fall Time
Cgate = 2.2nF
15
ns
OUT_B High
Saturation
MOS Device @ Iout =
10
-10mA,
6
20
Ω
(Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OUTPUT_B Peak
Current Sink
Bipolar Device @ Vcc/2
1
OUT_B Low
Saturation
MOS Device @ Iout =
10mA,
12
OUTPUT_B Rise Time
Cgate = 1nF
20
ns
OUTPUT_B Fall Time
Cgate = 1nF
15
ns
A
18
Ω
Output Timing Control
Overlap Time
RSET = 38 kΩ connected to
GND, 50% to 50%
transitions
75
105
135
ns
Deadtime
RSET = 29.5 kΩ connected
to REF, 50% to 50%
transitions
75
105
135
ns
Thermal Shutdown
TSD
Thermal Shutdown
Threshold
165
˚C
Thermal Shutdown
Hysteresis
25
˚C
MTC Package
125
˚C/W
SDA Package
32
˚C/W
Thermal Resistance
θJA
Junction to Ambient
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: For detailed information on soldering plastic TSSOP and LLP packages, refer to the Packaging Data Book available from National Semiconductor
Corporation.
Note 3: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25˚C. All hot and cold limits
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 4: Device thermal limitations may limit usable range.
7
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LM5025A
Electrical Characteristics
LM5025A
Typical Performance Characteristics
VCC Regulator Start-up Characteristics, VCC vs Vin
VCC vs ICC
20107403
20107404
VREF vs IREF
Oscillator Frequency vs RT
20107405
20107406
Overlap Time vs Temperature
RSET = 38K
Overlap Time vs RSET
20107407
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20107408
8
LM5025A
Typical Performance Characteristics
(Continued)
Dead Time vs Temperature
RSET = 29.5K
Dead Time vs RSET
20107409
20107410
SS Pin Current vs Temperature
20107411
9
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LM5025A
When the converter auxiliary winding is inactive, external
current draw on the VCC line should be limited so the power
dissipated in the start-up regulator does not exceed the
maximum power dissipation of the controller.
Detailed Operating Description
The LM5025A is a functional variant of the LM5025 active
clamp PWM controller. The functional differences of the
LM5025A are:
An external start-up regulator or other bias rail can be used
instead of the internal start-up regulator by connecting the
VCC and the VIN pins together and feeding the external bias
voltage into the two pins.
The CS1 and CS2 current limit thresholds have been increased to 0.5V.
The internal CS2 filter discharge device has been disabled
and no longer operates each clock cycle.
The internal VCC and VREF regulators continue to operate
when the line UVLO pin is below threshold.
Line Under-Voltage Detector
The LM5025A contains a line Under Voltage Lock Out
(UVLO) circuit. An external set-point voltage divider from Vin
to GND, sets the operational range of the converter. The
divider must be designed such that the voltage at the UVLO
pin will be greater than 2.5V when Vin is in the desired
operating range. If the undervoltage threshold is not met,
both outputs are disabled,all other functions of the controller
remain active. UVLO hysteresis is accomplished with an
internal 20uA current source that is switched on or off into
the impedance of the set-point divider. When the UVLO
threshold is exceeded, the current source is activated to
instantly raise the voltage at the UVLO pin. When the UVLO
pin voltage falls below the 2.5V threshold, the current source
is turned off causing the voltage at the UVLO pin to fall. The
UVLO pin can also be used to implement a remote enable /
disable function. Pulling the UVLO pin below the 2.5V
threshold disables the PWM outputs.
The LM5025A PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp Reset technique. The device can be configured to
control either a P-Channel clamp switch or an N-Channel
clamp switch. With the active clamp technique higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the main
power switch control (OUT_A) and the active clamp switch
control (OUT_B). The active clamp output can be configured
for either a guaranteed overlap time (for P-Channel switch
applications) or a guaranteed dead time (for N_Channel
applications). The two internal compound gate drivers parallel both MOS and Bipolar devices, providing superior gate
drive characteristics. This controller is designed for highspeed operation including an oscillator frequency range up
to 1MHz and total PWM and current sense propagation
delays less than 100ns. The LM5025A includes a highvoltage start-up regulator that operates over a wide input
range of 13V to 90V. Additional features include: Line Under
Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync
capability, precision reference and thermal shutdown.
PWM Outputs
The relative phase of the main (OUT_A) and active clamp
outputs (OUT_B) can be configured for the specific application. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two outputs should be in
phase with the active clamp output overlapping the main
output. For active clamp configurations utilizing a high side
N-Channel switch, the active clamp output should be out of
phase with main output and there should be a dead time
between the two gate drive pulses. A distinguishing feature
of the LM5025A is the ability to accurately configure either
dead time (both off) or overlap time (both on) of the gate
driver outputs. The overlap / deadtime magnitude is controlled by the resistor value connected to the TIME pin of the
controller. The opposite end of the resistor can be connected
to either REF for deadtime control or GND for overlap control. The internal configuration detector senses the connection and configures the phase relationship of the main and
active clamp outputs. The magnitude of the overlap/dead
time can be calculated as follows:
Overlap Time (ns) = 2.8 x RSET - 1.2
Dead Time (ns) = 2.9 x RSET +20
RSET in kΩ, Time in ns
High Voltage Start-Up Regulator
The LM5025A contains an internal high voltage start-up
regulator that allows the input pin (VIN) to be connected
directly to the line voltage. The regulator output is internally
current limited to 20mA. When power is applied, the regulator is enabled and sources current into an external capacitor
connected to the VCC pin. The recommended capacitance
range for the VCC regulator is 0.1µF to 100µF. When the
voltage on the VCC pin reaches the regulation point of 7.6V
and the internal voltage reference (REF) reaches its regulation point of 5V, the controller outputs are enabled. The
outputs will remain enabled until VCC falls below 6.2V or the
line Under Voltage Lock Out detector indicates that VIN is out
of range. In typical applications, an auxiliary transformer
winding is connected through a diode to the VCC pin. This
winding must raise the VCC voltage above 8V to shut off the
internal start-up regulator. Powering VCC from an auxiliary
winding improves efficiency while reducing the controller
power dissipation.
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10
LM5025A
PWM Outputs
(Continued)
20107412
FIGURE 1.
the internal 5V reference and COMP, can be used as the
pull-up for an optocoupler. The comparator polarity is such
that 0V on the COMP pin will produce a zero duty cycle on
both gate driver outputs.
Compound Gate Drivers
The LM5025A contains two unique compound gate drivers,
which parallel both MOS and Bipolar devices to provide high
drive current throughout the entire switching event. The Bipolar device provides most of the drive current capability and
provides a relatively constant sink current which is ideal for
driving large power MOSFETs. As the switching event nears
conclusion and the Bipolar device saturates, the internal
MOS device continues to provide a low impedance to compete the switching event.
During turn-off at the Miller plateau region, typically around
2V - 3V, is where gate driver current capability is needed
most. The resistive characteristics of all MOS gate drivers
are adequate for turn-on since the supply to output voltage
differential is fairly large at the Miller region. During turn-off
however, the voltage differential is small and the current
source characteristic of the Bipolar gate driver is beneficial to
provide fast drive capability.
Volt Second Clamp
The Volt x Second Clamp comparator compares the ramp
signal (RAMP) to a fixed 2.5V reference. By proper selection
of RFF and CFF, the maximum ON time of the main switch
can be set to the desired duration. The ON time set by Volt
x Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged by a resistor connected to Vin while the threshold of the clamp is a fixed
voltage (2.5V). An example will illustrate the use of the Volt x
Second Clamp comparator to achieve a 50% duty cycle limit,
at 200KHz, at a 48V line input: A 50% duty cycle at a 200KHz
requires a 2.5µs of ON time. At 48V input the Volt x Second
product is 120V x µs (48V x 2.5µs). To achieve this clamp
level:
RFF x CFF = VIN x TON / 2.5V
48 x 2.5µ / 2.5 = 48µ
Select CFF = 470pF
RFF = 102kΩ
The recommended capacitor value range for CFF is 100pF
to 1000pF.
The CFF ramp capacitor is discharged at the conclusion of
every cycle by an internal discharge switch controlled by
either the internal clock or by the V x S Clamp comparator,
whichever event occurs first.
Current Limit
The LM5025A contains two modes of over-current protection. If the sense voltage at the CS1 input exceeds 0.5V the
present power cycle is terminated (cycle-by-cycle current
limit). If the sense voltage at the CS2 input exceeds 0.5V, the
controller will terminate the present cycle, discharge the
softstart capacitor and reduce the softstart current source to
1µA. The softstart (SS) capacitor is released after being fully
discharged and slowly charges with a 1µA current source.
When the voltage at the SS pin reaches approximately 1V,
20107413
PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to
the loop error signal (COMP). This comparator is optimized
for speed in order to achieve minimum controllable duty
cycles. The internal 5kΩ pull-up resistor, connected between
11
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LM5025A
Current Limit
b) An external over-current timer can be configured which
trips after a pre-determined over-current time, driving the
CS2 input high, initiating a hiccup event.
(Continued)
the PWM comparator will produce the first output pulse at
OUT_A. After the first pulse occurs, the softstart current
source will revert to the normal 20µA level. Fully discharging
and then slowly charging the SS capacitor protects a continuously over-loaded converter with a low duty cycle hiccup
mode.
c) In a closed loop voltage regulaton system, the COMP
input will rise to saturation when the cycle-by-cycle current
limit is active. An external filter/delay timer and voltage divider can be configured between the COMP pin and the CS2
pin to scale and delay the COMP voltage. If the CS2 pin
voltage reaches 0.5V a hiccup event will initiate.
These two modes of over-current protection allow the user
great flexibility to configure the system behavior in over-load
conditions. If it is desired for the system to act as a current
source during an over-load, then the CS1 cycle-by-cycle
current limiting should be used. In this case the current
sense signal should be applied to the CS1 input and the CS2
input should be grounded. If during an overload condition it is
desired for the system to briefly shutdown, followed by softstart retry, then the CS2 hiccup current limiting mode should
be used. In this case the current sense signal should be
applied to the CS2 input and the CS1 input should be
grounded. This shutdown / soft-start retry will repeat indefinitely while the over-load condition remains. The hiccup
mode will greatly reduce the thermal stresses to the system
during heavy overloads. The cycle-by-cycle mode will have
higher system thermal dissipations during heavy overloads,
but provides the advantage of continuous operation for short
duration overload conditions.
It is possible to utilize both over-current modes concurrently,
whereby slight overload conditions activate the CS1 cycleby-cycle mode while more severe overloading activates the
CS2 hiccup mode. Generally the CS1 input will always be
configured to monitor the main switch FET current each
cycle. The CS2 input can be configured in several different
ways depending upon the system requirements.
a) The CS2 input can also be set to monitor the main switch
FET current except scaled to a higher threshold than CS1
A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic
performance. This same FET remains on an additional 50ns
at the start of each main switch cycle to attenuate the leading
edge spike in the current sense signal. The CS2 discharge
FET only operates following a CS2 event, UVLO and thermal
shutdown.
The LM5025A CS comparators are very fast and may respond to short duration noise pulses. Layout considerations
are critical for the current sense filter and sense resistor. The
capacitor associated with the CS filter must be placed very
close to the device and connected directly to the pins of the
IC (CS and GND). If a current sense transformer is used,
both leads of the transformer secondary should be routed to
the filter network , which should be located close to the IC. If
a sense resistor in the source of the main switch MOSFET is
used for current sensing, a low inductance type of resistor is
required. When designing with a current sense resistor, all of
the noise sensitive low power ground connections should be
connected together near the IC GND and a single connection should be made to the power ground (sense resistor
ground point).
20107414
chronization feature is not required, the SYNC pin should be
connected to GND to prevent any abnormal interference .
The internal oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal
will act directly as the master clock for the controller. Both the
frequency and the maximum duty cycle of the PWM controller can be controlled by the SYNC signal (within the limitations of the Volt x Second Clamp). The maximum duty cycle
(D) will be (1-D) of the SYNC signal.
Oscillator and Sync Capability
The LM5025A oscillator is set by a single external resistor
connected between the RT pin and GND. To set a desired
oscillator frequency (F), the necessary RT resistor can be
calculated from:
RT = (5725/F)1.026
where F is in kHz and RT in kΩ.
The RT resistor should be located very close to the device
and connected directly to the pins of the IC (RT and GND).
A unique feature of LM5025A is the ability to synchronize the
oscillator to an external clock with a frequency that is either
higher or lower than the frequency of the internal oscillator.
The lower frequency sync frequency range is 80% of the free
running internal oscillator frequency. There is no constraint
on the maximum SYNC frequency. A minimum pulse width of
100ns is required for the synchronization clock . If the synwww.national.com
Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to
VIN and GND are required to create the PWM ramp signal.
The slope of the signal at the RAMP pin will vary in proportion to the input line voltage. This varying slope provides line
feedforward information necessary to improve line transient
response with voltage mode control. The RAMP signal is
12
discharged. When the fault condition is no longer present a
softstart sequence will be initiated. Following a second level
current limit detection (CS2), the softstart current source is
reduced to 1µA until the first output pulse is generated by the
PWM comparator. The current source returns to the nominal
20µA level after the first output pulse (~1V at the SS pin).
(Continued)
compared to the error signal at the COMP pin by the pulse
width modulator comparator to control the duty cycle of the
main switch output. The Volt Second Clamp comparator also
monitors the RAMP pin and if the ramp amplitude exceeds
2.5V the present cycle is terminated. The ramp signal is
reset to GND at the end of each cycle by either the internal
clock or the Volt Second comparator, which ever occurs first.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165˚C,
the controller is forced into a low power standby state with
the output drivers and the bias regulator disabled. The device will restart after the thermal hysteresis (typically 25˚C).
During a restart after thermal shutdown, the softstart capacitor will be fully discharged and then charged in the low
current mode (1µA) similar to a second level current limit
event. The thermal protection feature is provided to prevent
catastrophic failures from accidental device overheating.
Soft-start
The softstart feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and surges. At power on, a 20µA current is
sourced out of the softstart pin (SS) into an external capacitor. The capacitor voltage will ramp up slowly and will limit
the COMP pin voltage and therefore the PWM duty cycle. In
the event of a fault as determined by VCC undervoltage, line
undervoltage (UVLO) or second level current limit, the output
gate drivers are disabled and the softstart capacitor is fully
13
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LM5025A
Feed-Forward Ramp
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14
Application Circuit: Input 36-78V, Output 3.3V, 30A
20107417
LM5025A
LM5025A
Physical Dimensions
inches (millimeters)
unless otherwise noted
Molded TSSOP-16
NS Package Number MTC16
Note: It is recommended that the exposed pad be connected to Pin 11 (AGND)
16-Lead LLP Surface Mount Package
NS Package Number SDA16A
15
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LM5025A Active Clamp Voltage Mode PWM Controller
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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