ADC0833 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer General Description Features The ADC0833 series is an 8-bit successive approximation A/D converter with a serial I/O and configurable input multiplexer with 4 channels. The serial I/O is configured to comply with the NSC MICROWIRETM serial data exchange standard for easy interface to the COPSTM family of processors, as well as with standard shift registers or mPs. The 4-channel multiplexer is software configured for singleended or differential inputs when channel assigned by a 4bit serial word. The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Y Y Y Y Y Y Y Y Y Y Y NSC MICROWIRE compatible – direct interface to COPS family processors Easy interface to all microprocessors, or operates ‘‘stand alone’’ Works with 2.5V (LM336) voltage reference No full-scale or zero adjust required Differential analog voltage inputs 4-channel analog multiplexer Shunt regulator allows operation with high voltage supplies 0V to 5V input range with single 5V power supply Remote operation with serial digital data link TTL/MOS input/output compatible 0.3× standard width 14-pin DIP package Key Specifications Y Y Y Y Y Resolution Total Unadjusted Error Single Supply Low Power Conversion Time 8 Bits g (/2 LSB and g 1 LSB 5 VDC 23 mW 32 ms Connection and Functional Diagrams Dual-In-Line Package (J and N) TL/H/5607–14 Top View Order Number ADC0833CCJ, ADC0833BCN or ADC0833CCN See NS Package Number J14A or N14A TL/H/5607 – 1 COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/5607 RRD-B30M115/Printed in U. S. A. ADC0833 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer December 1994 Absolute Maximum Ratings (Notes 1 & 2) Package Dissipation at TA e 25§ C (Board Mount) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Current into V a (Note 3) Supply Voltage, VCC (Note 3) Voltage Logic Inputs Analog Inputs Input Current per Pin (Note 4) Package Input Current (Note 4) Storage Temperature 15 mA 6.5V b 0.3V to VCC a 0.3V b 0.3V to VCC a 0.3V 0.8W Lead Temperature (Soldering, 10 sec.) Dual-In-Line Package (Plastic) Dual-In-Line Package (Ceramic) 260§ C 300§ C ESD Susceptibility (Note 5) 2000V Operating Conditions (Notes 1 & 2) Supply Voltage, VCC Temperature Range ADC0833CCJ ADC0833BCN, ADC0833CCN g 5 mA g 20 mA b 65§ C to a 150§ C 4.5 VDC to 6.3 VDC TMINsTAsTMAX b 40§ C s TA s 85§ C 0§ CsTAs70§ C Electrical Characteristics The following specifications apply for VCC e V a e 5V, fCLK e 250 kHz and VREF/2 s (VCC a 0.1V) unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e Tj e 25§ C. Parameter Typ (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) g (/2 g (/2 g1 g1 Units CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error ADC0833BCN ADC0833CCN ADC0833CCJ VREF/2 Forced to 2.500 VDC g1 LSB LSB LSB Minimum Total Ladder Resistance (Note 9) ADC0833CCJ ADC0833BCN/CCN 7.0 7.0 2.6 2.6 2.6 kX kX Maximum Total Ladder Resistance (Note 9) ADC0833CCJ ADC0833BCN/CCN 7.0 7.0 11.8 10.8 11.8 kX kX GNDb0.05 GNDb0.05 GNDb0.05 V V VCC a 0.05 VCC a 0.05 VCC a 0.05 V V Minimum Common-Mode Input Range (Note 10) ADC0833CCJ ADC0833BCN/CCN All MUX Inputs and COM Input Maximum Common-Mode Input Range (Note 10) ADC0833CCJ ADC0833BCN/CCN All MUX Inputs and COM Input DC Common-Mode Error ADC0833CCJ ADC0833BCN/CCN Change In Zero Error From VCC e 5V To Internal Zener Operation (Note 3) ADC0833CCJ ADC0833BCN/CCN g (/16 g (/4 g (/16 g (/4 g (/4 LSB LSB 1 1 1 LSB LSB 15mA Into V a VCC e N.C. VREF/2 e 2.500V 2 Electrical Characteristics The following specifications apply for VCC e V a e 5V, fCLK e 250 kHz and VREF/2 s (VCC a 0.1V) unless otherwise specified. Boldface limits apply from tMIN to tMAX; all other limits TA e Tj e 25§ C. (Continued) Parameter Typ (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) 6.3 6.3 6.3 V V 8.5 8.5 8.5 V V g (/4 LSB LSB Units CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) VZ, Minimum Internal Diode Breakdown (At V a ) (Note 3) ADC0833CCJ ADC0833BCN/CCN 15mA Into V a VZ, Maximum Internal Diode Breakdown (At V a ) (Note 3) ADC0833CCJ ADC0833BCN/CCN 15mA Into V a Power Supply Sensitivity ADC0833CCJ ADC0833BCN/CCN VCC e 5V g 5% IOFF, Off Channel Leakage Current (Note 11) ADC0833CCJ On Channel e 5V, Off Channel e 0V g (/16 g (/4 g (/16 g (/4 b1 b 200 ADC0833BCN/CCN b1 b 200 mA nA mA nA On Channel e 0V, Off Channel e 5V ADC0833CCJ 1 200 ADC0833BCN/CCN 1 200 ION, On Channel Leakage Current (Note 11) ADC083CCJ mA nA mA nA On Channel e 5V, Off Channel e 0V 1 200 ADC0833BCN/CCN 1 200 mA nA mA nA On Channel e 0V, Off Channel e 5V ADC083CCJ b1 b 200 ADC0833BCN/CCN b1 b 200 mA nA mA nA DIGITAL AND DC CHARACTERISTICS VIN(1), Logical ‘‘1’’ Input Voltage ADC0833CCJ ADC0833BCN/CCN VCC e 5.25V VIN(0), Logical ‘‘0’’ Input Voltage ADC0833CCJ ADC0833BCN/CCN VCC e 4.75V IIN(1), Logical ‘‘1’’ Input Current ADC0833CCJ ADC0833BCN/CCN VIN e VCC 0.005 0.005 3 2.0 2.0 2.0 V V 0.8 0.8 0.8 V V 1 1 1 mA mA Electrical Characteristics The following specifications apply for VCC e V a e 5V, fCLK e 250 kHz and VREF/2 s (VCC a 0.1V) unless otherwise specified. Boldface limits apply from tMIN to tMAX; all other limits TA e Tj e 25§ C. (Continued) Parameter Conditions Typ (Note 6) Tested Limit (Note 7) Design Limit (Note 8) b 0.005 b 0.005 b1 b1 b1 Units DIGITAL AND DC CHARACTERISTICS (Continued) IIN(0), Logical ‘‘0’’ Input Current ADC0833CCJ ADC0833BCN/CCN VIN e 0V VOUT(1), Logical ‘‘1’’ Output Voltage ADC0833CCJ ADC0833BCN/CCN ADC0833CCJ ADC0833BCN/CCN VCC e 4.75V VOUT(0), Logical ‘‘0’’ Output Voltage ADC0833CCJ ADC0833BCN/CCN IOUT, TRI-STATE Output Current (DO, SARS) ADC0833CCJ ADC0833BCN/CCN ADC0833CCJ ADC0833BCN/CCN IOUT eb360mA mA mA 2.4 2.4 4.5 4.5 4.5 V V V V 0.4 0.4 0.4 V V b 0.1 b 0.1 b3 b3 b3 0.1 0.1 3 3 3 mA mA mA mA b 14 b 14 b 6.5 b 7.5 b 6.5 mA mA 16 16 8.0 9.0 8.0 mA mA 0.9 0.9 4.5 4.5 4.5 mA mA IOUT eb10mA 2.4 IOUT e 1.6mA, VCC e 4.75V VOUT e 0.4V VOUT e 5V ISOURCE ADC0833CCJ ADC0833BCN/CCN VOUT Short to GND ISINK ADC0833CCJ ADC0833BCN/CCN VOUT Short to VCC ICC, Supply Current (Note 3) ADC0833CCJ ADC0833BCN/CCN VREF/2 Open Circuit 4 AC Electrical Characteristics The following specifications apply for VCC e V a e 5V and tr e tf e 20 ns unless otherwise specified. These limits apply for TA e Tj e 25§ C. Parameter fCLK, Clock Frequency Min Max TC, Conversion Time Clock Duty Cycle (Note 12) Typ (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) 10 400 Not including MUX Addressing Time 8 Min Max Units kHz kHz 1/fCLK 40 60 % % tSET-UP, CS Falling Edge or Data Input Valid to CLK Rising Edge 250 ns tHOLD, Data Input Valid after CLK Rising Edge 90 ns 1500 600 ns ns 250 ns ns tpd1, tpd0ÐCLK Falling Edge to Output Data Valid (Note 13) CL e 100 pF Data MSB First Data LSB First t1H, tOHÐRising Edge of CS to Data Output and SARS Hi-Z CL e 10 pF, RL e 10k CL e 100 pF, RL e 2k (see TRI-STATE Test Circuits) 650 250 125 500 CIN, Capacitance of Logic Input 5 pF COUT, Capacitance of Logic Outputs 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the ground pins. Note 3: Internal zener diodes (approx. 7V) are connected from V a to GND and VCC to GND. The zener at V a can operate as a shunt regulator and is connected to VCC via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode insures that VCC will be below breakdown when the device is powered from V a . Functionality is therefore guaranteed for V a operation even though the resultant voltage at VCC may exceed the specified Absolute Max. of 6.5V. It is recommended that a resistor be used to limit the max. current into V a . Note 4: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l V a ) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor. Note 6: Typicals are at 25§ C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 9: See Applications, section 3.0. Note 10: For VIN( b ) t VIN( a ) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 11: Leakage current is measured with the clock not switching. Note 12: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 1ms. The maximum time the clock can be high is 60 ms. The clocked can be stopped when low so long as the analog input voltage remains stable. Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for comparator response time. 5 Timing Diagrams Data Input Timing Data Output Timing TRI-STATE Test Circuits and Waveforms Leakage Current Test Circuit TL/H/5607 – 2 6 Typical Performance Characteristics Effect of Unadjusted Offset Error vs VREF/2 Voltage Linearity Error vs VREF Voltage Linearity Error vs Temperature Linearity Error vs fCLK Power Supply Current vs Temperature Output Current vs Temperature Power Supply Current vs fCLK TL/H/5607 – 3 7 TL/H/5607 – 4 ADC0833 Functional Block Diagram 8 Timing Diagram TL/H/5607 – 5 acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs. A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be selected as a differential pair. Channel 0 or 1 cannot act differentially with any other channel. In addition to selecting differential mode the sign may also be selected. Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is best illustrated by the MUX addressing codes shown in the following table. The MUX address is shifted into the converter through the DI line. Functional Description 1.0 MULTIPLEXER ADDRESSING The design of the ADC0833 utilizes a sample-data comparator structure which provides for a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always the difference between an assigned ‘‘ a ’’ input terminal and a ‘‘b’’ input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned ‘‘ a ’’ input is less than the ‘‘b’’ input the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable single-ended (ground referred) or differential inputs. The analog signal conditioning required in transducer-based data TABLE I. MUX Addressing Single-Ended MUX Mode Address Channel Ý SGL/ ODD/ SELECT DIF SIGN 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 2 3 a a a a COM is internally ties to a GND Differential MUX Mode Address Channel Ý SGL/ ODD/ SELECT DIF SIGN 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 9 0 1 a b b a 2 3 a b b a Functional Description (Continued) ting highly noise immune digital data back to the host processor. Since the input configuration is under software control, it can be modified, as required, at each conversion. A channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved. The analog input voltages for each channel can range from 50 mV below ground to 50mV above VCC(typically 5V) without degrading conversion accuracy. To understand the operation of these converters it is best to refer to the Timing Diagram and Functional Block Diagram and to follow a complete conversion sequence. 1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its MUX assignment word. 2. A clock is then generated by the processor (if not provided continuously) and output to the A/D clock input. 3. On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift register. The start bit is the first logic ‘‘1’’ that appears on this line (all leading zeros are ignored). Following the start bit the converter expects the next 4 bits to be the MUX assignment word. 2.0 THE DIGITAL INTERFACE A most important characteristic of these converters is their serial data link with the controlling processor. Using a serial communication format offers two very significant system improvements; it allows more function to be included in the converter package with no increase in package size and it can eliminate the transmission of low level analog signals by locating the converter right at the analog sensor; transmit- 4 Single-Ended 2 Differential Mixed Mode TL/H/5607 – 6 FIGURE 1. Analog Input Multiplexer Options for the ADC0833 10 inputs vary between very specific voltage limits and the reference voltage for the A/D converter must remain stable with time and temperature. For ratiometric applications, an ADC0834 is a pin-for-pin compatible alternative since it has a VREF input (note the ADC0834 needs one less bit of mux addressing information). The voltage applied to the VREF/2 pin defines the voltage span of the analog input [the difference between VIN( a ) and VIN(b)] over which the 256 possible output codes apply. A full-scale conversion (an all 1s output code) will result when the voltage difference between a selected ‘‘ a ’’ input and ‘‘b’’ input is approximately twice the voltage at the VREF/2 pin. This internal gain of 2 from the applied reference to the full-scale input voltage allows biasing a low voltage reference diode from the 5VDC converter supply. To accommodate a 5V input span, only a 2.5V reference is required. The LM385 and LM336 reference diodes are good low current devices to use with these converters. The output code changes in accordance with the following equation: Functional Description (Continued) 4. When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of (/2 clock period (where nothing happens) is automatically inserted to allow the selected MUX channel to settle. The SAR status line goes high at this time to signal that a conversion is now in progress and the DI line is disabled (it no longer accepts data). 5. The data out (DO) line now comes out of TRI-STATE and provides a leading zero for this one clock period of MUX settling time. 6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater than (high) or less than (low) each successive voltage from the internal resistor ladder, appears at the DO line on each falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and can be read by the processor immediately. 7. After 8 clock periods the conversion is completed. The SAR status line returns low to indicate this (/2 clock cycle later. 8. If the programmer prefers, the data can be read in an LSB first format. All 8 bits of the result are stored in an output shift register. The conversion result, LSB first, is automatically shifted out the DO line, after the MSB first data stream. The DO line then goes low and stays low until CS is returned high. 9. All internal registers are cleared when the CS line is high. If another conversion is desired, CS must make a high to low transition followed by address information. The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire. This is possible because the DI input is only ‘‘looked-at’’ during the MUX addressing interval while the DO line is still in a high impedance state. # J VIN( a ) b VIN(b) 2(VREF/2) where the output code is the decimal equivalent of the 8-bit binary output (ranging from 0 to 255) and the term VREF/2 is the voltage from pin 9 to ground. The VREF/2 pin is the center point of a two resistor divider (each resistor is 3.5 kX) connected from VCC to ground. Total ladder input resistance is the sum of these two equal resistors. As shown in Figure 2, a reference diode with a voltage less than VCC/2 can be connected without requiring an external biasing resistor if its current requirements meet the indicated level. The minimum value of VREF/2 can be quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/256). Output Code e 256 3.0 REFERENCE CONSIDERATIONS The ADC0833 is intended primarily for use in circuits requiring absolute accuracy. In this type of system, the analog TL/H/5607 – 7 VFULL-SCALE j 2.4V VFULL-SCALE j 5.0V VCC VCC/2 b VZ Note: No external biasing resistor needed if VZ k and IZ min k 2 1.75 kX FIGURE 2. Reference Biasing Examples 11 Functional Description (Continued) is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal (/2 LSB value ((/2 LSB e 9.8 mV for VREF/2 e 2.500 VDC). 4.0 THE ANALOG INPUTS The most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the inputs be noisy to begin with or possibly riding on a large common-mode voltage. The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected ‘‘ a ’’ and ‘‘b’’ inputs for a conversion (60 Hz is most typical). The time interval between sampling the ‘‘ a ’’ input and then the ‘‘b’’ input is (/2 of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: Verror(max) e VPEAK(2qfCM) 5.2 Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 1 (/2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input or VCC for a digital output code which is just changing from 1111 1110 to 1111 1111. 5.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN( a ) voltage which equals this desired zero reference plus (/2 LSB (where the LSB is calculated for the desired analog span, using 1 LSB e analog span/256) is applied to selected ‘‘ a ’’ input and the zero reference voltage at the corresponding ‘‘ b’’ input should then be adjusted to just obtain the 00HEX to 01HEX code transition. The full-scale adjustment should be made [with the proper VIn(b) voltage applied] by forcing a voltage to the VIN( a ) input which is given by: #f J 0.5 CLK where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value and fCLK is the A/D clock frequency. For a 60 Hz common-mode signal to generate a (/4 LSB error ( & 5 mV) with the converter running at 250 kHz, its peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input limits. Due to the sampling nature of the analog inputs short spikes of current enter the ‘‘ a ’’ input and exit the ‘‘b’’ input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater than 1 kX. This source resistance limitation is important with regard to the DC leakage currents of input multiplexer as well. The worst-case leakage current of g 1 mA over temperature will create a 1 mV inut error with a 1 kX source resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. VIN ( a ) fs adj e VMAX b 1.5 Ð (VMAX b VMIN) 256 ( where: VMAX e the high end of the analog input range and VMIN e the low end (the offset zero) of the analog range. (Both are ground referenced.) The VREF/2 voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure. 6.0 POWER SUPPLY A unique feature of the ADC0833 is the inclusion of a 7V zener diode connected from the V a terminal to ground which also connects to the VCC terminal (which is the actual converter supply) through a silicon diode, as shown in Figure 3. 5.0 OPTIONAL ADJUSTMENTS 5.1 Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any VIN (b) input at this VIN(MIN) value. This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN(b) input and applying a small magnitude positive voltage to the VIN( a ) input. Zero error is the difference between the actual DC input voltage which TL/H/5607 – 8 FIGURE 3. An On-Chip Shunt Regulator Diode 12 Functional Description (Continued) to be derived from the clock. The low current requirements of the A/D ( E 3 mA) and the relatively high clock frequencies used (typically in the range of 10k-400 kHz) allows using the small value filter capacitor shown to keep the ripple on the VCC line to well under (/4 of an LSB. The shunt zener regulator can also be used in this mode. This requires a clock voltage swing which is in excess of VZ. A current limit for the zener is needed, either built into the clock generator or a resistor can be used from the CLK pin to the V a pin. This zener is intended for use as a shunt voltage regulator to eliminate the need for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source. Figures 4 and 5 illustrate two useful applications of this on-board zener when an external transistor can be afforded. An important use of the interconnecting diode between V a and VCC is shown in Figures 6 and 7. Here, this diode is used as a rectifier to allow the VCC supply for the converter Applications TL/H/5607 – 16 TL/H/5607 – 15 FIGURE 5. Using the A/D as the System Supply Regulator FIGURE 4. Operating with a Temperature Compensated Reference TL/H/5607 – 9 TL/H/5607 – 17 FIGURE 7. Remote SensingÐClock and Power on 1 Wire *Note 4.5V s VCC s 6.3V FIGURE 6. Generally VCC from the Converter Clock 13 Applications (Continued) Digital Link and Sample Controlling Software for the Serially Oriented COP420 and the Bit Programmable I/O INS8048 TL/H/5607 – 10 8048 CODING EXAMPLE COP CODING EXAMPLE Mnemonic LEI SC OGI CLR A AISC 1 XAS LDD NOP XAS Mnemonic ANL P1, Ý0F7H MOV B, Ý5 MOV A, ÝADDR LOOP 1: RRC A JC ONE Instruction ;SELECT A/D (CS e 0) ;BIT COUNTER w 5 ;A w MUX ADDRESS ;CY w ADDRESS BIT ;TEST BIT ;BIT e 0 ZERO: ANL P1, Ý0FEH ;DI w 0 JMP CONT ;CONTINUE ;BIT e 1 ONE: ORL P1, Ý1 ;DI w 1 CONT: CALL PULSE ;PULSE SK 0 x 1 x 0 DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE CALL PULSE ;EXTRA CLOCK FOR SYNC MOV B, Ý8 ;BIT COUNTER w 8 LOOP 2: CALL PULSE ;PULSE SK 0 x 1 x 0 IN A, P1 ;CY w DO RRC A RRC A MOV A, C ;A w RESULT RLC A ;A(0) w BIT AND SHIFT MOV C, A ;C w RESULT DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE RETR ;PULSE SUBROUTINE PULSE: ORL P1, Ý04 ;SK w 1 NOP ;DELAY ANL P1, Ý0FBH ;SK w 0 RET Instruction ENABLES SIO’s INPUT AND OUTPUT Ce1 G0 e 0 (CS e 0) CLEARS ACCUMULATOR LOADS ACCUMULATOR WITH 1 EXCHANGES SIO WITH ACCUMULATOR AND STARTS SK CLOCK LOADS MUX ADDRESS FROM RAM INTO ACCUMULATOR Ð LOADS MUX ADDRESS FROM ACCUMULATOR TO SIO REGISTER START: u 8 INSTRUCTIONS v XAS XIS CLR A RC XAS XIS OGI LEI READS HIGH ORDER NIBBLE (4 BITS) INTO ACCUMULATOR PUTS HIGH ORDER NIBBLE INTO RAM CLEARS ACCUMULATOR Ce0 READS LOW ORDER NIBBLE INTO ACCUMULATOR AND STOPS SK PUTS LOW ORDER NIBBLE INTO RAM G0 e 1 (CS e 1) DISABLES SIO’s INPUT AND OUTPUT 14 Applications (Continued) A ‘‘Stand-Alone’’ Hook-Up for ADC0833 Evaluation Low Cost Remote Temperature Sensor TL/H/5607 – 11 15 Applications (Continued) Digitizing a Current Flow Operating with Automotive Ratiometric Transducers *VIN( b ) e 0.15 VCC 15% of VCC s VXDR s 85% of VCC TL/H/5607 – 12 16 Applications (Continued) Span Adjust: OVsVINs3V TL/H/5607 – 18 Zero-Shift and Span Adjust: 2VsVINs5V TL/H/5607 – 19 Protecting the Input High Accuracy Comparators DO e all 1s if a VIN l b VIN DO e all 0s if a VIN k b VIN Diodes are 1N914 TL/H/5607 – 20 For additional application ideas, refer to the data sheet for the ADC0831 family of serial data converters. 17 TL/H/5607 – 13 Ordering Information Temperature Range Total Unadjusted Error ADC0833BCN 0§ C to a 70§ C g 1/2 LSB ADC0833CCJ b 40§ C to a 85§ C ADC0833CCN 0§ C to a 70§ C Part Number 18 g 1 LSB Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number ADC0833CCJ NS Package Number J14A 19 ADC0833 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number ADC0833BCN or ADC0833CCN NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.