ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters General Description Key Specifications The ADC1205 and ADC1225 are CMOS, 12-bit plus sign successive approximation A/D converters. The 24-pin ADC1205 outputs the 13-bit data result in two 8-bit bytes, formatted high-byte first with sign extended. The 28-pin ADC1225 outputs a 13-bit word in parallel for direct interface to a 16-bit data bus. Negative numbers are represented in 2’s complement data format. All digital signals are fully TTL and MOS compatible. A unipolar input (0V to 5V) can be accommodated with a single 5V supply, while a bipolar input (b5V to a 5V) requires the addition of a 5V negative supply. The ADC1205C and ADC1225C have a maximum non-linearity of 0.0224% of Full Scale. Y Y Y ResolutionÐ12 bits plus sign Linearity ErrorÐ g 1 LSB Conversion TimeÐ100 ms Features Y Y Y Y Y Y Compatible with all mPs True differential analog voltage inputs 0V to 5V analog voltage range with single 5V supply TTL/MOS input/output compatible Low powerÐ25 mW max Standard 24-pin or 28-pin DIP Connection and Functional Diagrams Dual-In-Line Package TL/H/5676–1 Top View Dual-In-Line Package TL/H/5676 – 3 See Ordering Information Top View TL/H/5676–2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/5676 RRD-B30M115/Printed in U. S. A. ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters June 1994 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (DVCC and AVCC) 6.5V b 15V to GND Negative Supply Voltage (Vb) b 0.3V to a 15V Logic Control Inputs Voltage at Analog Inputs [VIN( a ), VIN(b)] (Vb)b0.3V to VCC a 0.3V b 0.3V to (VCC a 0.3)V Voltage at All Outputs, VREF, VOS g 5mA Input Current per Pin g 20mA Input Current per Package b 65§ C to a 150§ C Storage Temperature Range 875 mW Package Dissipation at TA e 25§ C Lead Temp. (Soldering, 10 seconds) 300§ C ESD Susceptibility (Note 12) 800V Temperature Range ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1 Supply Voltage (DVCC and AVCC) Negative Supply Voltage (Vb) TMINsTAsTMAX b 40§ C s TA s a 85§ C 0§ CsTAs70§ C 4.5 VDC to 6.0 VDC b 15V to GND Electrical Characteristics The following specifications apply for DVCC e AVCC e 5V, VREF e 5V, fCLK e 1.0 MHz, Vb e b5V for bipolar input range, or Vb e GND for unipolar input range unless otherwise specified. Bipolar input range is defined as b5.05V s VIN( a ) s 5.05V; b 5.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Unipolar input range is defined as b 0.05V s VIN( a ) s 5.05V; b 0.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C (Notes 3, 4, 5, 6, 7). ADC1205CCJ, ADC1225CCD Parameter Conditions Typ (Note 8) Tested Design Limit Limit (Note 9) (Note 10) ADC1205CCJ-1, ADC1225CCD-1 Typ (Note 8) Limit Units Tested Limit (Note 9) Design Limit (Note 10) g1 g1 LSB LSB CONVERTER CHARACTERISTICS Linearity Error Unipolar Input ADC1205CCJ, ADC1225CCD Range ADC1205CCJ-1, ADC1225CCD-1 (Note 11) g1 Unadjusted Zero Error Unipolar Input Range g2 g2 g2 LSB Unadjusted Positive and Negative Full-Scale Error Unipolar Input Range g 30 g 30 g 30 LSB Negative Full-Scale Error Unipolar Input Range, Full Scale Adj. to Zero g (/2 LSB g2 g2 LSB LSB g (/2 Linearity Error Bipolar Input ADC1205CCJ, ADC1225CCD Range ADC1205CCJ-1, ADC1225CCD-1 (Note 11) g2 Unadjusted Zero Error Bipolar Input Range g2 g2 g2 LSB Unadjusted Positive and Negative Full-Scale Error Bipolar Input Range g 30 g 30 g 30 LSB Negative Full-Scale Error Bipolar Input Range, Full Scale Adj. to Zero g2 g2 g2 LSB Maximum Gain Temperature Coefficient 6 15 6 15 ppm/§ C Maximum Offset Temperature Coefficient 0.5 1.5 0.5 1.5 ppm/§ C Minimum VREF Input Resistance 4.0 2 4.0 2 2 kX Maximum VREF Input Resistance 4.0 8 4.0 8 8 kX 2 Electrical Characteristics (Continued) The following specifications apply for DVCC e AVCC e 5V, VREF e 5V, fCLK e 1.0 MHz, Vb e b5V for bipolar input range, or Vb e GND for unipolar input range unless otherwise specified. Bipolar input range is defined as b5.05V s VIN( a ) s 5.05V; b 5.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Unipolar input range is defined as b 0.05V s VIN( a ) s 5.05V; b 0.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C (Notes 3, 4, 5, 6, 7). ADC1205CCJ, ADC1225CCD Parameter Conditions Typ (Note 8) Tested Limit (Note 9) Design Limit (Note 10) ADC1205CCJ-1, ADC1225CCD-1 Typ (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Limit Units GND-0.05 GND-0.05 V CONVERTER CHARACTERISTICS (Continued) Minimum Analog Input Voltage Maximum Analog Input Voltage Unipolar Input Range Bipolar Input Range Unipolar Input Range Bipolar Input Range b VC b 0.05 b VCC b 0.05 V VCC a 0.05 VCC a 0.05 V VCC a 0.05 VCC a 0.05 V g (/2 g (/2 LSB g */4 g */4 g */4 g */4 g */4 g */4 LSB LSB g (/4 g (/4 g (/4 LSB b VCC b 0.05 VCC a 0.05 VCC a 0.05 g (/8 DC Common-Mode Error Power Supply Sensitivity GND-0.05 g (/2 g (/8 AVCC e DVCC e 5V g 5%, Vb eb5V g 5% Zero Error Positive and Negative Full-Scale Error Linearity Error DIGITAL AND DC CHARACTERISTICS VIN(1), Logical ‘‘1’’ Input Voltage (Min) VCC e 5.25V, All Inputs except CLK IN 2.0 2.0 2.0 V VIN(0), Logical ‘‘0’’ Input Voltage (Max) VCC e 4.75V, All Inputs except CLK IN 0.8 0.8 0.8 V IIN(1), Logical ‘‘1’’ Input Current (Max) VIN e 5V 0.005 1 0.005 1 mA IIN(0), Logical ‘‘0’’ Input Current (Max) VIN e 0V b 0.005 b1 b 0.005 b1 mA VT a (Min), Minimum PositiveGoing Threshold Voltage CLK IN 3.1 2.7 3.1 2.7 2.7 V VT a (Max), Maximum Positive- CLK IN Going Threshold Voltage 3.1 3.5 3.1 3.5 3.5 V VTb (Min), Minimum NegativeGoing Threshold Voltage CLK IN 1.8 1.4 1.8 1.4 1.4 V VTb (Max), Maximum Negative- CLK IN Going Threshold Voltage 1.8 2.1 1.8 2.1 2.1 V VH(Min), Minimum Hysteresis [VT a (Min)bVTb(Max)] CLK IN 1.3 0.6 1.3 0.6 0.6 V VH(Max), Maximum Hysteresis [VT a (Max)bVTb(Min)] CLK IN 1.3 2.1 1.3 2.1 2.1 V 3 Electrical Characteristics (Continued) The following specifications apply for DVCC e AVCC e 5V, VREF e 5V, fCLK e 1.0 MHz, Vb e b5V for bipolar input range, or Vb e GND for unipolar input range unless otherwise specified. Bipolar input range is defined as b5.05V s VIN( a ) s 5.05V; b 5.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Unipolar input range is defined as b 0.05V s VIN( a ) s 5.05V; b 0.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C (Notes 3, 4, 5, 6, 7). ADC1205CCJ, ADC1225CCD Parameter Conditions Typ (Note 8) Tested Design Limit Limit (Note 9) (Note 10) ADC1205CCJ-1, ADC1225CCD-1 Typ (Note 8) Tested Limit (Note 9) Design Limit Units Limit (Note 10) DIGITAL AND DC CHARACTERISTICS (Continued) VOUT(1), Logical ‘‘1’’ Output Voltage (Min) VCC e 4.75V IOUT eb360 mA IOUT eb10 mA VOUT(0), Logical ‘‘0’’ Output Voltage (Max) VCC e 4.75V IOUT e 1.6 mA IOUT, TRI-STATE Output Leakage VOUT e 0V Current (Max) VOUT e 5V 2.4 4.5 2.4 4.5 2.4 4.5 V V 0.4 0.4 0.4 V b 0.01 b3 b 0.01 b 0.3 b3 0.01 3 0.01 0.3 3 mA mA ISOURCE, Output Source Current (Min) VOUT e 0V b 12 b 6.0 b 12 b 7.0 b 6.0 mA ISINK, Output Sink Current (Min) VOUT e 5V 16 8.0 16 9.0 8.0 mA DICC, DVCC Supply Current (Max) fCLK e 1 MHz, CS e 1 1 3 1 2.5 3 mA AICC, AVCC Supply Current (Max) fCLK e 1 MHz, CS e 1 1 3 1 2.5 3 mA Ib, 10 100 10 100 100 mA Vb fCLK e 1 MHz, CS e 1 Supply Current (Max) AC Electrical Characteristics The following specifications apply for DVCC e AVCC e 5.0V, tr e tf e 20 ns and TA e 25§ C unless otherwise specified. Parameter Conditions Typ (Note 8) Tested Limit (Note 9) 1.0 1.0 0.3 1.5 Design Limit (Note 10) Limit Units fCLK, Clock Frequency MIN MAX Clock Duty Cycle MIN MAX 40 60 % % TC, Conversion Time MIN MAX MIN MAX 108 109 108 109 1/fCLK 1/fCLK ms ms tW(WR)L, WR Pulse Width fCLK e 1.0 MHz fCLK e 1.0 MHz MAX MHz MHz 220 350 ns tACC, Access Time (Delay from Falling Edge of RD to Output Data Valid) (Max) CL e 100 pF 210 340 ns t1H, t0H, TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) (Max) RL e 2k, CL e 100 pF 170 290 ns tPD(READYOUT), RD or WR to READYOUT Delay (Max) 250 400 ns tPD(INT),RD or WR to Reset of INT (Max) 250 400 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings. Note 2: All voltages are measured with respect to ground, unless otherwise specified. Note 3: A parasitic zener diode exists internally from AVCC and DVCC to ground. This parasitic zener has a typical breakdown voltage of 7 VDC. 4 AC Electrical Characteristics (Continued) Note 4: Two on-chip diodes are tied to each analog input as shown below. TL/H/5676 – 4 Errors in the A/D conversion can occur if these diodes are forward biased more than 50 mV. This means that if AVCC and DVCC are minimum (4.75 VDC) and Vb is minimum ( b 4.75VDC), full-scale must be s 4.8VDC. Note 5: A diode exists between analog VCC and digital VC. TL/H/5676 – 20 To guarantee accuracy, it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin. Note 6: A diode exists between analog ground and digital ground. TL/H/5676 – 21 To guarantee accuracy, it is required that the analog ground and digital ground be connected together externally. Note 7: Accuracy is guaranteed at fCLK e 1.0 MHz. At higher clock frequencies accuracy may degrade. Note 8: Typicals are at 25§ C and represent most likely parametric norm. Note 9: Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 11: Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through positive full scale and zero, after adjusting zero error. (See Figures 1b and 1c ). Note 12: Human body model; 100 pF discharged through a 1.5 kX resistor. TL/H/5676 – 8 FIGURE 1a. Transfer Characteristic 5 TL/H/5676 – 22 FIGURE 1b. Simplified Error Curve vs. Output Code Without Zero and Fullscale Adjustment TL/H/5676 – 23 FIGURE 1c. Simplified Error Curve vs. Output Code after Zero/Fullscale Adjustment TL/H/5676 – 7 FIGURE 2. TRI-STATE Test Circuits and Waveforms 6 Timing Diagrams TL/H/5676 – 15 FIGURE 3. Timing Diagram TL/H/5676 – 13 FIGURE 4. Ready Out TL/H/5676 – 14 FIGURE 5. Data Out 7 8 FIGURE 6. Functional Block Diagram TL/H/5676 – 5 Functional Description Setting CC enables the UPDATE LOGIC . This logic controls the transfer of data from the SAR LOGIC to the OUTPUT LATCH  and resets the internal logic in preparation for a new conversion. This means that when EOC goes high, a new conversion can be immediately started since the internal logic has already been reset. In the same way, data is transferred to the OUTPUT LATCH prior to issuing an interrupt. This assures that data can be read immediately after INT goes low. 1.0 THE A/D CONVERSION 1.1 STARTING A CONVERSION When using the ADC1225 or ADC1205 with a microprocessor, starting an A-to-D conversion is like writing to an external memory location. The WR and CS lines are used to start the conversion. The simplified logic (Figure 6 ) shows that the falling edge of WR with CS low clocks the D-type flipflop and initiates the conversion sequence. A new conversion can therefore be restarted before the end of the previous sequence. INT going low indicates the conversion’s end. 2.0 READING THE A/D The ADC 1225 makes all thirteen bits of the conversion result available in parallel. Taking CS and RD low enables the TRI-STATEÉ output buffers. The conversion result is represented in 2’s complement format. The ADC1205 makes the conversion result available in two eight-bit bytes. The output format is 2’s complement with extended sign. Data is right justified and presented high byte first. With CS low and STATUS high, the high byte (DB12 – DB8) will be enabled on the output buffers the first time RD goes low. When RD goes low a second time, the low byte (DB7 – DB0) will be enabled. On each read operation, the ‘byst’ flip-flop is toggled so that on successive reads alternate bytes will be available on the outputs. The ‘byst’ flip-flop is always reset to the high byte at the end of a conversion. Table 1 below shows the data bit locations on the ADC1205. The ADC1205’s STATUS pin makes it possible to read the conversion status and the state of the ‘byst’ flip-flop. With RD, STATUS and CS low, this information appears on the data bus. The ‘byst’ status appears on pin 18 (DB2/DB10). A low output on pin 18 indicates that the next data read will be the high byte. A high output indicates that the next data read will be the low byte. A high status bit on pin 22 (DB6/ DB12) indicates that the conversion is in progress. A high output appears on pin 17 (DB1/DB9) when the conversion is completed and the data has been transferred to the output latch. A high output on pin 16 (DB0/DB8) indicates that the conversion has been completed and the data is ready to read. This status bit is reset when a new conversion is initiated, data is read, or status is read. When reading status or a conversion result, STATUS should always change states at least 600 ns before RD goes low. If the conversion status information is not needed, the STATUS pin should be hardwired to V a . Table 2 summarizes the meanings of the four status bits. TABLE I. Data Bit Locations, ADC1205 1.2 THE CONVERSION PROCESS (Numbers designated by [ ] refer to portions of Figure 6 .) The SARS LOGIC  controls the A-to-D conversion process. When ‘sars’ goes high the clock (clk) is gated to the TIMING GENERATOR . One of the outputs of the TIMING GENERATOR, Tz, provides the clock for the Successive Approximation Register, SAR LOGIC . The Tz clock rate is (/8 of the CLK IN frequency. Inputs to the 12-BIT DAC  and control of the SAMPLED DATA COMPARATOR  sign logic are provided by the SAR LOGIC. The first step in the conversion process is to set the sign to positive (logic ‘0’) and the input of the DAC to 000 (HEX notation). If the differential input, VIN( a )bVIN(b), is positive the sign bit will remain low. If it is negative the sign bit will be set high. Differential inputs of only a few hundred microvolts are enough to provide full logic swings at the output of the SAMPLED DATA COMPARATOR. The sign bit indicates the polarity of the differential input. If it is set high, the negative input must have been greater than the positive input. By reversing the polarity of the differential input, VIN( a ) and VIN(b) are interchanged and the DAC sees the negative input as positive. The input polarity reversal is done digitally by changing the timing on the input sampling switches of the SAMPLED DATA COMPARATOR. Thus, with almost no additional circuitry, the A/D is extended from a unipolar 12-bit to a bipolar 12-bit (12-bit plus sign) device. After determining the input polarity, the conversion proceeds with the successive approximation process. The SAR LOGIC successively tries each bit of the 12-BIT DAC. The most significant bit (MSB), B11, has a weight of (/2 of VREF. The next bit, B10, has a weight of (/4 VREF. Each successive bit is reduced in weight by a factor of 2 which gives the least significant bit (LSB) a weight of 1/4096 VREF. When the MSB is tried, the comparator compares the DAC output, VREF/2, to the analog input. If the analog input is greater than VREF/2 the comparator tells the SAR LOGIC to set the MSB. If the analog input is less than VREF/2 the comparator tells the SAR LOGIC to reset the MSB. On the next bit-test the DAC output will either be */4 VREF or (/4 VREF depending on whether the MSB was set or not. Following this sequence through for each successive bit will approximate the analog input to within 1-bit (one part in 4096). On completion of the LSB bit-test the conversion-complete flip-flop (CC) is set, signifying that the conversion is finished. The end-of-conversion (EOC) and interrupt (INT) lines are not changed at this time. Some internal housekeeping tasks must be completed before the outside world is notified that the conversion is finished. HIGH BYTE DB12 DB12 DB12 DB12 DB11 DB10 DB9 DB8 LOW BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TABLE II. Status Bit Locations and Meanings 9 Status Bit Location Status Bit DB6 SARS ‘‘High’’ indicates that the conversion is in progress DB2 BYST ‘‘Low’’ indicates that the next data read is the high byte. ‘‘High’’ indicates that the next data read is the low byte Meaning Condition to Clear Status Bit Status write or toggle it with data read Functional Description (Continued) TABLE II. Status Bit Locations and Meanings (Continued) Status Status Bit Bit Location Meaning DB1 EOC ‘‘High’’ indicates that the conversion is completed and data is transferred to the output latch. DB0 INT ‘‘High’’ indicates that it is the end of the conversion and the data is ready to read Condition to Clear Status Bit Data read or status read or status write 3.0 INTERFACE TL/H/5676 – 10 FIGURE 8. READY OUT Timing Diagram 3.1 RESET OF INTERRUPT INT goes low at the end of the conversion and indicates that data is transferred to the output latch. By reading data, INT will be reset to high on the leading edge of the first read (RD going low). INT is also reset on the leading (falling) edge of WR when starting a conversion. 3.3 RESETTING THE A/D All the internal logic can be reset, which will abort any conversion in process and reset the status bits. The reset function is achieved by performing a status write (CS, WR and STATUS are low). 3.4 ADDITIONAL TIMING AND INTERFACE OPTIONS ADC1225 1. WR and RD can be tied together with CS low continuously or strobed. The previous conversion’s data will be available when the WR and RD are low as shown below. One drawback is that, since the conversion is started on the falling edge and the data read on the rising edge of WR/RD, the first data access will have erroneous information depending on the power-up state of the internal output latches. If the WR/RD strobe is longer than the conversion time, INTR will never go low to signal the end of a conversion. The conversion will be completed and the output latches will be updated. In this case the READY OUT signal can be used to sense the end of the conversion since it will go low when the output latches are being updated. 3.2 READY OUT To simplify the hardware connection to high speed microprocessors, a READY OUT line is provided. This allows the A-to-D to insert a wait state in the mP’s read cycle. The equivalent circuit and the timing diagram for READY OUT is shown in Figures 7 and 8 . TL/H/5676–9 FIGURE 7. READY OUT Equivalent Circuit TL/H/5676 – 24 FIGURE 9 10 Functional Description (Continued) TL/H/5676 – 25 FIGURE 10 TL/H/5676 – 26 FIGURE 11 TL/H/5676 – 27 FIGURE 12 11 Functional Description (Continued) TL/H/5676 – 28 TL/H/5676 – 29 FIGURE 13 When using this method of conversion only one strobe is necessary and the rising edge of WR/RD can be used to read the current conversion results. These methods reduce the throughput time of the conversion since the RD and WR cycles are combined. 2. With the standard timing WR pulse width longer than the conversion time a conversion is completed but the INTR will never go low to signal the end of a conversion. The output latches will be updated and valid information will be available when the RD cycle is accomplished. 3. Tying CS and RD low continuously and strobing WR to initiate a conversion will also yield valid data. The INTR will never go low to signal the end of a conversion and the digital outputs will always be enabled, so using INTR to strobe the WR line for a continuous conversion cannot be done with this part. A simple stand-alone circuit can be accomplished by driving WR with the inverse of the READY OUT signal using a simple inverter as shown below. FIGURE 14 12 TL/H/5676 – 30 Functional Description (Continued) through the output resistance of the analog signal source. This charge pumping action is worse for continuous conversions with the VIN( a ) input voltage at full-scale. For continuous conversions with a 1 MHz clock frequency and the VIN( a ) input at 5V, the average input current is approximately 5 mA. For this reason bypass capacitors should not be used at the analog inputs for high resistance sources (RSOURCE 100 X). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental effects of the voltage drop across this input resistance, due to the average value of the input current, can be minimized with a full-scale adjustment while the given source resistance and input bypass capacitor are both in place. This is effective because the average value of the input current is a linear function of the differential input voltage. ADC1205 Case 1 would be the only one that would appy to the ADC1205 since two RD strobes are necessary to retrieve the 13 bits of information on the 8 bit data bus. Simultaneously strobing WR and RD low will enable the most significant byte on DB0–DB7 and start a conversion. Pulsing WR/RD low before the end of this conversion will enable the least significant byte of data on the outputs and restart a conversion. 4.0 REFERENCE VOLTAGE The voltage applied to the reference input of the converter defines the voltage span of the analog inputs (the difference between VIN( a ) and VIN(b), over which 4096 positive output codes and 4096 negative output codes exist. The A-to-D can be used in either ratiometric or absolute reference applications. VREF must be connected to a voltage source capable of driving the reference input resistance (typically 4 kX). In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. When this voltage is the system power supply, the VREF pin can be tied to VCC. This technique relaxes the stability requirement of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors. 5.4 INPUT SOURCE RESISTANCE Large values of source resistance where an input bypass capacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (Rs100 X) for a passive RC section or add an op amp RC active low pass filter. For low source resistance applications, (RSOURCEs100 X) a 0.001 mF bypass capacitor at the inputs will prevent pickup due to series lead inductance of a long wire. A 100 X series resistor can be used to isolate this capacitor – both the R and C are placed outside the feedback loop – from the output of an op amp, if used. 5.5 NOISE The leads to the analog inputs should be kept as short as possible to minimize input noise coupling. Both noise and undesired digital clock coupling to these inputs can cause errors. Input filtering can be used to reduce the effects of these sources, but careful note should be taken of sections 5.3 and 5.4 if this route is taken. 5.0 THE ANALOG INPUTS 5.1 DIFFERENTIAL VOLTAGE INPUTS AND COMMON MODE REJECTION The differential inputs of the ADC1225 and ADC1205 actually reduce the effects of common-mode input noise, i.e., signals common to both VIN( a ) and VIN(b) inputs (60 Hz is most typical). The time interval between sampling the ‘‘ a ’’ and ‘‘b‘‘ input is 4 clock periods. Therefore, a change in the common-mode voltage during this short time interval may cause conversion errors. For a sinusoidal common-mode signal the error would be: 6.0 POWER SUPPLIES Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. Low inductance tantalum capacitors of 1 mF or greater are recommended for supply bypassing. Separate bypass caps should be placed close to the DVCC and AVCC pins. If an unregulated voltage source is available in the system, a separate LM340LAZ-5.0 voltage regulator for the A-to-D’s VCC (and other analog circuitry) will greatly reduce digital noise on the supply line. 4 fCLK where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value and fCLK is the converter’s clock frequency. In most cases VERROR will not be significant. For a 60 Hz common-mode signal to generate a (/4 LSB error (300 mV) with the converter running at 1 MHz its peak value would have to be 200mV. VERROR(MAX) e VPEAK (2q fCM) 7.0 ERRORS AND REFERENCE VOLTAGE ADJUSTMENTS 7.1 ZERO ADJUST The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN(b) input and applying a small magnitude positive voltage to the VIN( a ) input. Zero error is the difference between the actual DC input voltage necessary to just cause an output digital code transition from all zeroes to 0,0000,0000,0001 and the ideal (/2 LSB value ((/2 LSB e 0.61 mV for VREF e 5 VDC). Zero error can be adjusted as shown in Figure 15 . VIN( a ) is forced to 0.61 mV, and VIN(b) is forced to 0V. The potentiometer is adjusted until the digital output code changes from all zeroes to 0,000,0000,0001. 5.2 INPUT CURRENT Due to the sampling nature of the analog inputs, short duration spikes of current enter the ‘‘ a ’’ input and exit the ‘‘b’’ input at the leading clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. 5.3 INPUT BYPASS CAPACITORS Bypass capacitors at the inputs will average the current spikes mentioned in 5.2 and cause a DC current to flow 13 Functional Description (Continued) tude of the VREF input so that the output code is just changing from 0,1111,1111,1110 to 0,1111,1111,1111. A simpler, although slightly less accurate, approach is to ground VIN( a ) and VIN(b), and adjust for all zeros at the output. Error will be well under (/2 LSB if the adjustment is done so that the potentiometer is ‘‘centered’’ within the 0,000,000 range. A positive voltage at the VOS input will reduce the output code. The adjustment range is a 4 to b 30 LSB. Bipolar Inputs Do the same procedure outlined above for the unipolar case and then change the differential input voltage so that the digital output code is just changing from 1,0000,0000,0001 to 1,0000,0000,0000. Record the differential input voltage, VX. the ideal differential input voltage for that transition should be; # b VF a VF 8192 J Calculate the difference between Vx and the ideal voltage; VF D e VX b bVF a 8192 Then apply a differential input voltage of; # #V J J D 2 and adjust the magnitude of VREF so the digital output code is just changing from 1,0000,0000,0001 to 1,0000,0000,0000. That will obtain the positive and negative full-scale transition with symmetrical minimum error. TL/H/5676–11 Xb FIGURE 15. Zero Adjust Circuit 7.2 POSITIVE AND NEGATIVE FULL-SCALE ADJUSTMENT Unipolar Inputs Apply a differential input voltage which is 1.5 LSB below the desired analog full-scale voltage (VF) and adjust the magni- Typical Applications *Input must have some current return path to signal ground TL/H/5676 – 12 14 Typical Applications (Continued) Protecting the Input TL/H/5676 – 16 Diodes are 1N914 Operating with Ratiometric Transducers *VIN( b ) e 0.15 VCC 15% of VCC s VXDR s 85% of VCC TL/H/5676 – 17 15 Typical Applications (Continued) Bipolar Input Temperature Converter TL/H/5676 – 18 a 150 to b 55§ C with 0.04§ C resolution Note: * resistors are 1% metal film types Strain Gauge Converter with .025% Resolution and Single Power Supply TL/H/5676 – 19 Note: 1)* resistors are 1% metal film types 2) LF412 power a 10V and ground 16 Ordering Information Temperature Range Non-Linearity 0.024% Package Outline 0§ C to 70§ C b 40§ C to a 85§ C ADC1205CCJ-1 ADC1225CCD-1 ADC1205CCJ ADC1225CCD J24A D28D J24A D28D Physical Dimensions inches (millimeters) Ceramic Dual-In Line Package (J) Order Number ADC1205CCJ-1 or ADC1205CCJ NS Package Number J24A 17 ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters Physical Dimensions inches (millimeters) (Continued) Ceramic Dual-In-Line Package (D) Order Number ADC1225CCD-1 or ADC1225CCD NS Package Number D28D LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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