54F/74F175 Quad D Flip-Flop General Description Features The ’F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, LOW. Y Commercial Y Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous common reset True and complement output Guaranteed 4000V minimum ESD protection Package Number Military 74F175PC 54F175DM (Note 2) 74F175SC (Note 1) Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F175FM (Note 2) W16A 16-Lead Cerpack 54F175LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F175SJ (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak IEEE/IEC TL/F/9490 – 1 Pin Assignment for LCC TL/F/9490 – 2 TL/F/9490–5 TL/F/9490 – 3 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9490 RRD-B30M75/Printed in U. S. A. 54F/74F175 Quad D Flip-Flop November 1994 Unit Loading/Fan Out 54F/74F Pin Names D0 – D3 CP MR Q0 – Q3 Q0 – Q3 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) True Outputs Complement Outputs 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA b 1 mA/20 mA Functional Description Truth Table The ’F175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The ’F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Inputs Outputs MR CP Dn Qn Qn L H H X L L X H L L H L H L H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition Logic Diagram TL/F/9490 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current 2.5 2.5 2.7 4.75 b 60 22.5 3 b 0.6 mA Max VIN e 0.5V b 150 mA Max VOUT e 0V 34.0 mA Max CP e L Dn e MR e HIGH AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Typ fmax Maximum Clock Frequency 100 140 tPLH tPHL Propagation Delay CP to Qn or Qn 4.0 4.0 5.0 6.5 6.5 8.5 3.5 4.0 8.5 10.5 4.0 4.0 7.5 9.5 ns tPHL Propagation Delay MR to Qn 4.5 9.0 11.5 4.5 15.0 4.5 13.0 ns tPLH Propagation Delay MR to Qn 4.0 6.5 8.0 4.0 10.0 4.0 9.0 ns 80 Min Units Max 100 MHz AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to CP 3.0 3.0 3.0 3.0 3.0 3.0 th(H) th(L) Hold Time, HIGH or LOW Dn to CP 1.0 1.0 1.0 2.0 1.0 1.0 tw(H) tw(L) CP Pulse Width HIGH or LOW 4.0 5.0 4.0 5.0 4.0 5.0 Units Max ns ns tw(L) MR Pulse Width, LOW 5.0 5.0 5.0 ns trec Recovery Time, MR to CP 5.0 5.0 5.0 ns 4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 175 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 5 Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 7 54F/74F175 Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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