HOLTEK HT66F017L

0.9V Battery Flash A/D Type 8-Bit MCU
HT66F016L/HT66F017L
Revision: V1.00
Date: �������������
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Table of Contents
Features............................................................................................................. 6
CPU Features.......................................................................................................................... 6
Peripheral Features.................................................................................................................. 6
General Description.......................................................................................... 7
Selection Table.................................................................................................. 7
Block Diagram................................................................................................... 8
Pin Assignment................................................................................................. 8
Pin Description................................................................................................. 9
Absolute Maximum Ratings........................................................................... 10
D.C. Characteristics........................................................................................ 10
A.C. Characteristics.........................................................................................11
LVD & LVR Electrical Characteristics........................................................... 12
ADC Characteristics....................................................................................... 13
Comparator Electrical Characteristics......................................................... 13
DC/DC Converter Electrical Characteristics................................................ 14
Power on Reset Electrical Characteristics................................................... 14
Bandgap Reference (VBG) Characteristic Curve........................................... 15
System Architecture....................................................................................... 15
Clocking and Pipelining.......................................................................................................... 15
Program Counter.................................................................................................................... 16
Stack...................................................................................................................................... 17
Arithmetic and Logic Unit – ALU............................................................................................ 17
Flash Program Memory.................................................................................. 18
Structure................................................................................................................................. 18
Special Vectors...................................................................................................................... 18
Look-up Table......................................................................................................................... 19
Table Program Example......................................................................................................... 19
In Circuit Programming.......................................................................................................... 20
On-Chip Debug Support – OCDS.......................................................................................... 21
RAM Data Memory.......................................................................................... 22
Structure................................................................................................................................. 22
General Purpose Data Memory Structure.............................................................................. 22
Rev. 1.00
2
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Special Function Register Description......................................................... 24
Indirect Addressing Registers – IAR0, IAR1.......................................................................... 24
Memory Pointers – MP0, MP1............................................................................................... 24
Bank Pointer – BP.................................................................................................................. 25
Accumulator – ACC................................................................................................................ 25
Program Counter Low Register – PCL................................................................................... 25
Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 25
Status Register – STATUS..................................................................................................... 26
EEPROM Data Memory................................................................................... 28
EEPROM Data Memory Structure......................................................................................... 28
EEPROM Registers............................................................................................................... 28
Reading Data from the EEPROM.......................................................................................... 30
Writing Data to the EEPROM................................................................................................. 30
Write Protection...................................................................................................................... 30
EEPROM Interrupt................................................................................................................. 30
Programming Considerations................................................................................................. 31
Programming Examples......................................................................................................... 31
Oscillator......................................................................................................... 32
Oscillator Overview................................................................................................................ 32
System Clock Configurations................................................................................................. 32
External Crystal/Ceramic Oscillator – HXT............................................................................ 33
High Speed Internal RC Oscillator – HIRC............................................................................ 34
Internal 32kHz Oscillator – LIRC............................................................................................ 34
Supplementary Oscillator....................................................................................................... 34
Operating Modes and System Clocks.......................................................... 35
System Clocks....................................................................................................................... 35
System Operation Modes....................................................................................................... 36
Control Register..................................................................................................................... 37
Fast Wake-up......................................................................................................................... 38
Operating Mode Switching and Wake-up............................................................................... 39
Standby Current Considerations............................................................................................ 43
Wake-up................................................................................................................................. 43
Programming Considerations................................................................................................. 44
Watchdog Timer.............................................................................................. 44
Watchdog Timer Clock Source............................................................................................... 44
Watchdog Timer Control Register.......................................................................................... 44
Watchdog Timer Operation.................................................................................................... 46
Reset and Initialisation................................................................................... 47
Reset Functions..................................................................................................................... 47
Reset Initial Conditions.......................................................................................................... 50
Rev. 1.00
3
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Input/Output Ports.......................................................................................... 52
Pull-high Resistors................................................................................................................. 52
Port A Wake-up...................................................................................................................... 53
I/O Port Control Registers...................................................................................................... 53
Pin-remapping Functions....................................................................................................... 54
Pin-remapping Registers........................................................................................................ 54
I/O Pin Structures................................................................................................................... 55
Programming Considerations................................................................................................. 56
Timer Modules – TM....................................................................................... 57
Introduction............................................................................................................................ 57
TM Operation......................................................................................................................... 57
TM Clock Source.................................................................................................................... 58
TM Interrupts.......................................................................................................................... 58
TM External Pins.................................................................................................................... 58
TM Input/Output Pin Control Registers.................................................................................. 59
Programming Considerations................................................................................................. 60
Compact Type TM – CTM............................................................................... 61
Compact TM Operation.......................................................................................................... 61
Compact Type TM Register Description................................................................................ 61
Compact Type TM Operating Modes..................................................................................... 66
Compare Match Output Mode................................................................................................ 66
Timer/Counter Mode.............................................................................................................. 69
PWM Output Mode................................................................................................................. 69
Standard Type TM – STM............................................................................... 72
Standard TM Operation.......................................................................................................... 72
Standard Type TM Register Description................................................................................ 72
Standard Type TM Operating Modes..................................................................................... 77
Compare Match Output Mode................................................................................................ 77
Timer/Counter Mode.............................................................................................................. 80
PWM Output Mode................................................................................................................. 80
Single Pulse Mode................................................................................................................. 83
Capture Input Mode............................................................................................................... 85
Analog to Digital Converter........................................................................... 86
A/D Overview......................................................................................................................... 86
A/D Converter Register Description....................................................................................... 86
A/D Converter Data Registers – ADRL, ADRH...................................................................... 87
A/D Converter Control Registers – ADCR0, ADCR1, ACERL................................................ 87
A/D Operation........................................................................................................................ 90
A/D Input Pins........................................................................................................................ 91
Summary of A/D Conversion Steps........................................................................................ 92
Programming Considerations................................................................................................. 93
A/D Transfer Function............................................................................................................ 93
A/D Programming Examples.................................................................................................. 94
Rev. 1.00
4
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Comparators................................................................................................... 96
Comparator Operation........................................................................................................... 96
Comparator Interrupt.............................................................................................................. 96
Programming Considerations................................................................................................. 96
Interrupts......................................................................................................... 98
Interrupt Registers.................................................................................................................. 98
Interrupt Operation............................................................................................................... 103
External Interrupt.................................................................................................................. 104
Comparator Interrupt............................................................................................................ 105
Multi-function Interrupt......................................................................................................... 105
A/D Converter Interrupt........................................................................................................ 105
Time Base Interrupts............................................................................................................ 106
EEPROM Interrupt............................................................................................................... 107
LVD Interrupt........................................................................................................................ 107
TM Interrupts........................................................................................................................ 107
Interrupt Wake-up Function.................................................................................................. 107
Programming Considerations............................................................................................... 108
Low Voltage Detector – LVD........................................................................ 109
LVD Register........................................................................................................................ 109
LVD Operation.......................................................................................................................110
DC/DC Converter...........................................................................................110
DC/DC Converter Register....................................................................................................111
Configuration Options...................................................................................112
Application Circuits.......................................................................................112
Instruction Set................................................................................................113
Introduction...........................................................................................................................113
Instruction Timing..................................................................................................................113
Moving and Transferring Data...............................................................................................113
Arithmetic Operations............................................................................................................113
Logical and Rotate Operation...............................................................................................114
Branches and Control Transfer.............................................................................................114
Bit Operations.......................................................................................................................114
Table Read Operations.........................................................................................................114
Other Operations...................................................................................................................114
Instruction Set Summary..............................................................................115
Table Conventions.................................................................................................................115
Instruction Definition.....................................................................................117
Package Information.................................................................................... 126
16-pin NSOP (150mil) Outline Dimensions.......................................................................... 127
Rev. 1.00
5
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Features
CPU Features
• Operating Voltage:
♦♦ fSYS= 4MHz: 2.0V~3.3V
♦♦ fSYS= 8MHz: 2.2V~3.3V
♦♦ fSYS= 12MHz: 2.7V~3.3V
• Power down and wake-up functions to reduce power consumption
• Three oscillators
♦♦ External crystal – HXT
♦♦ Internal RC – HIRC
♦♦ Internal 32kHz RC – LIRC
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• Fully integrated internal 8MHz oscillator requires no external components
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• 8 subroutine nesting levels
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: up to
16
• RAM Data Memory: up to 128×8
• EEPROM Memory: 64×8
• Watchdog Timer function
• Up to 13 bidirectional I/O lines
• Two external interrupt lines shared with I/O pins
• Multiple Timer Module for time measure, input capture, compare match output, PWM output or
single pulse output functions
• Comparator function
• Dual Time-Base functions for generation of fixed time interrupt signals
• Low voltage reset function
• Low voltage detect function
• 4 channels 12-bit resolution A/D converter
• Package types: 16-pin NSOP
Rev. 1.00
6
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
General Description
The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers.
Offering users the convenience of Flash Memory multi-programming features, these devices also
include a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog features include a multi-channel 12-bit A/D converter and a comparator functions. Multiple
and extremely flexible Timer Modules provide timing, pulse generation and PWM generation
functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low
Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable
operation is maintained in hostile electrical environments.
A full choice of HXT, HIRC and LIRC oscillator functions are provided including a fully integrated
system oscillator which requires no external components for its implementation. The ability to
operate and switch dynamically between a range of operating modes using different clock sources
gives users the ability to optimise microcontroller operation and minimize power consumption.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the devices will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
Selection Table
Most features are common to all devices. The main features distinguishing them are memory
capacity and the A/D Converter. The following table summarises the main features of each device.
Part No.
Program
Data
Data
External
A/D
I/O
Memory Memory EEPROM
Interrupt Converter
16-bit Timer
Module
Comparator
Time
Stacks Package
Base
HT66F016L
1k×16
64×8
64×8
13
2
12-bit×4
CTM×1
STM×1
1
2
8
16NSOP
HT66F017L
2k×16
128×8
64×8
13
2
12-bit×4
CTM×1
STM×1
1
2
8
16NSOP
Note: As devices exist in more than one package format, the table reflects the situation for the package
with the most pins.
Rev. 1.00
7
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Block Diagram
„ …
† €  „ …
† 
ƒ
€  ­ €    € € ‚   ­ €
‚  Pin Assignment
PB�/CX_�
PB1/[TCK0/TP1]
PB0/[TP0]
PA�/INT0/TCK1/TP0/CX_1/AN�
PA�/[INT0]/[TCK1]/[TP0]/CX_0/AN�/ICPDA/OCDSDA
PA1/C-/AN1/VREF
PA0/C+/AN0
VSS/AVSS
1
16
�
15
�
1�
�
1�
5
1�
6
11
7
10
8
9
PB�
PB�
PA7/[TCK0/TP1]/ICPCK/OCDSCK
PA�/[INT1]/TCK0/TP1
PA5/INT1/[TP0]/OSC�
PA6/[TCK0/TP1]/OSC1
VDD/AVDD/VOUT
LX
HT66F016L/HT66F017L
16 NSOP-A
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
“/” sign can be used for higher priority.
3. VDD and AVDD means the VDD and AVDD are the double bonding.
4. VSS and AVSS means the VSS and AVSS are the double bonding.
Rev. 1.00
8
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name,
e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are
also shared with other function such as the Analog to Digital Converter, Timer Module pins etc.
The function of each pin is listed in the following table, however the details behind how each pin is
configured is contained in other sections of the datasheet.
The following tables only include the pins which are directly related to the MCU. The pin
descriptions of the additional peripheral functions are located at the end of the datasheet along with
the relevant peripheral function functional description.
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PAWU
PAPU
ST
CMOS
—
PA0~PA7
Port A
PB0~PB4
Port B
PBPU
ST
CMOS
AN0~AN3
A/D Converter Input
ACERL
AN
—
PA0~PA3
—
VREF
A/D Converter Reference Input ADCR1
AN
—
PA1
C-
Comparator Input
CPC
AN
—
PA1
C+
Comparator Input
CPC
AN
—
PA0
CX_0, CX_1, CX_2 Comparator Output
CPC
—
TCK0
TM0 Input
PRM
ST
TCK1
TM1 Input
PRM
ST
TP0
TM0 I/O
PRM
ST
CMOS PA3 or PB0 or PA5 or PA2
TP1
TM1 I/O
CMOS PA4 or PB1 or PA6 or PA7
CMOS PA2, PA3, PB2
—
PA4 or PB1 or PA6 or PA7
—
PA3 or PA2
PRM
ST
ST
—
PA3 or PA2
—
PA5 or PA4
INT0
External Interrupt 0
INTC0
INTEG
INT1
External Interrupt 1
INTC2
INTEG
ST
OSC1
HXT Pin
CO
HXT
—
PA6
OSC2
HXT Pin
CO
—
HXT
PA5
ICPCK
ICP Clock Pin
—
ST
—
PA7
ICPDA
ICP Data/Address Pin
—
ST
OCDSCK
OCDS Clock Pin
—
ST
OCDSDA
OCDS Data/Address Pin
—
ST
LX
External Inductor Connection
Pin for DC/DC Converter
—
PWR
—
—
VOUT
DC/DC Converter Voltage
Output*
—
PWR
—
—
CMOS PA2
—
PA7
CMOS PA2
VDD
Power Supply*
—
PWR
—
—
AVDD
A/D Converter Power Supply*
—
PWR
—
—
VSS
Ground**
—
PWR
—
—
AVSS
A/D Converter Ground**
—
PWR
—
—
Note: I/T: Input type
O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
AN: Analog input pin
HXT: High frequency crystal oscillator
*: The AVDD and VOUT pins are bonded together internally with VDD.
**: The AVSS pin is bonded together internally with VSS.
Rev. 1.00
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July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOH Total.....................................................................................................................................-80mA
IOL Total...................................................................................................................................... 80mA
Total Power Dissipation ......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
D.C. Characteristics
Ta= 25˚C
Symbol
VDD
Parameter
Operating Voltage (HXT)
Test Conditions
—
2V
3V
IDD1
Operating Current (HXT),
(fSYS= fH)
2.2V
3V
3V
3.3V
IDD2
IDD3
Min.
Typ.
Max.
Unit
fSYS= 4MHz
2.0
—
3.3
V
fSYS= 8MHz
2.0
—
3.3
V
fSYS= 12MHz
2.7
—
3.3
V
Conditions
VDD
No load, fH= 4MHz
No load, fH= 8MHz
No load, fH= 12MHz
—
0.4
0.6
mA
—
0.7
1.1
mA
—
0.5
0.8
mA
—
1.0
1.5
mA
—
1.5
2.5
mA
—
2.0
3.0
mA
—
1.1
(TBC)
1.6
(TBC)
mA
Operating Current (HIRC),
Normal Mode, fSYS= fH
2V
3V
—
1.4
2.0
mA
Operating Current (LIRC),
(fSYS= fL= fLIRC, fSUB= fLIRC)
2V
—
5
10
µA
3V
No load, fH= 8MHz
No load, fSYS= fLIRC
—
10
20
µA
—
1.00
2.00
µA
IIDLE0
IDLE0 Mode Standby Current
(LIRC On)
2.2V
IIDLE11
IDLE1 Mode Standby Current
(HXT)
2.0V
IIDLE12
IDLE1 Mode Standby Current
(HXT)
2.2V
IIDLE121
IDLE1 Mode Standby Current
(HIRC)
2.2V
3V
—
IIDLE13
IDLE1 Mode Standby Current
(HXT)
3V
—
ISLEEP1
SLEEP1 Mode Standby Current
(LIRC On)
Rev. 1.00
3V
3V
3V
3.3V
2.2V
3V
No load
No load, fSYS= 4MHz on
No load, fSYS= 8MHz on
No load, fSYS= 8MHz on
No load, fSYS= 12MHz on
No load
10
—
1.30
3.00
µA
—
0.20
0.40
mA
—
0.40
0.80
mA
—
0.25
0.50
mA
—
0.50
1.00
mA
—
0.7
(TBC)
1.0
(TBC)
mA
0.9
1.3
mA
0.60
1.20
mA
—
0.80
1.60
mA
—
1.00
3.00
µA
—
1.30
5.00
µA
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage for I/O Ports
or Input Pins
—
—
0
—
0.2VDD
V
VIH
Input High Voltage for I/O Ports
or Input Pins
—
—
0.8VDD
—
VDD
V
IOL
I/O Port Sink Current
IOH
I/O Port, Source Current
RPH
Pull-high Resistance for I/O
Ports
2.2V
VOL= 0.1VDD
2
4
—
mA
3V
VOL= 0.1VDD
4
8
—
mA
2.2V
VOH= 0.9VDD
−1
−2
—
mA
3V
VOH= 0.9VDD
−2
−4
—
mA
30
100
200
kΩ
20
60
100
kΩ
2.2V
—
3V
A.C. Characteristics
Ta= 25˚C
Symbol
Parameter
Test Condition
VDD
Condition
2.0~3.3V
fCPU
Operating Clock
—
2.0~3.3V
2.7~3.3V
2.0~3.3V
fSYS
System clock (HXT)
fHIRC
System Clock (HIRC)
tHIRCST
HIRC stable time after enabled
2.0~3.3V
—
2.7~3.3V
2.0~3.3V
Ta= -40°C to 85°C
2.0~3.3V
Ta= -40°C to 85°C
2.0V~3.3V Ta= 25°C
Min.
Typ.
Max.
Unit
DC
—
4
MHz
DC
—
8
MHz
DC
—
12
MHz
0.4
—
4
MHz
0.4
—
8
MHz
0.4
—
12
MHz
-2%
8MHz
+2%
MHz
—
—
300
μs
-10%
32
+10%
kHz
fLIRC
System Clock (LIRC)
-30%
32
+60%
kHz
tTCK
TCKn Input Pulse Width
—
—
0.3
—
—
μs
tINT
Interrupt Pulse Width
—
—
10
—
—
μs
tEERD
EEPROM Read Time
—
—
—
2
4
tSYS
tEEWR
EEPROM Write Time
—
—
—
2
4
ms
System Start-up Timer Period
(Wake-up From HALT, fSYS Off at
HALT state)
—
fSYS= fHXT
128
—
—
tSYS
—
fSYS= fHIRC
16
—
—
tSYS
—
fSYS= fLIRC
2
—
—
tSYS
tSST
tRSTD
2.0V~3.3V Ta= -40°C to 85°C
System Start-up Timer Period
(Wake-up From HALT, fSYS On at
HALT state)
—
—
2
—
—
tSYS
System Reset Delay Time
(Power On Reset)
—
—
25
50
100
ms
System Reset Delay Time
(Any Reset except Power On Reset)
—
—
8.3
16.7
33.3
ms
Note: 1. tSYS= 1/fSYS; tSUB = 1/fSUB
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Rev. 1.00
11
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
LVD & LVR Electrical Characteristics
Ta= 25˚C
Symbol
Parameter
Test Conditions
VDD
VLVR1
VLVR2
Conditions
LVR Enable, 1.8V option
Low Voltage Reset Voltage
—
LVR Enable, 2.0V option
Min.
Typ.
Max.
Unit
1.7
(TBC)
1.8
(TBC)
1.9
(TBC)
V
−5%×
Typ.
2.0
V
VLVR3
LVR Enable, 2.4V option
VLVR4
LVR Enable, 2.7V option
VLVD1
LVDEN= 1, VLVD= 2.0V
2.0
V
VLVD2
LVDEN= 1, VLVD= 2.2V
2.2
V
VLVD3
LVDEN= 1, VLVD= 2.4V
2.4
V
VLVD4
LVDEN= 1, VLVD= 2.6V
2.6
VLVD5
Low Voltage Detector Voltage
—
LVDEN= 1, VLVD= 2.8V
−5%×
Typ.
2.4
−5%×
Typ.
2.7
2.8
+5%×
Typ.
V
V
V
V
VLVD6
LVDEN= 1, VLVD= 3.0V
3.0
V
VLVD7
LVDEN= 1, VLVD= 3.1V
3.1
V
VLVD8
LVDEN= 1, VLVD= 3.2V
3.2
LVR enable, LVDEN= 0
—
40
µA
40
70
µA
240
480
µs
90
µs
ILV
—
—
tLVR
Low Voltage Width to Reset
—
—
120
tLVD
Low Voltage Width to Interrupt
—
—
20
45
tLVDS
LVDO Stable Time
—
tSRESET
Software Reset Width to Reset
—
Rev. 1.00
LVR enable, LVDEN= 1
For LVD off → on
—
12
V
70
Additional Power Consumption
if LVD is Used
15
—
—
µs
45
90
120
µs
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
ADC Characteristics
Ta= 25˚C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
AVDD
A/D Converter Operating Voltage
—
—
2.2
—
3.3
V
VADI
A/D Converter Input Voltage
—
—
0
—
VREF
V
VREF
A/D Converter Reference Voltage
—
—
2
—
AVDD
V
VBG
Reference with Buffer Voltage
—
—
-3%
1.09
+3%
V
-3
—
+3
LSB
DNL1
Differential Non-linearity
2.2V~ VREF= AVDD= VDD
3.0V tADCK= 0.5μs, Ta= 25˚C
DNL2
Differential Non-linearity
2.2V~ VREF= AVDD= VDD,
3.0V tADCK= 0.5μs, Ta= -40˚C~85˚C
-4
—
+4
LSB
INL1
Integral Non-linearity
2.2V~ VREF= AVDD= VDD
3.0V tADC= 0.5μs, Ta= 25˚C
-4
—
+4
LSB
INL2
Integral Non-linearity
2.2V~ VREF= AVDD= VDD
3.0V tADCK= 0.5μs, Ta= -40˚C~85˚C
-8
—
+8
LSB
IADC
Additional Power Consumption if
A/D Converter is Used
2.2V
No load (tADCK= 0.5μs )
—
0.5
1.0
mA
3V
No load (tADCK= 0.5μs )
—
0.9
1.35
mA
I109
Additional Power Consumption if
1.09V Reference with Buffer is used
—
—
—
200
300
μA
tADCK
A/D Converter Clock Period
—
—
0.5
—
10
μs
tADC
A/D Conversion Time
(Include Sample and Hold Time)
—
—
16
—
tADCK
tADS
A/D Converter Sampling Time
—
—
—
4
—
tADCK
tON2ST
A/D Converter On-to-Start Time
—
—
2
—
—
μs
tBGS
VBG Turn on Stable Time
—
—
10
—
—
ms
12-bit ADC
Comparator Electrical Characteristics
Ta= 25˚C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VCMP
Comparator Operating Voltage
—
—
2.2
—
3.3
V
ICMP
Comparator Operating Current
3V
—
—
37
56
µA
VCMPOS
Comparator Input Offset Voltage
—
—
−10
—
+10
mV
VHYS
Hysteresis Width
—
—
20
40
60
mV
VCM
Comparator Common Mode
Voltage Range
—
—
VSS
—
VDD −
1.4V
V
AOL
Comparator Open Loop Gain
—
—
60
80
—
dB
tPD
Comparator Response Time
—
With 100mV overdrive
(Note)
—
370
560
ns
Note: Measured with comparator one input pin at VCM = (VDD−1.4)/2 while the other pin input transition from VSS
to (VCM +100mV) or from VDD to (VCM -100mV).
Rev. 1.00
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July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
DC/DC Converter Electrical Characteristics
Ta= 25˚C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VBAT
Battery Input Voltage Range
─
─
0.9
─
1.8
V
LIN
Input Inductor Value
─
─
─
2.2
─
μH
RIL
Inductor DC Resistance
─
─
─
─
0.5
Ω
CIN
Input Capacitor Value
─
─
─
10
─
μF
-5%×
Typ.
2.0V
2.2V
2.4V
2.7V
2.85V
3.0V
3.15V
3.3V
+5%×
Typ.
V
─
%
VOUT
Output Voltage Range
ΔVOUT
Output Load Regulation
─
VOUT= 2.0V
VOUT= 2.2V
VOUT= 2.4V
VOUT= 2.7V
VOUT= 2.85V
VOUT= 3.0V
VOUT= 3.15V
VOUT= 3.3V
─
VOUT= 2.0V, 1 to 45 mA
─
±2
─
VOUT= 3.0V, 1 to 30 mA
─
±2
─
%
VOUT= 2.0V
VOUT= 2.2V
VOUT= 2.4V
VOUT= 2.7V
VOUT= 2.85V
VOUT= 3.0V
VOUT= 3.15V
VOUT= 3.3V
─
45
41
38
33
31
30
28
27
mA
mW
IOUT
Output Current (based on output
power spec)
─
POUT
Output Power
─
IQ
Quiescent Current
─
fDC-DC
Clock Frequency
─
IDCLOAD
Maximum DC Load Current During
Startup
─
COUT
Capacitance Connect to Output
─
TSTART
DC to DC Start-up Time
─
─
─
─
─
90
─
80
120
μA
─
0.5
1.0
1.5
MHz
─
─
─
1
mA
─
0.8
1.0
2.0
μF
─
1
─
ms
VFB= 1.4V, VOUT= 3.3V
VBAT= 0.9V, VOUT= 2.2V
Power on Reset Electrical Characteristics
Ta=25˚C
Symbol
Test Conditions
Parameter
VDD
Condition
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to ensure Power-on Reset
—
—
—
—
100
mV
RPOR AC
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD to remain at VPOR to
ensure Power-on Reset
—
—
1
—
—
ms
Rev. 1.00
14
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
ADC Internal Reference Voltage (VBG) Characteristic Curve
VBG Curve
Bandgap Voltage
1.12
1.11
2.2V
2.4V
2.7V
3.3V
1.1
1.09
1.08
1.07
-45℃
25℃
90℃
Operating Temperature
System Architecture
A key factor in the high-performance features of the Holtek range of is attributed to their internal
system architecture. The range of devices take advantage of the usual features found within RISC providing increased speed of operation and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and instruction execution are overlapped, hence
instructions are effectively executed in one cycle, with the exception of branch or call instructions.
An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic
operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal
data path is simplified by moving data through the Accumulator and the ALU. Certain internal
registers are implemented in the Data Memory and can be directly or indirectly addressed. The
simple addressing methods of these registers along with additional architectural features ensure that
a minimum of external components is required to provide a functional I/O and A/D control system
with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume
production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, HIRC or LIRC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the ensures that instructions are effectively executed in
one instruction cycle. The exception to this are instructions here the contents of the Program Counter
are changed, such as subroutine calls or jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
Rev. 1.00
15
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU


   
   
System Clocking and Pipelining
  €
€
 ­ €   
   ­
   
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as ″JMP″ or ″CALL″ that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter
Low Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition
has been met, the next instruction, which has already been fetched during the present instruction
execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Device
Program Counter
High Byte
Low Byte (PCL Register)
HT66F016L
PC9~PC8
PCL7~PCL0
HT66F017L
PC10~PC8
PCL7~PCL0
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Rev. 1.00
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack has multiple levels depending upon the device and is neither part of the data nor part of
the program space, and is neither readable nor writeable. The activated level is indexed by the Stack
Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal,
the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an
interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to
its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the
stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overflow, the first Program Counter save in the stack will be lost.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
C o u n te r
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l 8
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the that carries out arithmetic and logic
operations of the instruction set. Connected to the main data bus, the ALU receives related
instruction codes and performs the required arithmetic or logical operations after which the result
will be placed in the specified register. As these ALU calculation or operations may result in carry,
borrow or other status changes, the status register will be correspondingly updated to reflect these
changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM,SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM,XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,SIZA, SDZA, CALL, RET, RETI
Rev. 1.00
17
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device
series the Program Memory is Flash type, which means it can be programmed and re-programmed
a large number of times, allowing the user the convenience of code modification on the same
device. By using the appropriate programming tools, these Flash devices offer users the flexibility to
conveniently debug and develop their applications while also offering a means of field programming
and updating.
Structure
The Program Memory has a capacity of up to 2K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupts entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
Device
Capacity
HT66F016L
1K×16
HT66F017L
2K×16
HT66F017L
HT66F016L
0000H
0000H
Reset
000�H
000�H
Interr�pt Vector
Interr�pt Vector
00��H
00��H
0�FFH
Reset
16 bits
07FFH
16 bits
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Rev. 1.00
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July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the ″TABRD[m]″ or ″TABRDL[m]″ instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as ″0″.
The accompanying diagram illustrates the addressing data flow of the look-up table.
A d d re s s
L a s t p a g e o r
T B H P R e g is te r
T B L P R e g is te r
D a ta
1 6 b its
R e g is te r T B L H
U s e r S e le c te d
R e g is te r
H ig h B y te
L o w B y te
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is ″700H″ which refers to the start
address of the last page within the 2K words Program Memory of the device. The table pointer is
setup here to have an initial value of ″06H″. This will ensure that the first data read from the data
table will be at the Program Memory address ″706H″ or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the present page if the
″TABRD [m]″ instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the ″TABRD [m]″ instruction is
executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.00
19
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Table Read Program Example
tempreg1db ?
tempreg2db ?
:
:
mov a,06h mov tblp,a mov a,07h mov tbhp,a
:
:
tabrd tempreg1 ; temporary register #1
; temporary register #2
; transfers value in table referenced by table pointer data at program
; memory address ″706H″ transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
; initialise low table pointer - note that this address
; is referenced
; initialise high table pointer
tabrd tempreg2 ;
;
;
;
:
:
org 700h ;
transfers value in table referenced by table pointer data at program
memory address ″705H″ transferred to tempreg2 and TBLH in this
example the data ″1AH″ is transferred to tempreg1 and data ″0FH″ to
register tempreg2
sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
In Circuit Programming
The provision of Flash type Program Memory provides the user with a means of convenient and
easy upgrades and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing
their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage. This enables product manufacturers to easily
keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device.
Holtek Writer Pins
MCU Programming Pins
Pin Description
ICPDA
PA2
Programming Serial Data
ICPCK
PA7
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data
is downloaded and uploaded serially on a single pin with an additional line for the clock. Two
additional lines are required for the power supply and one line for the reset. The technical details
regarding the in-circuit programming of the devices are beyond the scope of this document and will
be supplied in supplementary literature.
During the programming process, taking control of the PA2 and PA7 pins for data and clock
programming purposes. The user must there take care to ensure that no other outputs are connected
to these two pins.
Rev. 1.00
20
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
M C U
P r o g r a m m in g P in s
W r ite r
C o n n e c to r S ig n a ls
V D D
V D D
IC P D A
P A 2
IC P C K
P A 7
V S S
V S S
*
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater
than 1kΩ or the capacitance of * must be less than 1nF.
On-Chip Debug Support – OCDS
There is an EV chip which is used to emulate the HT66F01xL devices series. The EV chip device
also provides an “On-Chip Debug” function to debug the devices during the development process.
The EV chip and the actual MCU devices are almost functionally compatible except for “OnChip Debug” function. Users can use the EV chip device to emulate the real chip device behavior
by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The
OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS
clock input pin. When users use the EV chip for debugging, other functions which are shared with
the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip.
However, the two OCDS pins which are pin-shared with the ICP programming pins are still used
as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the
corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.
Rev. 1.00
Holtek e-Link Pins
EV Chip Pins
OCDSDA
OCDSDA
On-Chip Debug Support Data/Address input/output
Pin Description
OCDSCK
OCDSCK
On-Chip Debug Support Clock input
VDD
VDD
Power Supply
GND
VSS
Ground
21
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation.
Device
Capacity
Bank 0
Bank 1
HT66F016L
64×8
80H~BFH
Unimplemented
128×8
80H~FFH
Unimplemented
HT66F017L
General Purpose Data Memory Structure
Note: 80H~BFH for HT66F016L
80H~FFH for HT66F017L
General Purpose Data Memory Structure
General Purpose Data Memory Structure
The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for
general purpose use. All locations within this area are read and write accessible under program control.
The overall Data Memory is subdivided into two banks for all the devices. The Special Purpose Data
Memory registers are accessible in all banks, with the exception of the EEC register at address 40H,
which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved
by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices
is the address 00H.
Rev. 1.00
22
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
00H
01H
0�H
0�H
0�H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1�H
1�H
1�H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Bank 0 Bank 1
IAR0
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
SMOD
LVDC
INTEG
INTC0
INTC1
INTC�
MFI0
MFI1
MFI�
PA
PAC
PAPU
PAWU
PRM
TMPC
WDTC
TBC
Un�sed
Un�sed
EEA
EED
Bank 0 Bank 1
�0H
ADRL
�1H
ADRH
��H
ADCR0
��H
ADCR1
��H
ACERL
CPC
�5H
�6H
CTRL
LVRC
�7H
TM0C0
�8H
�9H
TM0C1
�AH
TM0DL
TM0DH
�BH
TM0AL
�CH
TM0AH
�DH
TM0RP
�EH
�FH
TM1C0
�0H
TM1C1
�1H
TM1DL
��H
TM1DH
��H
TM1AL
��H
TM1AH
TM1RP
�5H
�6H
:
Un�sed
�AH
�BH
DCC
�CH
Un�sed
�DH
PB
PBC
�EH
�FH
PBPU
�0H Un�sed EEC
�1H
:
Un�sed
7FH
: Un�sed� read as 00H
HT66F016L/HT66F017L
Special Purpose Data Memory
Rev. 1.00
23
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section,
however several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in0. no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of ″00H″ and writing to the
registers indirectly will result in no operation.
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks according to BP register. Direct Addressing can only be used with Bank
0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for this series of
devices, the Memory Pointers, MP0 and MP1, are both 8-bit registers and used to access the Data
Memory together with their corresponding indirect addressing registers IAR0 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data .section data
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 'code'
org00h
start:
mov a,04h; setup size of block
mov block,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp0,a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by MP0
inc mp0; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific
RAM addresses.
Rev. 1.00
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Bank Pointer – BP
For this series of devices, the Data Memory is divided into two banks. Selecting the required Data
Memory area is achieved using the Bank Pointer. Bit 0 is used to select Data Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power
Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the
Special Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within any bank. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing
data from banks other than Bank 0 must be implemented using indirect addressing.
BP Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DMBP0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as “0”
Bit 0DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the ″INC″ or ″DEC″ instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
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0.9V Battery Flash A/D Type 8-Bit MCU
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the ″CLR WDT″ or ″HALT″ instruction. The PDF flag is affected only by executing
the ″HALT″ or ″CLR WDT″ instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
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STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
—
—
R
R
R/W
R/W
R/W
R/W
POR
—
—
0
0
x
x
x
x
"x" unknown
Bit 7, 6
Unimplemented, read as “0”
Bit 5TO: Watchdog Time-Out flag
0: After power up or executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred.
Bit 4PDF: Power down flag
0: After power up or executing the “CLR WDT” instruction
1: By executing the “HALT” instruction
Bit 3OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
C is also affected by a rotate through carry instruction.
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EEPROM Data Memory
The device contains an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is 64×8 bits for this series of devices. Unlike the Program
Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory
space and is therefore not directly addressable in the same way as the other types of memory. Read
and Write operations to the EEPROM are carried out in single byte operations using an address and
data register in Bank 0 and a single control register in Bank 1.
Device
All devices
Capacity
Address
64×8
00H ~ 3FH
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same was as any other
Special Function Register. The EEC register however, being located in Bank1, cannot be addressed
directly and can only be read from or written to indirectly using the MP1 Memory Pointer and
Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in
Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register,
BP, set to the value, 01H, before any operations on the EEC register are executed..
EEPROM Register List
Name
Bit
7
6
5
4
3
2
1
0
D0
EEA
—
—
D5
D4
D3
D2
D1
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
Bit
7
6
5
4
3
2
1
0
Name
—
—
D5
D4
D3
D2
D1
D0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
x
x
x
x
x
EEA Register
x
“x” unknown
Rev. 1.00
Bit 7~6
Unimplemented, read as “0”
Bit 5~0
Data EEPROM address
Data EEPROM address bit 5~bit 0
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EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x” unknown
Bit 7~0
Data EEPROM address
Data EEPROM address bit 7~bit 0
EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0
RD : EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The
WR and RD can not be set to “1” at the same time.
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0.9V Battery Flash A/D Type 8-Bit MCU
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
The EEPROM address of the data to be written must first be placed in the EEA register and the data
placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC
register must first be set high to enable the write function. After this, the WR bit in the EEC register
must be immediately set high to initiate a write cycle. These two instructions must be executed
consecutively. The global interrupt bit EMI should also first be cleared before implementing any
write operations, and then set again after the write cycle has started. Note that setting the WR bit
high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is
controlled using an internal timer whose operation is asynchronous to microcontroller system clock,
a certain time will elapse before the data will have been written into the EEPROM. Detecting when
the write cycle has finished can be implemented either by polling the WR bit in the EEC register or
by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically
cleared to zero by the microcontroller, informing the user that the data has been written to the
EEPROM. The application program can therefore poll the WR bit to determine when the write cycle
has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program. More details can be obtained in the Interrupt section.
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Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where
the EEPROM control register exist. Although certainly not necessary, consideration might be given
in the application program to the checking of the validity of new write data by a simple read back
process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high,
to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared
before a write cycle is executed and then re-enabled after the write cycle starts.
Programming Examples
Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
SET IAR1.1 SET IAR1.0 BACK:
SZ IAR1.0 JMP BACK
CLR IAR1 CLR BP
MOV A, EED MOV READ_DATA, A
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM read/write
; move read data to register
Writing data from the EEPROM – polling method
CLR EMI
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, EEPROM_DATA MOV EED, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
SET IAR1.3 SET IAR1.2 SET EMI
BACK:
SZ IAR1.2 JMP BACK
CLR IAR1 CLR BP
Rev. 1.00
; user defined address
; user defined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; Start Write Cycle - set WR bit - executed immediately
; after set WREN bit
; check for write cycle end
; disable EEPROM read/write
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0.9V Battery Flash A/D Type 8-Bit MCU
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through a combination of configuration options and registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external
components as well as fully integrated internal oscillators, requiring no external components,
are provided to form a wide range of both fast and slow system oscillators. All oscillator options
are selected through the configuration options. The higher frequency oscillators provide higher
performance but carry with it the disadvantage of higher power requirements, while the opposite
is of course true for the lower frequency oscillators. With the capability of dynamically switching
between fast and slow system clock, the device has the flexibility to optimize the performance/
power ratio, a feature especially important in power sensitive portable applications.
Type
Name
Freq.
400kHz~12MHz
Pins
External Crystal
HXT
OSC1/OSC2
Internal High Speed RC
HIRC
8MHz
—
Internal Low Speed RC
LIRC
32kHz
—
Oscillator Types
System Clock Configurations
There are methods of generating the system clock, two high speed oscillators and one low speed
oscillators. The high speed oscillators are the external crystal/ceramic oscillator - HXT and the
internal 8MHz RC oscillator - HIRC. The low speed oscillator is the internal 32kHz oscillator
- LIRC. Selecting whether the low or high speed oscillator is used as the system oscillator is
implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system
clock can be dynamically selected.
The actual source clock used for each of the high speed oscillator is chosen via configuration
options. The frequency of the slow speed or high speed system clock is also determined using the
HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be
made namely one high speed and one low speed system oscillators. It is not possible to choose a nooscillator selection for either the high or low speed oscillator. The OSC1 and OSC2 pins are used to
connect the external components for the external crystal.
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0.9V Battery Flash A/D Type 8-Bit MCU
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System Clock Configurations
External Crystal/Ceramic Oscillator – HXT
The External Crystal/ Ceramic System Oscillator is one of the high frequency oscillator choices,
which is selected via configuration option. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer′s specification.
     Crystal/Resonator Oscillator – HXT
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0.9V Battery Flash A/D Type 8-Bit MCU
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0pF
0pF
8MHz
0pF
0pF
4MHz
0pF
0pF
1MHz
100pF
100pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
High Speed Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, in a power supply range of 2.0V~3.3V and at
a temperature of -40˚C~85˚C degrees, the fixed oscillation frequency of the high speed internal
8MHz RC oscillator will have a tolerance within 2%. Note that if this internal system clock option
is selected as the high speed oscillator, as it requires no external pins for its operation, I/O pins PA6
and PA5 can only be used as normal I/O pins.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RC oscillator with a typical frequency of 32kHz at 3V, requiring no external components for its
implementation. Device trimming during the manufacturing process and the inclusion of internal
frequency compensation circuits are used to ensure that the influence of the power supply voltage,
temperature and process variations on the oscillation frequency are minimised. As a result, in
a power supply range of 2.0V~3.3V and at a temperature of 25˚C degrees, the fixed oscillation
frequency of 32kHz will have a tolerance within 10%.
Supplementary Oscillator
The low speed oscillator, in addition to providing a system clock source is also used to provide
a clock source to two other device functions. These are the Watchdog Timer and the Time Base
Interrupts.
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Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided these devices with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
The device has many different clock sources for both the CPU and peripheral function operation.
By providing the user with a wide range of clock options using configuration options and register
programming, a clock system can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or low frequency, fL, source,
and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed
system clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration
option. The low speed system clock source can be sourced from internal clock fL. The other choice,
which is a divided version of the high speed system oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the
Time Base clock, fTBC. Each of these internal clocks are sourced by the LIRC oscillators. The fSUB
clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred
to enable faster wake-up times.
High Speed Osci��ators
HXT
fH
6-stage Presca�er
HIRC
fH/�
fH/�
High Speed Osci��ator
Config�ration Options
fH/8
fH/16
fH/��
Low Speed Osci��ator
LIRC
fH/6�
fL
fLIRC
fSYS
fSUB
HLCLK�
CKS�~CKS0 bits
Fast Wake-�p from SLEEP Mode or
IDLE Mode Contro� (for HXT on��)
fS
WDT
fTBC
fTB
fSYS/�
Time Base
TBCK
System Clock Configurations
Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will
stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuits to use.
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System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to
conserve power.
Operation
Mode
Description
CPU
fSYS
fSUB
fS
fTBC
On
NORMAL Mode
On
fH~fH/64
On
On
SLOW Mode
On
fL
On
On
On
IDLE0 Mode
Off
Off
On
On
On
On
IDLE1 Mode
Off
On
On
On
SLEEP0 Mode
Off
Off
Off
Off
Off
SLEEP1 Mode
Off
Off
On
On
Off
• NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has
all of its functions operational and where the system clock is provided by one of the high speed
oscillators. This mode operates allowing the microcontroller to operate normally with a clock
source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The
high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio
being selected by the CKS2~LCKS0 and HLCLK bits in the SMOD register. Although a high
speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating
current.
• SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower
speed clock source. The clock source used will be from the low speed oscillators LIRC. Running
the microcontroller in this mode allows it to run with much lower operating currents. In the
SLOW Mode, the fH is off.
• SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit
in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and
fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the
LVDEN is must set to ″0″. If the LVDEN is set to ″1″, it won′t enter the SLEEP0 Mode.
• SLEEP1 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the bit, IDLEN, in
the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and
fS clocks will continue to operate if the LVDEN is 1 or the Watchdog Timer function is enabled
as its clock source is derived from the fSUB.
• IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in
the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode
the system oscillator will be inhibited from driving the CPU but some peripheral functions will
remain operational such as the Time Base and TMs. In the IDLE0 Mode, the system oscillator
will be stopped.
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0.9V Battery Flash A/D Type 8-Bit MCU
• IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in
the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode
the system oscillator will be inhibited from driving the CPU but may continue to provide a clock
source to keep some peripheral functions operational such as the Timer Base and TMs. In the
IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high
speed or low speed system oscillator.
Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
FSTEN
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
1
1
0
0
0
0
1
0
Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0”
000: fL (fLIRC)
001: fL (fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be the LIRC, a divided version of the
high speed system oscillator can also be chosen as the system clock source.
Bit 4FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fLIRC clock source is
initially used after the device wake up. When the bit is high, the fLIRC clock source can
be used as a temporary system clock to provide a faster wake up time as the fLIRC clock
is available.
Bit 3LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 1~2 clock cycles if the LIRC oscillator is used.
Bit 2HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to “0” by hardware when the devices are
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as “1” by the application program after
device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after
a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if
the HXT oscillator is used.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Bit 1IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
devices will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the devices will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0HLCLK: System clock selection
0: fH/2~fH/64 or fL
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the
system clock. When the bit is high the f H clock will be selected and if low the
fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock
to the fL clock and the fH clock will be automatically switched off to conserve power.
Fast Wake-up
To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system
clock source to the device will be stopped. However when the device is woken up again, it can take
a considerable time for the original system oscillator to restart, stabilise and allow normal operation
to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is
provided, which allows fSUB, namely the LIRC oscillator, to act as a temporary clock to first drive
the system until the original system oscillator has stabilised. As the clock source for the Fast Wakeup function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes.
When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect
because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the
FSTEN bit in the SMOD register.
If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up
function is enabled, then it will take one to two tSUB clock cycles of the LIRC oscillator for the
system to wake-up. The system will then initially run under the fSUB clock source until 128 HXT
clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch
over to operating from the HXT oscillator.
If the HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16
clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or
IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
System FSTEN
Oscillator
Bit
Wake-up Time
(SLEEP0 Mode)
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
128 HXT cycles
128 HXT cycles
1~2 HXT cycles
1
128 HXT cycles
1~2 fLIRC cycles (System runs first
with fLIRC for 128 HXT cycles and then
switches over to run with the HXT clock)
1~2 HXT cycles
HIRC
x
15~16 HIRC cycles 15~16 HIRC cycles
1~2 HIRC cycles
LIRC
x
1~2 LIRC cycles
1~2 LIRC cycles
0
HXT
1~2 LIRC cycles
Wake-Up Times
“x”: don’t care
Note that if the Watchdog Timer is disabled, which means that the LIRC is off, then there will be no
Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
­ €    
­ €    Operating Mode Switching and Wake-up
The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When
a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is
determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high
speed clock source will stop running to conserve power. When this happens it must be noted that the
fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other
internal functions such as the TMs. The accompanying flowchart shows what happens when the
device moves between the various operating modes.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLK bit to ″0″ and setting the CKS2~CKS0 bits to ″000″ or ″001″ in the SMOD register. This
will then use the low speed system oscillator which will consume less power. Users may decide to
do this for certain operations which do not require high performance and can subsequently reduce
power consumption.
The SLOW Mode is sourced from the the LIRC oscillators and therefore requires these oscillators
to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD
register.
  
   ­   ­       ­   ­  €‚ ƒ    ­   ­  €‚ ƒ    ­   ­  Rev. 1.00
40
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
  
     ­          ­   € ‚      ­   € ‚      ­   SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the
NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to
″1″ or HLCLK bit is ″0″, but CKS2~CKS0 is set to ″010″, ″011″, ″100″, ″101″, ″110″ or ″111″.
As a certain amount of time will be required for the high frequency clock to stabilise, the status of
the HTO bit is checked. The amount of time required for high speed system oscillator stabilization
depends upon which high speed system oscillator type is used.
Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the ″HALT″
instruction in the application program with the IDLEN bit in SMOD register equal to ″0″ and the
WDT and LVD both off. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the ″HALT″ instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the ″HALT″
instruction in the application program with the IDLEN bit in SMOD register equal to ″0″ and the
WDT or LVD on. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at the
″HALT″ instruction, but the WDT or LVD will remain with the clock source coming from the fSUB
clock.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the ″HALT″
instruction in the application program with the IDLEN bit in SMOD register equal to ″1″ and the
FSYSON bit in CTRL register equal to ″0″. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the ″HALT″
instruction, but the Time Base clock and fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the ″HALT″
instruction in the application program with the IDLEN bit in SMOD register equal to ″1″ and
the FSYSON bit in CTRL register equal to ″1″. When this instruction is executed under the with
conditions described above, the following will occur:
• The system clock and Time Base clock and fSUB clock will be on and the application program will
stop at the ″HALT″ instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 Mode, there are other considerations which must also be taken into account by the circuit
designer if the power consumption is to be minimised. Special attention must be made to the I/O pins
on the device. All high-impedance input pins must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations and result in increased current consumption.
This also applies to devices which have different package types, as there may be unbonbed pins.
These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the configuration options have enabled the LIRC oscillator.
In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system
oscillator, the additional standby current will also be perhaps in the order of several hundred microamps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external reset
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
″HALT″ instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the ″HALT″ instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the ″HALT″ instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
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0.9V Battery Flash A/D Type 8-Bit MCU
Programming Considerations
The high speed and low speed oscillators both use the same SST counter. For example, if the system is
woken up from the SLEEP0 Mode and both the HIRC and LIRC oscillators need to start-up from an
off state. The LIRC oscillator uses the SST counter after HIRC oscillator has finished its SST period.
• If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system
oscillator needs an SST period. The device will execute first instruction after HTO is ″1″. At this
time, the LIRC oscillator may not be stability. The same situation occurs in the power-on state.
The LIRC oscillator is not ready yet when the first instruction is executed.
• If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock
source is from HXT oscillator and FSTEN is ″1″, the system clock can be switched to the LIRC
oscillator after wake up.
• There are peripheral functions, such as TMs, for which the fSYS is used. If the system clock source
is switched from fH to fL, the clock source to the peripheral functions mentioned above will
change accordingly.
• The on/off condition of the LIRC oscillator depends upon whether the WDT function is enabled or
disabled.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by
the LIRC oscillator. The LIRC internal oscillator has an approximate period of 32kHz at a supply
voltage of 3V. However, it should be noted that this specified internal clock period can vary with
VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a
ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in
the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register together with the corresponding configuration option control the overall
operation of the Watchdog Timer.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3WE4~WE0: WDT function software control
If the WDT configuration option is ″always enable″:
10101 or 01010: WDT Enabled
Other values: Reset MCU
If the WDT configuration option is ″controlled by the WDT control register″:
10101: WDT Disabled
01010: WDT Enabled
Other values: Reset MCU
When these bits are changed by the environmental noise or software setting to reset
the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles
and the WRF bit in the CTRL register will be set to 1.
Bit 2~0
WS2, WS1, WS0: WDT time-out period selection
000: 28/fS
001: 210/fS
010: 212/fS
011: 214/fS
100: 215/fS
101: 216/fS
110: 217/fS
111: 218/fS
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
CTRL Register
Bit
7
6
5
4
3
2
Name
FSYSON
—
—
R/W
R/W
—
—
POR
0
—
—
—
1
0
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
R/W
x
0
0
″x″ unknown
Bit 7FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as “0”
Bit 2LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values.
This in effect acts like a software reset function. This bit can only be cleared to 0 by
the application program.
Bit 0WRF: WDT Control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application program.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This
is done using the clear watchdog instruction. If the program malfunctions for whatever reason,
jumps to an unknown location, or enters an endless loop, the clear watchdog instruction will not
be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the
device. The Watchdog Timer enable/disable control is selected using the configuration option. With
regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the
WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. If the
WDT configuration option is determined that the WDT function is always enabled, the WE4~WE0
bits still have effects on the WDT function. When the WE4~WE0 bits value is equal to 01010B or
10101B, the WDT function is enabled. However, if the WE4~WE0 bits are changed to any other
values except 01010B and 10101B, which is caused by the environmental noise or software setting,
it will reset the microcontroller after 2~3 LIRC clock cycles. If the WDT configuration option is
determined that the WDT function is controlled by the WDT control register, the WE4~WE0 values
can determine which mode the WDT operates in. The WDT function will be disabled when the
WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0
bits value is equal to 01010B. If the WE4~WE0 bits are set to any other values by the environmental
noise or software setting, except 01010B and 10101B, it will reset the device after 2~3 LIRC clock
cycles. After power on these bits will have the value of 01010B.
WDT Configuration Option
Always Enabled
Controlled by WDT Control
Register
WE4 ~ WE0 Bits
WDT Function
01010B or 10101B
Enable
Any other value
Reset MCU
10101B
Disable
01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single ″CLR WDT″ instruction to clear the WDT.
The maximum time out period is when the 218 division ratio is selected. As an example, with a
32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
WDTC Register
Reset MCU
WE4~WE0 bits
CLR
“CLR WDT”Instruction
LIRC
fS
fLIRC
8-stage Divider
fS/28
WS2~WS0
(fS/28 ~ fS/218)
WDT Prescaler
8-to-1 MUX
WDT Time-out
(28/fS ~ 218/fS)
Watchdog Timer
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
Another type of reset is when the Watchdog Timer overflows and resets the . All types of reset
operations result in different register conditions being setup. Another reset exists in the form of a
Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply
voltage falls below a certain threshold.
Reset Functions
There are several ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
• Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied
to the . As well as ensuring that the Program Memory begins execution from the first memory
address, a power-on reset also ensures that certain other registers are preset to known conditions.
All the I/O port and port control registers will power up in a high condition ensuring that all pins
will be first set to inputs.
Note: tRSTD is power-on delay, typical time=50ms
Power-on Reset Timing Chart
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0.9V Battery Flash A/D Type 8-Bit MCU
• Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply
voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing
the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL
register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C.
characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore
the low supply voltage and will not perform a reset function. The actual VLVR value is selected by
the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by
the environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock
cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the
register will have the value of 01010101B.
Note that the LVR function will be automatically disabled when the device enters the power
down mode.
Note: tRSTD is power-on delay, typical time=16.7ms
Low Voltage Reset Timing Chart
• Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a Power-on reset except
that the Watchdog time-out flag TO will be set to “1”.
Note: tRSTD is power-on delay, typical time=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart
• Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics
for tSST details.
Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC.
The tSST is 128 clock for HXT. The tSST is 1~2 clock for LIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0LVS7~LVS0: LVR Voltage Select
01010101B: 1.8V(default)
00110011B: 2.0V
10011001B: 2.4V
10101010B: 2.7V
Any other value: Generates MCU reset – LVRC register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined
LVR voltage values above, an MCU reset will be generated. The reset operation will
be activated after 2~3 LIRC clock cycles. In this situation the register contents will
remain the same after such a reset occurs.
Any register value, other than the four defined LVR values above, will also result in
the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC
clock cycles.However in this situation the register contents will be reset to the POR
value.
CTRL Register
Bit
7
6
5
4
3
2
Name
FSYSON
—
—
R/W
R/W
—
—
POR
0
—
—
—
1
0
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
R/W
x
0
0
″x″ unknown
Bit 7FSYSON: fSYS Control in IDLE Mode
Describe elsewhere.
Bit 6~3
Unimplemented, read as “0”
Bit 2LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values.
This in effect acts like a software reset function. This bit can only be cleared to 0 by the
application program.
Bit 0WRF: WDT Control register software reset flag
Describe elsewhere.
Rev. 1.00
49
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
RESET Conditions
0
0
Power-on reset
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
“u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer Modules
Timer Counter will be turned off
Input/Output Ports
I/O ports will be setup as inputs, and AN0~AN3 as A/D input pins
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the in different ways. To ensure
reliable continuation of normal program execution after a reset occurs, it is important to know what
condition the is in after a particular reset occurs. The following table describes how each type of
reset affects each of the internal registers. Note that where more than one package type exists the
table will reflect the situation for the larger package type.
HT66F017L
HT66F016L
Register
Reset
(Power On)
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(IDLE)*
MP0
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
●
●
---- ---0
---- ---0
---- ---0
---- ---u
ACC
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
●
●
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
●
---- -xxx
- - - - - uuu
- - - - - uuu
- - - - - uuu
---- --xx
- - - - - - uu
- - - - - - uu
- - - - - - uu
TBHP
TBHP
●
STATUS
●
●
--00 xxxx
- - uu uuuu
- - 1 u uuuu
- - 1 1 uuuu
SMOD
●
●
11 0 0 0 0 1 0
11 0 0 0 0 1 0
11 0 0 0 0 1 0
uuuu uuuu
LVDC
●
●
--00 -000
--00 -000
--00 -000
- - uu - uuu
INTEG
●
●
---- 0000
---- 0000
---- 0000
- - - - uuuu
INTC0
●
●
-000 0000
-000 0000
-000 0000
- uuu uuuu
INTC1
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
●
●
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI0
●
●
--00 --00
--00 --00
--00 --00
- - uu - - uu
Rev. 1.00
50
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
HT66F017L
HT66F016L
Register
Reset
(Power On)
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(IDLE)*
MFI1
●
●
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI2
●
●
--00 --00
--00 --00
--00 --00
- - uu - - uu
PA
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
●
●
- - - 1 1111
- - - 1 1111
- - - 1 1111
- - - u uuuu
PBC
●
●
- - - 1 1111
- - - 1 1111
- - - 1 1111
- - - u uuuu
PBPU
●
●
---0 0000
---0 0000
---0 0000
- - - u uuuu
PRM
●
●
0101 0000
0101 0000
0101 0000
uuuu uuuu
TMPC
●
●
---- --00
---- --00
---- --00
- - - - - - uu
WDTC
●
●
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
●
●
0 0 11 - 111
0 0 11 - 111
0 0 11 - 111
uuuu - uuu
EEC
●
●
---- 0000
---- 0000
---- 0000
- - - - uuuu
EEA
●
●
--00 0000
--00 0000
--00 0000
- - uu uuuu
EED
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADRL(ADRFS=0)
●
●
xxxx ----
xxxx ----
xxxx ----
uuuu - - - -
ADRL(ADRFS=1)
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH(ADRFS=0)
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH(ADRFS=1)
●
●
---- xxxx
---- xxxx
---- xxxx
- - - - uuuu
ADCR0
●
●
0 11 0 - - 0 0
0 11 0 - - 0 0
0 11 0 - - 0 0
uuu - uuuu
ADCR1
●
●
00-0 -000
00-0 -000
00-0 -000
uu - u - uuu
ACERL
●
●
- - - - 1111
- - - - 1111
- - - - 1111
- - - - uuuu
CPC
●
●
1000 00-1
1000 00-1
1000 00-1
uuuu uu - u
CTRL
●
●
0--- -x00
0--- -000
0--- -000
u - - - - uuu
LVRC
●
●
0101 0101
0101 0101
0101 0101
uuuu uuuu
TM0C0
●
●
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM0C1
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DH
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AH
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0RP
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1C0
●
●
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM1C1
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DH
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AH
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1RP
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
DCC
●
●
--00 0000
--00 0000
--00 0000
- - uu uuuu
Note: ″u″ stands for unchanged
″x″ stands for unknown
″−″ stands for unimplemented
Rev. 1.00
51
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA and PB. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction ″MOV A,[m]″, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
I/O Register List
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
D7
D6
D5
D4
D3
D2
D1
D0
PAPU
D7
D6
D5
D4
D3
D2
D1
D0
PAC
D7
D6
D5
D4
D3
D2
D1
D0
PA
D7
D6
D5
D4
D3
D2
D1
D0
PBPU
—
—
—
D4
D3
D2
D1
D0
PB
—
—
—
D4
D3
D2
D1
D0
PBC
—
—
—
D4
D3
D2
D1
D0
PRM
PRML3
PRML2
PRML1
PRML0
PRMS3
PRMS2
PRMS1
PRMS0
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using the register PAPU and PBPU, and are implemented using weak
PMOS transistors.
PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
I/O Port A bit 7~bit 0 Pull-high Control
0: Disable
1: Enable
52
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
PBPU Register
Bit
7
6
5
4
Name
─
─
─
D4
D3
D2
D1
D0
R/W
─
─
─
R/W
R/W
R/W
R/W
R/W
POR
─
─
─
0
0
0
0
0
Bit 7~5
″─″ Unimplemented, read as 0
Bit 4~0
I/O Port B bit 4~bit 0 Pull-high Control
0: Disable
1: Enable
3
2
1
0
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0PAWU: Port A bit 7~bit 0 Wake-up Control
0: Disable
1: Enable
I/O Port Control Registers
The I/O port has its own control register known as PAC and PBC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O port is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a ″1″. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a ″0″,
the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7~0
Rev. 1.00
I/O Port A bit 7 ~ bit 0 Input/Output Control
0: Output
1: Input
53
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
PBC Register
Bit
7
6
5
4
3
Name
─
─
─
D4
D3
D2
D1
D0
R/W
─
─
─
R/W
R/W
R/W
R/W
R/W
POR
─
─
─
1
1
1
1
1
Bit 7~5
″─″ Unimplemented, read as 0
Bit 4~0
I/O Port A bit 4 ~ bit 0 Input/Output Control
0: Output
1: Input
2
1
0
Pin-remapping Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but
by supplying pins with multi-functions, many of these difficulties can be overcome. The way in
which the pin function of each pin is selected is different for each function and a priority order is
established where more than one pin function is selected simultaneously. Additionally there is a
PRM register to establish certain pin functions. Generally speaking, the analog function has higher
priority than the digital function. However, if more than two analog functions are enabled and the
analog signal input comes from the same external pin, the analog input will be internally connected
to all of these active analog functional modules.
Pin-remapping Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes.
PRM Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
PRML3
PRML2
PRML1
PRML0
PRMS3
PRMS2
PRMS1
PRMS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
0
0
Bit 7~4PRML3~PRML0: pin-remapping function lock bits (default: 0101)
1010: PRM register write operation is enabled
Others: PRM register write operation is disabled
Bit 3PRMS3: INT1 pin-remapping function selection bit
0: INT1 on PA5
1: INT1 on PA4
Bit 2PRMS2: INT0/TCK1 pin-remapping function selection bit
0: INT0 on PA3, TCK1 on PA3
1: INT0 on PA2, TCK1 on PA2
Bit 1~0PRMS1~PRMS0: pin-remapping function selection bits
00: TP0 on PA3, TP1/TCK0 on PA4
01: TP0 on PB0, TP1/TCK0 on PB1
10: TP0 on PA5, TP1/TCK0 on PA6
11: TP0 on PA2, TP1/TCK0 on PA7
Rev. 1.00
54
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.

 
    
Generic Input/Output Structure
€

€
‚
€
‚
€
­     
A/D Input/Output Structure
Rev. 1.00
55
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set high. This means that all I/O pins will default
to an input state, the level of which depends on the other connected circuitry and whether pullhigh selections have been chosen. If the port control registers, PAC and PBC, are then programmed
to setup some pins as outputs, these output pins will have an initial high output value unless the
associated port data registers, PA and PB, are first programmed. Selecting which pins are inputs and
which are outputs can be achieved byte-wide by loading the correct values into the appropriate port
control register or by programming individual bits in the port control register using the ″SET [m].
i″ and ″CLR [m].i″ instructions. Note that when using these bit control instructions, a read-modifywrite operation takes place. The microcontroller must first read in the data on the entire port, modify
it to the required new bit values and then rewrite this data back to the output ports.
The power-on reset condition of the A/D converter control registers ensures that any A/D input pins
- which are always shared with other I/O functions - will be setup as analog inputs after a reset.
Although these pins will be configured as A/D inputs after a reset, the A/D converter will not be
switched on. It is therefore important to note that if it is required to use these pins as I/O digital
input pins or as other functions, the A/D converter control registers must be correctly programmed
to remove the A/D function. Note also that as the A/D channel is enabled, any internal pull-high
resistor connections will be removed.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Rev. 1.00
56
July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions each device includes several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users are
provided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Compact and Standard TM sections.
Introduction
The devices contain two TMs with each TM having a reference name of TM0 and TM1. Each
individual TM can be categorised as a certain type, namely Compact Type TM (CTM) or Standard
Type TM (STM). Although similar in nature, the different TM types vary in their feature complexity.
The common features to all of the Compact and Standard TMs will be described in this section and
the detailed operation regarding each of the TM types will be described in separate sections. The
main features and differences between the two types of TMs are summarised in the accompanying
table.
Function
CTM
STM
Timer/Counter
√
√
I/P Capture
─
√
Compare Match Output
√
√
PWM Channels
1
1
Single Pulse Output
─
1
Edge
Edge
Duty or Period
Duty or Period
PWM Alignment
PWM Adjustment Period & Duty
TM Function Summary
Each device in the series contains a Compact Type and Standard Type TM units which are shown in
the table together with their individual reference name, TM0 and TM1.
Device
TM0
TM1
HT66F016L / HT66F017L
16-bit CTM
16-bit STM
TM Name/Type Reference
TM Operation
The two different types of TM offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the TM output pin. The internal TM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.
Rev. 1.00
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HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources.
The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM
control registers. The clock source can be a ratio of either the system clock fSYS or the internal high
clock fH, the fTBC clock source or the external TCKn pin. The TCKn pin clock source is used to allow
an external signal to drive the TM as an external clock source or for event counting.
TM Interrupts
The Compact and Standard type TMs each have two internal interrupts, one for each of the internal
comparator A or comparator P, which generate a TM interrupt when a compare match condition
occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the
state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM
input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in
the TMnC0 register. This external TM input pin allows an external clock source to drive the internal
TM. This external TM input pin is shared with other functions but will be connected to the internal
TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a
rising or falling active edge.
The TMs each have one output pin with the label TPn. When the TM is in the Compare Match
Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle
when a compare match situation occurs. The external TPn output pin is also the pin where the
TM generates the PWM output waveform. The TPn pin acts as an input when the TM is setup to
operate in the Capture Input Mode. As the TPn pins are pin-shared with other functions, the TPn
pin function is enabled or disabled according to the internal TM on/off control, operation mode and
output control settings. When the corresponding TM configuration selects the TPn pin to be used as
an output pin, the associated pin will be setup as an external TM output pin. If the TM configuration
selects the TPn pin to be setup as an input pin, the input signal supplied on the associated pin can
be derived from an external signal and other pin-shared output function. If the TM configuration
determines that the TPn pin function is not used, the associated pin will be controlled by other
pin-shared functions. The details of the TPn pin for each TM type and device are provided in the
accompanying table.
Device
HT66F016L HT66F017L
CTM
STM
TP0
TP1
TM Output Pins
Rev. 1.00
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July 04, 2013
HT66F016L/HT66F017L
0.9V Battery Flash A/D Type 8-Bit MCU
TM Function Pin Control Block Diagram
TM Input/Output Pin Control Registers
Selecting to have a TM input/output or whether to retain its other shared functions is implemented
using one register with a single bit in each register corresponding to a TM input/output pin. Setting
the bit high will setup the corresponding pin as a TM input/output if reset to zero the pin will retain
its original other functions.
TMPC Register
Bit
Rev. 1.00
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
T1CP
T0CP
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2 Unimplemented, read as "0"
Bit 1
T1CP: TP1 pin control
0: disable TP1 pin function
1: enable TP1 pin function
Bit 1
T0CP: TP0 pin control
0: disable TP0 pin function
1: enable TP0 pin function
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Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA registers, being 16-bit, all have a low
and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be
accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in
a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its
related low byte only takes place when a write or read operation to its corresponding high byte is
executed. As the CCRA registers are implemented in the way shown in the following diagram and
accessing these register pairs is carried out in a specific way described above, it is recommended
to use the "MOV" instruction to access the CCRA low byte registers, named TMxAL, using the
following access procedures. Accessing the CCRA low byte registers without following these access
procedures will result in unpredictable values.
 The following steps show the read and write procedures:
• Writing Data to CCRA
♦♦ Step 1. Write data to Low Byte TMxAL
––note that here data is only written to the 8-bit buffer.
♦♦ Step 2. Write data to High Byte TMxAH
––here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA
♦♦ Step 1. Read data from the High Byte TMxDH, TMxAH
––here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦ Step 2. Read data from the Low Byte TMxDL, TMxAL
––this step reads data from the 8-bit buffer.
Rev. 1.00
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Compact Type TM – CTM
Although the simplest form of the TM types, the Compact TM type still contains three operating
modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The
Compact TM can also be controlled with an external input pin and can drive one external output pin.
CTM
Name
TM No.
TM Input Pin
TM Output Pin
HT66F016L
HT66F017L
16-bit CTM
0
TCK0
TP0
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„ …  Compact Type TM Block Diagram
Compact TM Operation
At its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock
source. There are also two internal comparators with the names, Comparator A and Comparator
P. These comparators will compare the value in the counter with CCRP and CCRA registers. The
CCRP is 8-bit wide whose value is compared with the highest eight bits in the counter while the
CCRA is 16-bit wide and therefore compares with all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the TnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Compact
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Compact Type TM Register Description
Overall operation of the Compact TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. There is also a read/write register used to store the internal 8-bit
CCRP value. The remaining two registers are control registers which setup the different operating
and control modes.
Rev. 1.00
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CTM Register List
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TM0C0
T0PAU
T0CK2
T0CK1
T0CK0
T0ON
—
—
—
TM0C1
T0M1
T0M0
T0IO1
T0IO0
T0OC
T0POL
T0DPX
T0CCLR
TM0DL
D7
D6
D5
D4
D3
D2
D1
D0
TM0DH
D15
D14
D13
D12
D11
D10
D9
D8
TM0AL
D7
D6
D5
D4
D3
D2
D1
D0
TM0AH
D15
D14
D13
D12
D11
D10
D9
D8
TM0RP
T0RP7
T0RP6
T0RP5
T0RP4
T0RP3
T0RP2
T0RP1
T0RP0
16-bit Compact TM Register List
TM0DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM0DL: TM0 counter low byte register bit 7 ~ bit 0
TM0 16-bit Counter bit 7 ~ bit 0
TM0DH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TM0DH: TM0 counter high byte register bit 7 ~ bit 0
TM0 16-bit counter bit 15 ~ bit 8
TM0AL Register
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TM0AL: TM0 CCRA low byte register bit 7 ~ bit 0
TM0 16-bit CCRA bit 7 ~ bit 0
TM0AH Register
Bit
6
5
4
3
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
7
TM0AH: TM0 CCRA high byte register bit 7 ~ bit 0
TM0 16-bit CCRA bit 15 ~ bit 8
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TM0C0 Register
Bit
7
6
5
4
3
2
1
0
Name
T0PAU
T0CK2
T0CK1
T0CK0
T0ON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
T0PAU: TM0 counter pause control
0: run
1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4
T0CK2~T0CK0: Select TM0 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH/8
110: TCK0 rising edge clock
111: TCK0 falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can be
found in the oscillator section.
Bit 3
T0ON: TM0 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset
to zero, however when the bit changes from high to low, the internal counter will
retain its residual value. If the TM is in the Compare Match Output Mode then the TM
output pin will be reset to its initial condition, as specified by the T0OC bit, when the
T0ON bit changes from low to high.
Bit 2~0
"—": Unimplemented, read as 0
TM0C1 Register
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
T0IO1
T0IO0
T0OC
T0POL
T0DPX
T0CCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Rev. 1.00
T0M1~T0M0: select TM0 operating mode
00: compare match output mode
01: undefined
10: PWM mode
11: Timer/Counter mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the T0M1 and T0M0
bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
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Rev. 1.00
Bit 5~4
T0IO1~T0IO0: Select TP0 output function
compare match output mode
00: no change
01: output low
10: output high
11: toggle output
PWM Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/Counter mode
unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the
TM output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the TM output
pin should be setup using the T0OC bit in the TM0C1 register. Note that the output
level requested by the T0IO1 and T0IO0 bits must be different from the initial value
setup using the T0OC bit otherwise no change will occur on the TM output pin when
a compare match occurs. After the TM output pin changes state it can be reset to its
initial level by changing the level of the T0ON bit from low to high.
In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the T0IO1 and T0IO0 bits only after the TMn has been switched off. Unpredictable
PWM outputs will occur if the T0IO1 and T0IO0 bits are changed when the TM is
running
Bit 3
T0OC: TP0 output control bit
compare match output mode
0: initial low
1: initial high
PWM mode
0: active low
1: active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output
Mode it determines the logic level of the TM output pin before a compare match
occurs. In the PWM Mode it determines if the PWM signal is active high or active
low.
Bit 2
T0POL: TP0 output polarity control
0: non-invert
1: invert
This bit controls the polarity of the TP0 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1
T0DPX: TM0 PWM period/duty control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
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Bit 0
T0CCLR: select TM0 counter clear condition
0: TM0 Comparatror P match
1: TM0 Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not
used in the PWM Mode.
TM0RP Register
Bit
7
6
5
4
3
2
1
0
Name
T0RP7
T0RP6
T0RP5
T0RP4
T0RP3
T0RP2
T0RP1
T0RP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
T0RP7~T0RP0: TM0 CCRP register bit 7~bit 0, compared with the TM0 counter bit
15~bit 8
Comparator P match period =
0: 65536 TM0 clocks
1~255: (1~255) × 256 TM0 clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter's highest eight bits. The result of this
comparison can be selected to clear the internal counter if the T0CCLR bit is set to
zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value
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Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0
bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00B respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which
allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator
A and Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the
counter will overflow when its reaches its maximum 16-bit, FFFF Hex, value, however here the
TnAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin will change
state. The TM output pin condition however only changes state when a TnAF interrupt request flag
is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1
and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0
bits are zero then no pin change will take place.
Rev. 1.00
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Counter Value
CCRP = 0
TnCCLR = 0; TnM[1:0] = 00
Counter
overflow
0xFFFF
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
CCRP
Pause Resume
CCRA
Stop
Counter
Reset
Time
TnON bit
TnPAU bit
TnAPOL bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TPnA O/P Pin
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
with TnAF flag
Now TnIO1, TnIO0 = 10
Active High Output
Select
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Here TnIO1, TnIO0 = 11
Toggle Output Select
Output inverts
when TnPOL is high
Output Pin
Reset to initial value
Output controlled
by other pin-shared function
Compare Match Output Mode – TnCCLR=0
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.00
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TnCCLR = 1; TnM1, TnM0 = 00
Counter Value
CCRA = 0
Counter overflows
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA = 0
CCRA
Pause Resume
Counter
Reset
Stop
CCRP
Time
TnON bit
TnPAU bit
TnPOL bit
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
Output does
not change
TnPF not
generated
Output Pin set
to Initial Level
Low if TnOC = 0
Output not affected by
TnAF flag remains High
until reset by TnON bit
Output Toggle
with TnAF flag
Now TnIO1, TnIO0 = 10
Active High Output
Select
Output controlled by
other pin-shared function
Output inverts
when TnPOL is high
Output Pin
Reset to initial value
Here TnIO1, TnIO0 = 11
Toggle Output Select
Compare Match Output Mode – TnCCLR=1
Note: 1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 1.00
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Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively.
The PWM function within the TM is useful for applications which require functions such as motor
control, heating control, illumination control etc. By providing a signal of fixed frequency but
of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
1~255
Period
CCRP×256
Duty
0
65536
CCRA
If fSYS= 16MHz, TM clock source is fSYS/4, CCRP= 2 and CCRA= 128
The CTM PWM output frequency= (fSYS/4)/(2×256)= fSYS/2048= 7.8125kHz, duty= 128/
(2×256)= 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value,
then the PWM output duty is 100%.
16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
1~255
Period
0
CCRA
Duty
CCRP×256
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to 0.
Rev. 1.00
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Co�nter Va��e
Co�nter C�eared
b� CCRP
TnDPX = 0; TnM [1:0] = 10
CCRP
Co�nter reset
Co�nter Stop when TnON
if TnON bit �ow ret�rns high
Pa�se Res�me
CCRA
Time
TnON
TnPAU
TnPOL
CCRA Int.
F�ag TnAF
CCRP Int.
F�ag TnPF
TM O/P Pin
TnOC = 1
TM O/P Pin
TnOC =