Agilent HMMC-3128 DC-12 GHz Packaged High Efficiency Divide-by-8 Prescaler 1GC1-8208-TR1-7" diameter reel/500 each 1GC1-8208-BLK-bubble strip/10 each Data Sheet Features • Wide Frequency Range: 0.2-12 GHz • High Input Power Sensitivity: On-chip pre- and post-amps -15 to +10 dBm (1- 8 GHz) -10 to +8 dBm (8-10 GHz) -5 to +2 dBm (10-12 GHz) • Pout: 0 dBm (0.5 Vp–p) • Low Phase Noise: -153 dBc/Hz @ 100 kHz Offset • (+) or (-) Single Supply Bias Operation • Wide Bias Supply Range: 4.5 to 6.5 volt operating range • Differential I/0 with on-chip 50 Ω matching Description The HMMC-3128 is a packaged GaAs HBT MMIC pre-scaler which offers dc to 12 GHz frequency translation for use in communications and EW systems incorporating high-frequency PLL oscillator circuits and signalpath down conversion applications. The prescaler provides a large input power sensitivity window and low phase noise. Package Type: Package Dimensions: Package Thickness: Lead Pitch: Lead Width: 8-lead SOIC Plastic 4.9 x 3.9 mm typ. 1.55 mm typ. 1.25 mm nom. 0.42 mm nom. Absolute Maximum Ratings1 (@ TA = 25°C, unless otherwise indicated) Symbol Parameters/Conditions Min. Max. Units VCC Bias supply voltage +7 volts VEE Bias supply voltage -7 VCC - VEE Bias supply delta 0 +7 volts VLogic Logic threshold voltage VCC -1.5 VCC -1.2 volts Pin(CW) CW RF input power +10 dBm VRFin DC input voltage (@ RFin or RFin ports) VCC ±0.5 volts volts TBS2 Backside operating temperature -40 +85 °C Tst Storage temperature -65 +165 °C Tmax Maximum assembly temperature (60 s max.) 310 °C Notes 1. Operation in excess of any parameter limit (except TBS) may cause permanent damage to the device. 2. MTTF > 1 x 106 hours @ TBS ≤ 85°C. Operation in excess of maximum operating temperature (TBS) will degrade MTTF. DC Specifications/Physical Properties (TA = 25°C, VCC – VEE = 5.0 volts, unless otherwise listed) Symbol Parameters/Conditions Min. Typ. Max. Units VCC – VEE Operating bias supply difference1 4.5 5.0 6.5 volts |ICC| or |IEE| Bias supply current 37 44 51 mA VRFin(q) VRFout(q) Quiescent dc voltage appearing at all RF ports VLogic Nominal ECL Logic Level (VLogic contact self-bias voltage, generated on-chip) VCC VCC -1.45 VCC -1.32 volts VCC -1.25 volts Notes 1. Prescaler will operate over full specified supply voltage range, VCC or VEE not to exceed limits specified in Absolute Maximum Ratings section. RF Specifications (TA = 25°C, Z0 = 50 Ω, VCC – VEE = 5.0 volts) Symbol Parameters/Conditions Min. Typ. Max. Units ƒin(max) Maximum input frequency of operation 12 14 ƒin(min) Minimum input frequency of operation1 (Pin = -10 dBm) 0.2 ƒSelf-Osc. Output Self-Oscillation Frequency2 3.4 Pin @ dc, (Square-wave input) -15 > -25 +10 dBm @ ƒin = 500 MHz, (Sine-wave input) -15 > -20 +10 dBm ƒin = 1 to 8 GHz -15 > -20 +10 dBm ƒin = 8 to 10 GHz -10 > -15 +5 dBm ƒin = 10 to 12 GHz -5 > -10 -1 dBm GHz 0.5 GHz GHz RL Small-Signal Input/Output Return Loss (@ ƒin < 10 GHz) 15 dB S12 Small-Signal Reverse Isolation (@ ƒin < 10 GHz) 30 dB φN SSB Phase noise (@ Pin = 0 dBm, 100 kHz offset from a ƒout = 1.2 GHz Carrier) -153 dBc/Hz Jitter Input signal time variation @ zero-crossing (ƒin = 10 GHz, Pin = -10 dBm) 1 ps Tr or Tf Output transition time (10% to 90% rise/fall time) 70 ps Notes 1. For sine-wave input signal. Prescaler will operate down to dc for square-wave input signal. Minimum divide frequency limited by input slew-rate. 2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Input dc offset technique described on page 4. 2 RF Specifications (Continued) (TA = 25°C, Z0 = 50 Ω, VCC – VEE = 5.0 volts) Symbol Parameters/Conditions Min. Typ. Pout3 @ ƒout < 1 GHz -2 0 dBm @ ƒout = 2.5 GHz -3.5 -1.5 dBm @ ƒout = 3.0 GHz -4.5 -2.5 dBm @ ƒout < 1 GHz 0.5 volts @ ƒout = 2.5 GHz 0.42 volts @ ƒout = 3.0 GHz 0.37 volts ƒout power level appearing at RFin or RFin (@ ƒin 10 GHz, unused RFout or RFout unterminated) -50 dBm ƒout power level appearing at RFin or RFin (@ ƒin = 10 GHz, both RFout & RFout terminated) -55 dBm Pfeedthru Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz, Pin = 0 dBm, referred to Pin (ƒin)) -30 dBc H2 Second harmonic distortion output level (@ ƒout = 3.0 GHz, referred to Pout (ƒout)) -25 dBc |Vout(p–p)|4 PSpitback Max. Units Notes 3. Fundamental of output square wave's Fourier Series. 4. Square wave amplitude calculated from Pout. Applications The HMMC-3128 is designed for use in high frequency communications, microwave instrumentation, and EW radar systems where low phase-noise PLL control circuitry or broad-band frequency translation is required. Operation The device is designed to operate when driven with either a single-ended or differential sinusoidal input signal over a 200 MHz to 12 GHz bandwidth. Below 200 MHz the prescaler input is “slew-rate” limited, requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to dc when driven with a square-wave. Due to the presence of an off-chip RF-bypass capacitor inside the package (connected to the VCC contact on the device), and the unique design of the device itself, the component may be biased from either a single positive or single negative supply bias. The backside of the package is not dc connected to any dc bias point on the device. For positive supply operation, VCC pins are nominally biased at any voltage in the +4.5 to +6.5 volt range with pin 8 (VEE) grounded. For negative bias operation VCC pins are typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to pin 8 (VEE). 3 AC-Coupling and DC-Blocking All RF ports are dc connected on-chip to the VCC contact through on-chip 50 Ω resistors. Under any bias conditions where VCC is not dc grounded the RF ports should be ac coupled via series capacitors mounted on the PC board at each RF port. Only under bias conditions where VCC is dc grounded (as is typical for negative bias supply operation) may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. In the latter case the package heat sink may be “floated” and bias applied as the difference between VCC and VEE. Input DC Offset If an RF signal with sufficient signal to noise ratio is present at the RF input lead, the prescaler will operate and provide a divided output equal the input frequency divided by the divide modulus. Under certain "ideal" conditions where the input is well matched at the right input frequency, the component may “self-oscillate”, especially under small signal input powers or with only noise present at the input. This “self-oscillation” will produce a undesired output signal also known as a false trigger. To prevent false triggers or self-oscillation conditions, apply a 20 to 100 mV dc offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider. Adding a 10 kΩ resistor between the unused RF input to a contact point at the VEE potential will result in an offset of ≈ 25 mV between the RF inputs. Note however, that the input sensitivity will be reduced slightly due to the presence of this offset. Assembly Notes Independent of the bias applied to the package, the backside of the package should always be connected to both a good RF ground plane and a good thermal heat sinking region on the PC board to optimize performance. For single-ended output operation the Figure 1. Simplified Schematic unused RF output lead should be terminated into 50 Ω to a contact point at the VCC potential or to RF ground through a dc blocking capacitor. A minimum RF and thermal PC board contact area equal to or greater than 2.67 × 1.65 mm (0.105" × 0.065") with eight 0.020" diameter plated-wall thermal vias is recommended. MMIC ESD precautions, handling considerations, die attach and bonding methods are critical factors in successful GaAs MMIC performance and reliability. Agilent application note #54, “GaAs MMIC ESD, Die Attach and Bonding Guidelines” provides basic information on these subjects. Moisture Sensitivity Classification: Class 1, per JESD22-A112-A. Additional References: PN #18, "HBT Prescaler Evaluation Board." 4 Symbol Min. Max. A 1.35 1.75 A1 0.0 .25 B 0.33 0.51 C 0.19 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC 1.27 BSC H 5.80 6.20 .025 L 0.40 1.27 a 0° 8° Notes: • • • • All dimensions in millimeters. Refer to JEDEC Outline MS-012 for additional tolerances. Exposed heat slug area on package bottom = 2.67 x 1.65. Exposed heat sink on package bottom must be soldered to PCB RF ground plane. Figure 2. Package and dimensions Figure 3. Assembly diagram (Single-supply, positive-bias configuration shown) 5 Figure 4. Typical input sensitivity window Figure 5. Typical supply current & VLogic vs. supply voltage Figure 6. Typical phase noise performance Figure 7. Typical output power vs. output frequency, ƒout (GHz) Figure 8. Typical “Spitback” power P(ƒout) appearing at RF input port 6 Device Orientation Tape Dimensions and Product Orientation Notes: 1. 2. 3. 4. 5. 6. 10 sprocket hole pitch cumulative tolerance: 0.2 mm. Camber not to exceed 1 mm in 100 mm. Material: Black Conductive Advantek Polystyrene. Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 7 www.agilent.com www.agilent.com/find/emailupdates Get the latest information on the products and applications you select. For more information on Agilent Technologies’ products, applications or services, please contact your local Agilent office. The complete list is available at: www.agilent.com/find/contactus www.agilent.com/find/agilentdirect Quickly choose and use your test equipment solutions with confidence. www.agilent.com/find/open Agilent Open simplifies the process of connecting and programming test systems to help engineers design, validate and manufacture electronic products. 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[email protected]. © Agilent Technologies, Inc. 2007 Printed in USA, November 26, 2007 5989-7354EN