HYNIX H5TQ4G83MMR-G7C

H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
4Gb DDR3 SDRAM DDP(2Gbx2)
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Rev. 0.1 / Aug 2008
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
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H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Revision History
Revision No.
History
Draft Date
0.1
Initial Release (Preliminary version)
2008-8
Rev. 0.1 /Aug 2008
Remark
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H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Description
1.1.2 Features
1.1.3 Ordering Information
1.1.4 Ordering Frequency
1.2 Package Ball out
1.3 Row and Column Address Table: 512M/1G Fixed
1.4 Pin Functional Description
1.5 Functional Block Diagram
2. Command Description
2.1 Command Truth Table
2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
3. Absolute Maximum Ratings
4. Operating Conditions
4.1 Operating Temperature Condition
4.2 DC Operating Conditions
5. AC and DC Input Measurement Levels
5.1 AC and DC Logic Input Levels for Single-Ended Signals
5.2 AC and DC Logic Input Levels for Differential Signals
5.3 Differential Input Cross Point Voltage
5.4 Slew Rate Definitions for Single Ended Input Signals
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
5.5 Slew Rate Definitions for Differential Input Signals
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6. AC and DC Output Measurement Levels
6.1 Single Ended AC and DC Output Levels
6.1.1 Differential AC and DC Output Levels
6.2 Single Ended Output Slew Rate
6.3 Differential Output Slew Rate
6.4 Reference Load for AC Timing and Output Slew Rate
7. Overshoot and Undershoot Specifications
7.1 Address and Control Overshoot and Undershoot Specifications
7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
7.3 34 ohm Output Driver DC Electrical Characteristics
7.4 Output Driver Temperature and Voltage sensitivity
7.5 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.1 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.2 ODT DC Electrical Characteristics
7.5.3 ODT Temperature and Voltage sensitivity
7.6 ODT Timing Definitions
7.6.1 Test Load for ODT Timings
7.6.2 ODT Timing Reference Load
8. IDD Specification Parameters and Test Conditions
8.1 IDD Measurement Conditions
8.2 IDD Specifications
8.2.1 IDD6 Current Definition
8.2.2 IDD6TC Specification (see notes 1~2)
9. Input/Output Capacitance
10. Standard Speed Bins
11. Electrical Characteristics and AC Timing
12. Package Dimensions
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1. DESCRIPTION
The H5TQ4G43MMR-xxX and H5TQ4G83MMR-xxX are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.1 Device Features and Ordering Information
1.1.1 FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• Differential Data Strobe (DQS, DQS)
• BL switch on the fly
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• 8banks
• DM masks write data-in at the both rising and falling
edges of the data strobe
• JEDEC standard 82ball FBGA(x4/x8)
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Dynamic On Die Termination supported
• Programmable CAS latency 6, 7, 8, 9 and (10)
supported
• ZQ calibration supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Write Levelization supported
• Programmable CAS Write latency (CWL) = 5, 6, 7
• 8K refresh cycles /64ms
• Driver strength selected by EMRS
• Asynchronous RESET pin supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Auto Self Refresh supported
• On Die Thermal Sensor supported (JEDEC optional)
• 8 bit pre-fetch
1.1.2 ORDERING INFORMATION
Part No.
Configuration
H5TQ4G43MMR-xx*X
512M x 4
H5TQ4G83MMR-xx*X
256M x 8
1.1.3 OPERATING FREQUENCY
Package
Grade
82ball FBGA
* xx means Binning grade (Speed/IDD...)
-S6
-G7
Frequency [MHz]
CL5
CL6
O
O
O
CL7
CL8 CL9 CL10
Remark
(CL-tRCD-tRP)
DDR3-800 6-6-6
O
O
DDR3-1066 7-7-7
* X means Power Consumption & Temperature
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H5TQ4G83MMR-xxC
1.2 Package Ball out
1.2.1 x4/x8 Package Ball out
1
2
3
4
NC
VSS
VDD
NC
B
VSS
VSSQ
C
VDDQ
DQ2
D
VSSQ
DQ6
E
VREFDQ
F
G
A
5
6
7
8
9
10
11
NU/TDQS
VSS
VDD
NC
DQ0
DM
VSSQ
VDDQ
B
DQS
DQ1
DQ3
VSSQ
C
DQS
VDD
VSS
VSSQ
D
VDDQ
DQ4
DQ7
DQ5
VDDQ
E
ODT1
VSS
RAS
CK
VSS
CKE1
F
ODT0
VDD
CAS
CK
VDD
CKE0
G
H
A
H
CS1
CS0
WE
A10/AP
ZQ0
ZQ1
J
VSS
BA0
BA2
NC
VREFCA
VSS
J
K
VDD
A3
A0
A12/BC
BA1
VDD
K
L
VSS
A5
A2
A1
A4
VSS
L
M
VDD
A7
A9
A11
A6
VDD
M
NC
VSS
RESET
A13
A14
A8
VSS
NC
1
2
3
4
8
9
10
11
N
5
6
7
N
Note: Green NC balls indicate mechanical support balls with no internal connection
1 2 3 4
8 9 10 11
A
B
C
D
E
F
G
H
J
K
(Top View: See the balls through the Package)
Populated ball
Ball not populated
L
M
N
Back View
Populated ball
Ball not populated
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1.3 ROW AND COLUMN ADDRESS TABLE
1Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
256Mb x 4
128Mb x 8
64Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9,A11
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A12
A0 - A9
2 KB
512Mb x 4
256Mb x 8
128Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9,A11
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9
2 KB
1Gb x 4
512Mb x 8
256Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9,A11
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9
2 KB
2Gb x 4
1Gb x 8
512Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9, A11, A13
2 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9, A11
2 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9
2 KB
2Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
4Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
8Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG ÷ 8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
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H5TQ4G83MMR-xxC
1.4 Pin Functional Description
Input / output functional description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK.
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and SelfRefresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable
during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down.
Input buffers, excluding CKE, are disabled during Self-Refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH.
CS provides for external Rank selection on systems with multiple Ranks.
CS is considered part of the command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/
TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8
configurations. For x16 configuration ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL,
DMU, and DML signal.
The ODT pin will be ignored if MR1 is programmed to disable ODT.
RAS.
CAS. WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM, (DMU),
(DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register
A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS cycle.
Input
Address Inputs: Provide the row address for Active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12/BC have additional functions, see below).
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop
(on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V
for DC high and 0.30V for DC low.
A0 - A15
RESET
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Symbol
Type
DQ
Input /
Output
Data Input/ Output: Bi-directional data bus.
Input /
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU
corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL, and DQSU are paired
with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair
signaling to the system during reads and writes. DDR3 SDRAM supports differential data
strobe only and does not support single-ended.
Output
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 =
0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4 DRAMs
must disable the TDQS function via mode register A11 = 0 in MR1.
DQU, DQL,
DQS, DQS,
DQSU, DQSU,
DQSL, DQSL
TDQS, TDQS
Function
No Connect: No internal electrical connection is present.
NC
VDDQ
Supply
DQ Power Supply: 1.5 V +/- 0.075 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.5 V +/- 0.075 V
VSS
Supply
Ground
VREFDQ
Supply
Reference voltage for DQ
VREFCA
Supply
Reference voltage
ZQ
Supply
Reference Pin for ZQ calibration
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.
Rev. 0.1 /Aug 2008
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H5TQ4G83MMR-xxC
1.5 Functional Block Diagram
Block Diagram (DDP. 1Gx4)
CLK, /RAS, /CAS
/WE, DM
512Mx4
CKE1
/CS1
ODT1
CKE0
/CS0
ODT0
512Mx4
DQ0~DQ3
A0~A14, BA0~BA2
Block Diagram (DDP. 512Mx8)
CLK, /RAS, /CAS
/WE, DM
256Mx8
CKE1
/CS1
ODT1
CKE0
/CS0
ODT0
256Mx8
DQ0~DQ7
A0~A14, BA0~BA2
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H5TQ4G83MMR-xxC
2. Command Description
2.1 Command Truth Table
(a) note 1,2,3,4 apply to the entire Command Truth Table
(b) Note 5 applies to all Read/Write command
[BA = Bank Address, RA = Rank Address, CA = Column Address, BC = Burst Chop, X = Don’t Care, V = Valid]
Function
CKE
Abbrev Previ Curre
iation
ous
nt
Cycle Cycle
CS
RAS
CAS
WE
BA0- A13- A12- A10- A0A9,
BA3 A15 BC
AP A11
Notes
Mode Register Set
MRS
H
H
L
L
L
L
BA
Refresh
REF
H
H
L
L
L
H
V
V
V
V
V
Self Refresh Entry
SRE
H
L
V
V
V
V
V
7,9,12
V
V
V
V
V
7,8,9,1
2
BA
V
V
L
V
V
V
H
V
L
L
L
H
H
V
V
V
L
H
H
H
L
OP Code
Self Refresh Exit
SRX
L
H
Single Bank Precharge
PRE
H
H
L
L
H
Precharge all Banks
PREA
H
H
L
L
H
L
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
Write (BC4, on the Fly)
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
Write with Auto
Precharge
(Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA
RFU
V
H
CA
Write with Auto
Precharge
(BC4, on the Fly)
WRAS
4
H
H
L
H
L
L
BA
RFU
L
H
CA
Write with Auto
Precharge
(BL8, on the Fly)
WRAS
8
H
H
L
H
L
L
BA
RFU
H
H
CA
Read (Fixed BL8 or BC4)
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
Read (BC4, on the Fly)
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
Read with Auto
Precharge
(Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA
RFU
V
H
CA
Read with Auto
Precharge
(BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
RFU
L
H
CA
Read with Auto
Precharge
(BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
RFU
H
H
CA
Row Address (RA)
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
L
H
H
H
H
V
V
V
V
V
V
V
V
6,12
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H5TQ4G83MMR-xxC
CKE
Function
Abbrev Previ Curre
iation
ous
nt
Cycle Cycle
CS
RAS
CAS
WE
L
H
H
H
H
V
V
V
Power Down Exit
PDX
L
H
ZQ Calibration Long
ZQCL
H
H
L
H
H
ZQ Calibration Short
ZQCS
H
H
L
H
H
BA0- A13- A12- A10- A0A9,
BA3 A15 BC
AP A11
V
V
V
V
V
L
X
X
X
H
X
L
X
X
X
L
X
Notes
6,12
Notes:
1. All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the
clock. The MSB of BA, RA and CA are device density and configuration dependant.
2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during
any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the Fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose
of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands
between operations. A No Operation command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
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2.2 CKE Truth Table
a) Notes 1-7 apply to the entire CKE Truth Table.
b) CKE low is allowed only if tMRD and tMOD are satisfied.
CKE
Current State
2
Power-Down
Previous
Cycle1
(N-1)
Current
Cycle1
(N)
Command (N)3
RAS, CAS,
WE, CS
Action (N)3
Notes
L
L
X
Maintain Power-Down
14, 15
L
H
DESELECT or NOP
Power-Down Exit
11,14
L
L
X
Maintain Self-Refresh
15,16
L
H
DESELECT or NOP
Self-Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Self-Refresh
Refreshing
All Banks Idle
H
L
DESELECT or NOP
Precharge Power-Down Entry
11
H
L
DESELECT or NOP
Precharge Power-Down Entry
11,13,14,18
H
L
REFRESH
Self-Refresh
9,13,18
For more details with all signals See “2.1 Command Truth Table” on page 11..
10
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is
not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during
Self-Refresh.
6. tCKEmin of [TBD] clocks means CKE must be registered on [TBD] consecutive positive clock edges. CKE must remain
at the valid input level the entire time it takes to achieve the [TBD] clocks of registration. Thus, after any CKE
transition, CKE may not transition from its valid level during the time period of tIS + [TBD] + tIH.
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS
period. Read or ODT commands may be issued only after tXSDLL is satisfied.
9. Self-Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self-Refresh Exit are NOP and DESELECT only.
13. Self-Refresh can not be entered during Read or Write operations. For a detailed list of restrictions
see 8.1 on page 36.
14. The Power-Down does not perform any refresh operations.
15. “X” means “don’t care” (including floating around VREF) in Self-Refresh and Power-Down. It also applies to
Address pins.
16. VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down
is entered, otherwise Active Power-Down is entered.
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high,
and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as
all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
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3. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 0.4 V ~ 1.975 V
V
,3
Voltage on VDDQ pin relative to Vss
- 0.4 V ~ 1.975 V
V
,3
- 0.4 V ~ 1.975 V
V
VIN, VOUT Voltage on any pin relative to Vss
TSTG
Storage Temperature
-55 to +100
,2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
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4. Operating Conditions
4.1 OPERATING TEMPERATURE CONDITION
Symbol
TOPER
Parameter
Rating
Units
Notes
Operating Temperature (Tcase)
0 to 85
o
C
2
Extended Temperature Range
85 to 95
o
C
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.
For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case
temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
(This double refresh requirement may not apply for some devices.) It is also possible to specify a component with
1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the
DIMM SPD for option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or
enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
4.2 RECOMMENDED DC OPERATING CONDITIONS
Rating
Symbol
VDD
VDDQ
Parameter
Units
Notes
1.575
V
1,2
1.575
V
1,2
Min.
Typ.
Max.
Supply Voltage
1.425
1.500
Supply Voltage for Output
1.425
1.500
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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5. AC and DC Input Measurement Levels
5.1 AC and DC Logic Input Levels for Single-Ended Signals
Single Ended AC and DC Input Levels
Symbol
DDR3-1066,
DDR3-1333
Parameter
Unit
Notes
1
Min
Max
Vref + 0.100
TBD
V
VIH(DC)
DC input logic high
VIL(DC)
DC input logic low
TBD
Vref - 0.100
V
1
VIH(AC)
AC input logic high
Vref + 0.175
-
V
1, 2
VIL(AC)
AC input logic low
Vref - 0.175
V
1, 2
VRefDQ(DC) Reference Voltage for DQ, DM inputs
0.49 * VDD
0.51 * VDD
V
3, 4
VRefCA(DC) Reference Voltage for ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3, 4
VDDQ/2 - TBD
VDDQ/2 + TBD
VTT
Termination voltage for DQ, DQS outputs
Notes:
1. For DQ and DM, Vref = VrefDQ. For input any pins except RESET, Vref = VrefCA.
2. The “t.b.d.” entries might change based on overshoot and undershoot specification.
3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD
(for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in
below Figure. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and
VRefDQ likewise).
VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in Table 1.
Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
voltage
VDD
VRef ac-noise
VRef(DC)
VRef(t)
VRef(DC)max
VDD/2
VRef(DC)min
VSS
time
Illustration of Vref (DC) tolerance and Vref ac-noise limits
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5.2 AC and DC Logic Input Levels for Differential Signals
Symbol
DDR3-1066,
DDR3-1333
Parameter
VIHdiff
VILdiff
Differential input logic high
Differential input logic low
Min
Max
+ 0.200
- 0.200
Unit
Notes
V
V
1
1
Note1.
Refer to “Overshoot and Undershoot Specification on page 25”
5.3 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe,
each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements
below table. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signal to the midlevel between of VDD and VSS.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
Symbol
VIX
DDR3-1066,
DDR3-1333
Parameter
Differential Input Cross Point
Rev. 0.1 /Aug 2008
Voltage relative to VDD/2
Unit Notes
Min
Max
- 150
150
mV
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5.4 Slew Rate Definitions for Single Ended Input Signals
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max.
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max
and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VIH (DC) min and the first crossing of VRef.
Single-Ended Input Slew Rate Definition
Measured
Description
Min
Max
Input slew rate for rising edge
Vref
VIH (AC) min
Input slew rate for falling edge
Vref
VIL (AC) max
Input slew rate for rising edge
VIL (DC) max
Vref
Input slew rate for falling edge VIH (DC) min
Vref
Defined by
Applicable for
VIH (AC) min-Vref
Delta TRS
Vref-VIL (AC) max
Setup
(tIS, tDS)
Delta TFS
Vref-VIL (DC) max
Delta TFH
VIH (DC) min-Vref
Hold
(tIH, tDH)
Delta TRH
Input Nominal Slew Rate Definition for Single-Ended Signals
P a rt A : S e t u p
Single Ended input Voltage(DQ,ADD, CMD)
D e lt a T R S
v I H ( A C ) m in
v I H ( D C ) m in
v R e fD Q o r
v R e fC A
v IH (D C )m a x
v IH (A C )m a x
D e lt a T F S
P a r t B : H o ld
Single Ended input Voltage(DQ,ADD, CMD)
D e lt a T R H
v I H ( A C ) m in
v I H ( D C ) m in
v R e fD Q o r
v R e fC A
v IH (D C )m a x
v IH (A C )m a x
D e lt a T F H
F ig u r e 8 2 ? I n p u t N o m in a l S le w R a t e D e f in it io n f o r S in g le - E n d e d S ig n a ls
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5.5 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table
and Figure .
Measured
Description
Min
Max
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
VILdiffmax
VIHdiffmin
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
VIHdiffmin
VILdiffmax
Defined by
VIHdiffmin-VILdiffmax
DeltaTRdiff
VIHdiffmin-VILdiffmax
DeltaTFdiff
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Note:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Delta
TRdiff
vIHdiffmin
0
vILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
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6. AC and DC Output Measurement Levels
6.1 Single Ended AC and DC Output Levels
Table shows the output levels used for measurements of single ended signals.
Symbol
DDR3-1066,
Parameter
Unit
1333
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V
Notes
1
VOL(AC)
VTT - 0.1 x VDDQ
V
1
AC output low measurement level (for output SR)
1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with
a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.
6.1.1 Differential AC and DC Output Levels
Below table shows the output levels used for measurements of differential signals.
DDR3-1066,
Symbol
Parameter
VOHdiff (AC)
AC differential output high measurement level (for output SR)
1333
+ 0.2 x VDDQ
Unit Notes
V
1
VOLdiff (AC) AC differential output low measurement level (for output SR)
- 0.2 x VDDQ
V
1
1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with
a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the differential outputs.
6.2 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table and Figure.
Measured
Description
Defined by
From
To
VOL(AC)
VOH(AC)
VOH(AC)-VOL(AC)
Single ended output slew rate for rising edge
DeltaTRse
VOH(AC)-VOL(AC)
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
DeltaTFse
Note:
Output slew rate is verified by design and characterization, and may not be subject to production test.
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Fig. Single Ended Output Slew Rate Definition
Single Ended Output Voltage(l.e.DQ)
Delta TRse
vOH(AC)
V∏
vOl(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Table. Output Slew Rate (single-ended)
DDR3-1066
Parameter
Single-ended Output Slew Rate
DDR3-1333
Units
Symbol
SRQse
Min
Max
Min
Max
2.5
5
2.5
5
V/ns
*** For Ron = RZQ/7 setting
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6.3 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in Table and Figure .
Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff (AC)
VOHdiff (AC)
Differential output slew rate for falling edge
VOHdiff (AC)
VOLdiff (AC)
VOHdiff (AC)-VOLdiff (AC)
DeltaTRdiff
VOHdiff (AC)-VOLdiff (AC)
DeltaTFdiff
Note:
Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
Delta
TRdiff
vOHdiff(AC)
O
vOLdiff(AC)
Delta
TFdiff
Differential Output Slew Rate Definition
Fig. Differential Output Slew Rate Definition
Table. Differential Output Slew Rate
DDR3-1066
Parameter
Differential Output Slew Rate
DDR3-1333
Units
Symbol
SRQdiff
Min
Max
Min
Max
5
10
5
10
V/ns
***For Ron = RZQ/7 setting
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6.4 Reference Load for AC Timing and Output Slew Rate
Figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the
device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial
transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ
DQS
DQS
25 Ohm
VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
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7. Overshoot and Undershoot Specifications
7.1 Address and Control Overshoot and Undershoot Specifications
Table. AC Overshoot/Undershoot Specification for Address and Control Pins
Specification
Description
Maximum peak amplitude allowed for
overshoot area (see Figure)
Maximum peak amplitude allowed for
undershoot area (see Figure)
Maximum overshoot area above VDD (See Figure)
Maximum undershoot area below VSS (See Figure)
DDR3-1066
DDR3-1333
0.4V
0.4V
0.4V
0.4V
0.5 V-ns
0.5 V-ns
0.4 V-ns
0.4 V-ns
M a x im u m A m p litu d e
O v e rs h o o t A re a
VDD
VSS
U n d e rs h o o t A re a
M a x im u m A m p litu d e
T im e (n s )
A d d re s s a n d C o n tro l O v e rs h o o t a n d U n d e rs h o o t D e fin itio n
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7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
Table. AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Specification
Description
Maximum peak amplitude allowed for
overshoot area (see Figure)
Maximum peak amplitude allowed for
undershoot area (see Figure)
Maximum overshoot area above VDDQ (See Figure)
Maximum undershoot area below VSSQ (See Figure)
DDR3-1066
DDR3-1333
0.4V
0.4V
0.4V
0.4V
0.19 V-ns
0.19 V-ns
0.15 V-ns
0.15 V-ns
M a x im u m A m p litu d e
O v e rsh o o t A re a
V o lts
(V )
VDDQ
VSSQ
U n d e rsh o o t A re a
M a x im u m A m p litu d e
T im e (n s)
C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n
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7.3 34 ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown in Figure . Output driver impedance RON is defined
by the value of the external reference resistor RZQ as follows:
RON34 = RZQ / 7 (nominal 34.3 W ±10% with nominal RZQ = 240 W ± 1%)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
V DDQ – V Out
RON Pu = -------------------------------------I Out
under the condition that RONPd is turned off
V Out
RON Pd = --------------I Out
under the condition that RONPu is turned off
Chip in Drive Mode
Output Driver
VDDQ
Ipu
To
other
Circuitry
Like
RCV,
...
RONpu
DQ
RONpd
Iout
Ipd
Vout
VSSQ
Output Driver: Definition of Voltages and Currents
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Output Driver DC Electrical Characteristics, assuming RZQ = 240 Ω ;
entire operating temperature range; after proper ZQ calibration
RONNom
VOut
min
nom
max
Unit
Notes
VOLdc = 0.2 × VDDQ
VOMdc = 0.5 × VDDQ
VOHdc = 0.8 × VDDQ
VOLdc = 0.2 × VDDQ
VOMdc = 0.5 × VDDQ
VOHdc = 0.8 × VDDQ
VOMdc
0.5 × VDDQ
0.6
1.0
1.1
1, 2, 3
0.9
1.0
1.1
0.9
1.0
1.4
1, 2, 4
Resistor
RON34Pd
34 Ω
RON34Pu
Mismatch between pull-up and pull-down,
MMPuPd
0.9
1.0
1.4
0.9
1.0
1.1
0.6
1.0
1.1
RZQ/7
RZQ/7
RZQ/7
RZQ/7
RZQ/7
RZQ/7
+10
%
-10
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of
the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and
temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other
calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ
and 0.8 x VDDQ.
4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, both at 0.5 x VDDQ:
RON Pu – RON Pd
MM PuPd = ------------------------------------------------- x 100
RON Nom
7.4 Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table and Table .
DT = T - T (@calibration); DV= VDDQ - VDDQ (@calibration); VDD = VDDQ
dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Output Driver Sensitivity Definition
min
max
unit
[email protected] VOHdc
0.6 - dRONdTH*|∆T| - dRONdVH*|∆V|
1.1 + dRONdTH*|∆T| + dRONdVH*|∆V|
RZQ/7
[email protected] VOMdc
0.9 - dRONdTM*|∆T| - dRONdVM*|∆V|
1.1 + dRONdTM*|∆T| + dRONdVM*|∆V|
RZQ/7
[email protected] VOLdc
0.6 - dRONdTL*|∆T| - dRONdVL*|∆V|
1.1 + dRONdTL*|∆T| + dRONdVL*|∆V|
RZQ/7
Output Driver Voltage and Temperature Sensitivity
min
max
unit
dRONdTM
0
1.5
%/oC
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/oC
dRONdVL
0
TBD
%/mV
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Output Driver Voltage and Temperature Sensitivity
min
max
unit
dRONdTH
0
1.5
%/oC
dRONdVH
0
TBD
%/mV
These parameters may not be subject to production test. They are verified by design and characterization.
7.5 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.1 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register.
ODT is applied to the DQ, DM, DQS/DQS and TDQS/TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown in Figure . The individual pull-up and pull-down resistors
(RTTPu and RTTPd) are defined as follows:
V DDQ – V Out
RTT Pu = --------------------------------I Out
V Out
RTT Pd = -----------I Out
under the condition that RTTPd is turned off
under the condition that RTTPu is turned off
C h ip in T e r m in a t io n M o d e
ODT
VDDQ
Ip u
To
o th e r
C ir c u it r y
L ik e
RCV,
. ..
Io u t = Ip d -Ip u
RTTpu
DQ
RTTpd
Io u t
Vout
Ip d
VSSQ
IO _ C T T _ D E F IN IT IO N _ 0 1
O n - D ie T e r m in a t io n : D e f in it io n o f V o lt a g e s a n d C u r r e n t s
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7.5.2 ODT DC Electrical Characteristics
A below table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120,
RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines:
ODT DC Electrical Characteristics, assuming RZQ = 240 Ω +/- 1% entire operating temperature range;
after proper ZQ calibration
MR1 A9, A6, A2
RTT
Resistor
RTT120Pd240
0, 1, 0
120 Ω
RTT120Pu240
RTT120
RTT60Pd120
0, 0, 1
60 Ω
RTT60Pu120
RTT60
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VOut
min
nom
max
Unit
Notes
VOLdc
0.2 × VDDQ
0.6
1.00
1.1
RZQ
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.9
1.00
1.4
RZQ
1) 2) 3) 4)
VOLdc
0.2 × VDDQ
0.9
1.00
1.4
RZQ
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.6
1.00
1.1
RZQ
1) 2) 3) 4)
VIL(ac) to VIH(ac)
0.9
1.00
1.6
RZQ/2
1) 2) 5)
VOLdc
0.2 × VDDQ
0.6
1.00
1.1
RZQ/2
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/2
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.9
1.00
1.4
RZQ/2
1) 2) 3) 4)
VOLdc
0.2 × VDDQ
0.9
1.00
1.4
RZQ/2
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/2
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.6
1.00
1.1
RZQ/2
1) 2) 3) 4)
VIL(ac) to VIH(ac)
0.9
1.00
1.6
RZQ/4
1) 2) 5)
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ODT DC Electrical Characteristics, assuming RZQ = 240 Ω +/- 1% entire operating temperature range;
after proper ZQ calibration
MR1 A9, A6, A2
RTT
Resistor
VOut
min
nom
max
Unit
Notes
VOLdc
0.2 × VDDQ
0.6
1.00
1.1
RZQ/3
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/3
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.9
1.00
1.4
RZQ/3
1) 2) 3) 4)
VOLdc
0.2 × VDDQ
0.9
1.00
1.4
RZQ/3
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/3
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.6
1.00
1.1
RZQ/3
1) 2) 3) 4)
VIL(ac) to VIH(ac)
0.9
1.00
1.6
RZQ/6
1) 2) 5)
VOLdc
0.2 × VDDQ
0.6
1.00
1.1
RZQ/4
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/4
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.9
1.00
1.4
RZQ/4
1) 2) 3) 4)
VOLdc
0.2 × VDDQ
0.9
1.00
1.4
RZQ/4
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/4
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.6
1.00
1.1
RZQ/4
1) 2) 3) 4)
VIL(ac) to VIH(ac)
0.9
1.00
1.6
RZQ/8
1) 2) 5)
VOLdc
0.2 × VDDQ
0.6
1.00
1.1
RZQ/6
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/6
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.9
1.00
1.4
RZQ/6
1) 2) 3) 4)
VOLdc
0.2 × VDDQ
0.9
1.00
1.4
RZQ/6
1) 2) 3) 4)
0.5 × VDDQ
0.9
1.00
1.1
RZQ/6
1) 2) 3) 4)
VOHdc
0.8 × VDDQ
0.6
1.00
1.1
RZQ/6
1) 2) 3) 4)
VIL(ac) to VIH(ac)
0.9
1.00
1.6
RZQ/12
1) 2) 5)
+5
%
1) 2) 5) 6)
RTT40Pd80
40 Ω
0, 1, 1
RTT40Pu80
RTT40
RTT30Pd60
30 Ω
1, 0, 1
RTT30Pu60
RTT30
RTT20Pd40
20 Ω
1, 0, 0
RTT20Pu40
RTT20
Deviation of VM w.r.t. VDDQ/2, DVM
-5
The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be
used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.
Not a specification requirement, but a design guide line.
Measurement definition for RTT:
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Apply VIH (ac) to pin under test and measure current I(VIH (ac)), then apply VIL (ac) to pin under test and measure current I(VIL (ac)) respectively.
V IH(ac) – V IL(ac)
RTT = -------------------------------------------------------I(VIH(ac)) – I(VIL(ac))
Measurement definition for VM and DVM:
Measure voltage (VM) at test pin (midpoint) with no load:
2 • VM
∆V M = ⎛ ----------------- – 1⎞⎠ • 100
⎝V
DDQ
7.5.3 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table and Table .
DT = T - T (@calibration); DV= VDDQ - VDDQ (@calibration); VDD = VDDQ
ODT Sensitivity Definition
RTT
min
max
unit
0.9 - dRTTdT*|∆T| - dRTTdV*|∆V|
1.6 + dRTTdT*|∆T| + dRTTdV*|∆V|
RZQ/2,4,6,8,12
ODT Voltage and Temperature Sensitivity
min
max
unit
dRTTdT
0
1.5
%/oC
dRTTdV
0
0.15
%/mV
These parameters may not be subject to production test. They are verified by design and characterization
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7.6 ODT Timing Definitions
7.6.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure .
VDDQ
DUT
CK, CK
DQ, DM
DQS, DQS
TDQS, TDQS
RTT
= 25 Ω
VTT =
VSSQ
VSSQ
Timing Reference Points
BD_REFLOAD_ODT
7.6.2 ODT Timing Reference Load
ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in the table and subsequent figures. Measurement
reference settings are provided in the table.
ODT Timing Definitions
Symbol
Begin Point Definition
End Point Definition
Figure
tAON
Rising edge of CK - CK defined by
the end point of ODTLon
Extrapolated point at VSSQ
Figure
tAONPD
Rising edge of CK - CK with
ODT being first registered high
Extrapolated point at VSSQ
Figure
tAOF
Rising edge of CK - CK defined by
the end point of ODTLoff
End point: Extrapolated point at VRTT_Nom
Figure
tAOFPD
Rising edge of CK - CK with
ODT being first registered low
End point: Extrapolated point at VRTT_Nom
Figure
tADC
Rising edge of CK - CK defined by the end point of
ODTLcnw, ODTLcwn4 or ODTLcwn8
End point: Extrapolated point at VRTT_Wr and
VRTT_Nom respectively
Figure
Reference Settings for ODT Timing Measurements
Measured
Parameter
tAON
tAONPD
tAOF
tAOFPD
tADC
Rev. 0.1 /Aug 2008
RTT_Nom Setting
RTT_Wr Setting
VSW1 [V]
VSW2 [V]
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/12
RZQ/2
0.20
0.30
Note
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Begin point: Rising edge of CK - CK
defined by the end point of ODTLon
CK
VTT
CK
t AON
TSW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
TD_TAON_DEF
Definition of tAON
Begin point: Rising edge of CK - CK with
ODT being first registered high
CK
VTT
CK
t AONPD
T SW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSSQ
VSW1
VSSQ
End point: Extrapolated point at VSSQ
TD_TAONPD_DEF
Definition of tAONPD
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Begin point: Rising edge of CK - CK
defined by the end point of ODTLoff
CK
VTT
CK
t AOF
End point: Extrapolated point at VRTT_Nom
VRTT_Nom
T SW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSW1
VSSQ
TD_TAOF_DEF
Definition of tAOF
Begin point: Rising edge of CK - CK with
ODT being first registered low
CK
VTT
CK
t AOFPD
End point: Extrapolated point at VRTT_Nom
VRTT_Nom
T SW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSW1
VSSQ
TD_TAOFPD_DEF
Definition of tAOFPD
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Begin point: Rising edge of CK - CK
defined by the end point of ODTLcnw
Begin point: Rising edge of CK - CK defined by
the end point of ODTLcwn4 or ODTLcwn8
CK
VTT
CK
t ADC
VRTT_Nom
End point:
DQ, DM
Extrapolated
DQS, DQS
point at VRTT_Nom
TDQS, TDQS
tADC
VRTT_Nom
T SW21
VSW2
TSW11
VSW1
T SW22
T SW12
VRTT_Wr
End point: Extrapolated point at VRTT_Wr
VSSQ
TD_TADC_DEF
Definition of tADC
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8. IDD and IDDQ Specification Parameters and Test Conditions
8.1 IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1 shows the
setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3
SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the
DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ
cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
”0” and “LOW” is defined as VIN <= VILAC(max).
•
”1” and “HIGH” is defined as VIN >= VIHAC(max).
•
“FLOATING” is defined as inputs are VREF - VDD/2.
•
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 38.
•
Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 38.
•
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 41 through Table 10 on page
46.
•
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or
IDDQ measurement is started.
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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IDDQ (optional)
IDD
VDD
VDDQ
RESET
CK/CK
DDR3
SDRAM
CKE
CS
RAS, CAS, WE
A, BA
ODT
ZQ
VSS
DQS, DQS
DQ, DM,
TDQS, TDQS
RTT = 25 Ohm
VDDQ/2
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Test Load
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1066
DDR3-1333
7-7-7
9-9-9
tCK
1.875
1.5
ns
CL
7
9
nCK
Symbol
Unit
nRCD
7
9
nCK
nRC
27
33
nCK
nRAS
20
24
nCK
nRP
7
9
nCK
x4/x8
20
20
nCK
x16
27
30
nCK
x4/x8
4
4
nCK
x16
6
5
nCK
nRFC -512Mb
48
60
nCK
nRFC-1 Gb
59
74
nCK
nRFC- 2 Gb
86
107
nCK
nRFC- 4 Gb
160
200
nCK
nRFC- 8 Gb
187
234
nCK
nFAW
nRRD
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: High between
IDD0
ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on page 41;
Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see
Table 3 on page 41); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 3 on page 41
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 38 BL: 8a); AL: 0; CS: High
IDD1
between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
Table 4 on page 42; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see
Table 4 on page 42); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 4 page 42
Precharge Stanby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2N
Address, Bank Address Inputs: partially toggling according to Table 5 on page 43; Data IO: FLOATING; DM:
stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 5 on page 43
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Precharge Stanby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2NT
Address, Bank Address Inputs: partially toggling according to Table 6 on page 43; Data IO: FLOATING; DM:
stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
toggling according to Table 6 on page 43; Pattern Details: see Table 6 on page 43
IDDQ2NT Precharge Stanby ODT IDDQ Current
(optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2P0
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2P1
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Fast Exitc)
Precharge Quiet Stanby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Stanby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD3N
Address, Bank Address Inputs: partially toggling according to Table 5 on page 43; Data IO: FLOATING; DM:
stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 5 on page 43
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDDQ4R Operating Burst Read IDDQ Current
(optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
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Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 44; Data IO: seamless
IDD4R
read data burst with different data between one burst and the next one according to Table 7 on page 44; DM:
stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7 on
page 44); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 7 on page 44
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 44; Data IO: seamless
IDD4W
read data burst with different data between one burst and the next one according to Table 8 on page 44; DM:
stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8 on
page 44); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details:
see Table 8 on page 44
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 38; BL: 8a); AL: 0; CS: High between REF;
IDD5B
Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 45; Data IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 45); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9 on page 45
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 38; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Self-Refresh Current: Extended Temperature Range (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 38; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Auto Self-Refresh Current (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6TC
Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 38; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
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Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 38; BL: 8a);
AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling
IDD7
according to Table 10 on page 46; Data IO: read data burst with different data between one burst and the next
one according to Table 10 on page 46; DM: stable at 0; Bank Activity: two times interleaved cycling through
banks (0, 1,...7) with different addressing, wee Table 10 on page 46; Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 46
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by
DDR3 SDRAM device
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
ACT
0
0
1
1
0
0
00
0
0
0
0
-
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
-
0
F
0
-
0
-
nRAS
...
1*nRC+0
Static High
Datab)
1,2
...
toggling
CS
0
Command
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 3 - IDD0 Measurement-Loop Patterna)
...
1*nRC+nRAS
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0
0
1
1
0
00
00
0
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
F
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.1 /Aug 2008
41
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
00000000
0
0
0
-
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 4 - IDD1 Measurement-Loop Patterna)
3,4
...
nRCD
...
nRAS
Static High
toggling
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC+1,2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 /Aug 2008
42
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Static High
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
toggling
Datab)
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-17
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Static High
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-17
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
A[2:0]
1
0
A[6:3]
1
0
A[9:7]
Cycle
Number
1
0
1
A[10]
1
0
A[15:11]
D
0
1
0
BA[2:0]
3
1
1
0
ODT
D
0
WE
D
2
1
CAS
1
RAS
D
CS
Command
0
toggling
0
Sub-Loop
CKE
CK, CK
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Datab)
0
0
0
-
0
0
0
-
0
F
0
-
0
F
0
00000000
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.1 /Aug 2008
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H5TQ4G83MMR-xxC
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Static High
0
toggling
Datab)
0
RD
0
1
0
1
0
0
00
0
0
0
0
00000000
1
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
5
D
1
0
0
0
0
0
00
0
0
F
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna)
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
WR
0
1
0
0
1
0
00
0
0
0
0
00000000
1
D
1
0
0
0
1
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
1
0
00
0
0
0
0
-
4
WR
0
1
0
0
1
0
00
0
0
F
0
00110011
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 8 - IDD4W Measurement-Loop Patterna)
Static High
toggling
5
6,7
D
1
0
0
0
1
0
00
0
0
F
0
-
D,D
1
1
1
1
1
0
00
0
0
F
0
-
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 /Aug 2008
44
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 9 - IDD5B Measurement-Loop Patterna)
Static High
toggling
3,4
2
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.1 /Aug 2008
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H5TQ4G83MMR-xxC
Table 10 - IDD7 Measurement-Loop Patterna)
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1
RDA
0
1
0
1
0
0
00
1
0
0
0
00000000
2
D
1
0
0
0
0
0
00
0
0
0
0
-
0
Cycle
Number
Sub-Loop
CKE
CK, CK
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
...
Static High
toggling
1
repeat above D Command until nRRD - 1
nRRD
ACT
0
0
1
1
0
1
00
0
0
F
0
-
nRRD+1
RDA
0
1
0
1
0
1
00
1
0
F
0
00110011
D
1
0
0
0
0
1
00
0
0
F
0
-
0
0
F
0
-
nRRD+2
...
repeat above D Command until 2* nRRD - 1
2
2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 2
3
3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 3
4
4*nRRD
...
Assert and repeat above D Command until nFAW - 1, if necessary
5
nFAW
repeat Sub-Loop 0, but BA[2:0] = 4
6
nFAW+nRRD
repeat Sub-Loop 1, but BA[2:0] = 5
7
nFAW+2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 6
8
nFAW+3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 7
9
nFAW+4*nRRD
...
10
D
1
1
0
0
0
0
0
0
0
0
7
00
00
0
0
F
0
-
Assert and repeat above D Command until 2* nFAW - 1, if necessary
ACT
0
0
1
1
0
0
00
0
0
F
0
-
2*nFAW+1
RDA
0
1
0
1
0
0
00
1
0
F
0
00110011
D
1
0
0
0
0
0
00
0
0
F
0
-
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
ACT
0
0
1
1
0
1
00
0
0
0
0
-
2*nFAW+nRRD+1
RDA
0
1
0
1
0
1
00
1
0
0
0
00000000
D
1
0
0
0
0
1
00
0
0
0
0
-
0
0
-
2&nFAW+nRRD+2
12
2*nFAW+2*nRRD
13
2*nFAW+3*nRRD
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
14
2*nFAW+4*nRRD
15
3*nFAW
repeat Sub-Loop 10, but BA[2:0] = 4
16
3*nFAW+nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
17
3*nFAW+2*nRRD
repeat Sub-Loop 10, but BA[2:0] = 6
18
3*nFAW+3*nRRD
14
3
2*nFAW+0
2&nFAW+2
11
D
3*nFAW+4*nRRD
0
00
0
0
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
0
00
0
0
0
0
-
Assert and repeat above D Command until 4* nFAW - 1, if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 /Aug 2008
46
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
8.2 IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise noted.
IDD Specification
Speed Grade
Bin
DDR3 - 800
6-6-6
DDR3 - 1066
7-7-7
Symbol
Max.
Max.
IDD0
TBD
IDD1
TBD
Unit
Notes
TBD
mA
x4/x8
TBD
mA
x4/x8
IDD2N
TBD
TBD
mA
x4/x8
IDD2NT
TBD
TBD
mA
x4/x8
IDD2QNT
TBD
TBD
mA
x4/x8
IDD2P0
TBD
TBD
mA
x4/x8
IDD2P1
TBD
TBD
mA
x4/x8
IDD2Q
TBD
TBD
mA
x4/x8
IDD3N
TBD
TBD
mA
x4/x8
IDD3P
TBD
TBD
mA
x4/x8
IDD4R
TBD
TBD
mA
x4/x8
IDDQ4R
TBD
TBD
mA
x4/x8
IDD4W
TBD
TBD
mA
x4/x8
IDD5B
TBD
TBD
mA
x4/x8
IDD6
TBD
TBD
mA
x4/x8
IDD6ET
TBD
TBD
mA
x4/x8
IDD6TC
TBD
TBD
mA
x4/x8
IDD7
TBD
TBD
mA
x4/x8
Rev. 0.1 /Aug 2008
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H5TQ4G83MMR-xxC
9. Input/Output Capacitance
DDR3-1066
Parameter
DDR3-1333
Symbol
Min
Max
Min
Max
Units
Notes
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS,
TDQS)
CIO
1.5
3.0
1.5
2.5
pF
1,2,3
Input capacitance, CK and CK
CCK
0.8
1.6
0.8
1.4
pF
2,3
CDCK
0
0.15
0
0.15
pF
2,3,4
CI
0.75
1.5
0.75
1.3
pF
2,3,6
CDDQS
0
0.20
0
0.15
pF
2,3,5
CDI_CTRL
-0.5
0.3
-0.4
0.2
pF
2,3,7,8
CDI_ADD_C
-0.5
0.5
-0.4
0.4
pF
2,3,9,10
-0.5
0.3
-0.5
0.3
pF
2,3,11
Input capacitance delta
CK and CK
Input capacitance
(All other input-only pins)
Input capacitance delta, DQS and
DQS
Input capacitance delta
(All CTRL input-only pins)
Input capacitance delta
(All ADD/CMD input-only pins)
Input/output capacitance delta
(DQ, DM, DQS, DQS)
Notes:
MD
CDIO
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK.
5. The minimum CCK will be equal to the minimum CI.
6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CTRL pins defined as ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))
9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS, CAS and WE.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS))
Rev. 0.1 /Aug 2008
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H5TQ4G83MMR-xxC
10. Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-1066 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 51.
Speed Bin
DDR3-1066F
CL - nRCD - nRP
Parameter
Symbol
Unit
7-7-7
min
max
Internal read command to
first data
tAA
13.125
20
ns
ACT to internal read or
write delay time
tRCD
13.125
—
ns
PRE command period
tRP
13.125
—
ns
ACT to ACT or REF
command period
tRC
50.625
—
ns
ACT to PRE command
period
tRAS
37.5
9 * tREFI
ns
CL = 5
CL = 6
CL = 7
CL = 8
Note
CWL = 5
tCK(AVG)
Reserved
ns
1)2)3)4)6)
CWL = 6
tCK(AVG)
Reserved
ns
4)
CWL = 5
tCK(AVG)
ns
1)2)3)6)
CWL = 6
tCK(AVG)
Reserved
ns
1)2)3)4)
CWL = 5
tCK(AVG)
Reserved
ns
4)
ns
1)2)3)4)
ns
4)
ns
1)2)3)
CWL = 6
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
2.5
3.3
1.875
< 2.5
Reserved
1.875
< 2.5
Supported CL Settings
6, 7, 8
nCK
Supported CWL Settings
5, 6
nCK
Rev. 0.1 /Aug 2008
49
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
DDR3-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 51..
Speed Bin
DDR3-1333H
CL - nRCD - nRP
Parameter
Symbol
Unit
9-9-9
min
max
Internal read command
to first data
tAA
13.5
20
ns
ACT to internal read or
write delay time
tRCD
13.5
—
ns
PRE command period
tRP
13.5
—
ns
ACT to ACT or REF
command period
tRC
49.5
—
ns
ACT to PRE command
period
tRAS
36
9 * tREFI
ns
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Note
CWL = 5
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 6, 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
ns
1,2,3,7
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
(Optional)
ns
1,2,3,4,7
CWL = 5
tCK(AVG)
Note 9.10
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3,7
CWL = 7
tCK(AVG)
ns
1,2,3,4
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
2.5
3.3
1.875
< 2.5
1.875
< 2.5
Reserved
Reserved
1.5
<1.875
Reserved
<1.875
4
ns
1,2,3,4
ns
4
1,2,3
5
Supported CL Settings
6, 7, 8, 9
ns
ns
nCK
Supported CWL Settings
5, 6, 7
nCK
Rev. 0.1 /Aug 2008
1.5
ns
(Optional)
50
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of
tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard
tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the
next ‘Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSE
LECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature.
Refer to supplier’s data sheet and SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not
subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not
subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not
subject to Production Tests but verified by Design/Characterization.
9. It is not a mandatory bin. Refer to supplier’s data sheet and/or the DIMM SPD information.
10. If it’s supported, the minimum tAA/tRCD/tRP that this device support is 13.125ns. Therefore, In Module application,
tAA/tRCD/tRP should be programed with minimum supported values. For example, DDR3-1333H supporting down-shift to
DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20). DDR3-1600K supporting down-shift to DDR3-1333H and/or DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20).
11. Electrical Characteristics and AC Timing
Timing Parameters by Speed Bin
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
Parameter
Symbol
DDR3-1333
Min
Max
Min
Max
Units
Notes
8
-
8
-
ns
6
ps
tCK
(avg)
tCK
(avg)
f
Clock Timing
Minimum Clock Cycle Time
(DLL off mode)
Average Clock Period
tCK
(DLL_OFF)
tCK (avg)
Average high pulse width
tCH (avg)
0.47
0.53
0.47
0.53
Average low pulse width
tCL (avg)
0.47
0.53
0.47
0.53
tCK
(abs)
tCK
(avg)
min + tJIT
(per)
min
tCK
(avg)
max +
tJIT
(per)
max
tCK
(avg)
min + tJIT
(per)
min
tCK
(avg)
max +
tJIT
(per)
max
Absolute Clock Period
Rev. 0.1 /Aug 2008
f
f
ps
51
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
Parameter
Absolute clock HIGH pulse
width
Absolute clock LOW pulse
width
Clock Period Jitter
Clock Period Jitter during
DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter
during DLL locking period
Duty Cycle jitter
Cumulative error across 2
cycles
Cumulative error across 3
cycles
Cumulative error across 4
cycles
Cumulative error across 5
cycles
Cumulative error across 6
cycles
Cumulative error across 7
cycles
Cumulative error across 8
cycles
Cumulative error across 9
cycles
Cumulative error across 10
cycles
Cumulative error across 11
cycles
Cumulative error across 12
cycles
Cumulative error across n =
13, 14,.....49, 50 cycles
Data Timing
DQS, DQS to DQ skew, per
group, per access
DQ output hold time from
DQS, DQS
DQ low-impedance time from
CK, CK
DQ high impedance time
from CK, CK
Rev. 0.1 /Aug 2008
DDR3-1333
Symbol
Min
Max
Min
Max
Units
tCH
(abs)
0.43
-
0.43
-
tCL (abs)
0.43
-
0.43
-
JIT (per)
tJIT
(per, lck)
tJIT (cc)
tJIT
(cc, lck)
tJIT
(duty)
tERR
(2per)
tERR
(3per)
tERR
(4per)
tERR
(5per)
tERR
(6per)
tERR
(7per)
tERR
(8per)
tERR
(9per)
tERR
(10per)
tERR
(11per)
tERR
(12per)
tERR
(nper)
- 90
90
- 80
80
tCK
(avg)
tCK
(avg)
ps
- 80
80
- 70
70
ps
180
160
ps
160
140
ps
-
-
-
-
ps
-132
132
-118
118
ps
-157
157
-140
140
ps
-175
175
-155
155
ps
-188
188
-168
168
ps
-200
200
-177
177
ps
-209
209
-186
186
ps
-217
217
-193
193
ps
-224
224
-200
200
ps
-231
231
-205
205
ps
-237
237
-210
210
ps
-242
242
-215
215
ps
Notes
25
26
ps
24
tDQSQ
-
150
-
125
ps
13
tQH
0.38
-
0.38
-
tCK
(avg)
13, b
tLZ (DQ)
- 600
300
- 500
250
ps
tHZ (DQ)
-
300
-
250
ps
13, 14,
a
13, 14,
a
52
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
Parameter
Data setup time to DQS,
DQS referenced to Vih (ac) /
Vil (ac) levels
Data hold time from DQS,
DQS referenced to Vih (dc) /
Vil (dc) levels
Data Strobe Timing
DQS,DQS differential READ
Preamble
DQS, DQS differential READ
Postamble
DQS, DQS differential output
high time
DQS, DQS differential output
low time
DQS, DQS differential
WRITE Preamble
DQS, DQS differential
WRITE Postamble
DQS, DQS rising edge
output access time from
rising CK, CK
DQS and DQS lowimpedance time (Referenced
from RL - 1)
DQS and DQS highimpedance time (Referenced
from RL + BL/2)
DQS, DQS differential input
low pulse width
DQS, DQS differential input
high pulse width
DQS, DQS rising edge to
CK, CK rising edge
DQS, DQS falling edge setup
time to CK, CK rising edge
DQS, DQS falling edge hold
time from CK, CK rising edge
Command and Address
Timing
DLL locking time
Internal READ Command to
PRECHARGE Command
delay
Delay from start of internal
write transaction to internal
read command
WRITE recovery time
Rev. 0.1 /Aug 2008
DDR3-1333
Symbol
Min
Max
Min
Max
Units
Notes
tDS (base)
25
TBD
ps
d, 17
tDH (base)
100
TBD
ps
d, 17
tRPRE
0.9
Note
0.9
Note
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
13, 19
b
tRPST
0.3
Note
0.3
Note
tQSH
0.38
-
0.38
-
tQSL
0.38
-
0.38
-
tWPRE
0.9
-
0.9
-
tWPST
0.3
-
0.3
-
tDQSCK
- 300
300
- 255
255
ps
13, a
tLZ(DQS)
- 600
300
- 500
250
ps
13, 14, a
tHZ(DQS)
-
300
-
250
ps
13, 14
a
tDQSL
0.4
0.6
0.4
0.6
tDQSH
0.4
0.6
0.4
0.6
tDQSS
- 0.25
0.25
- 0.25
0.25
c
tDSS
0.2
-
0.2
-
tDSH
0.2
-
0.2
-
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
tDLLK
512
-
-
tRTP
max
(4nCK, 7.5ns)
-
tWTR
max
(4nCK, 7.5ns)
-
tWR
15
-
512
max
(4nCK,
7.5ns)
max
(4nCK,
7.5ns)
15
11, 13, b
13, b
13, b
c
c
nCK
-
e
-
e, 18
-
ns
e
53
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
DDR3-1333
Parameter
Symbol
Min
Max
Min
Max
Units
Mode Register Set command
cycle time
tMRD
4
-
4
-
nCK
Mode Register Set command
update delay
tMOD
max
(12nCK
, 15ns)
-
max
(12nCK
, 15ns)
-
ACT to internal read or write
delay time
PRE command period
ACT to ACT or REF
command period
CAS to CAS command delay
Auto precharge write
recovery + precharge time
End of MPR Read burst to
MSR for MPR (exit)
ACTIVE to PRECHARGE
command period
ACTIVE to ACTIVE
command period for 1KB
page size
ACTIVE to ACTIVE
command period for 2KB
page size
Four activate window for 1KB
page size
Four activate window for 2KB
page size
Command and Address
setup time to CK, CK
referenced to Vih (ac) / Vil
(ac) levels
Command and Address hold
time from CK, CK referenced
to Vih (dc) / Vil (dc) levels
Command and Address
setup time to CK, CK
referenced to Vih (ac) / Vil
(ac) levels
Calibration Timing
Power-up and RESET
calibration time
Normal operation Full
calibration time
Normal operation Short
calibration time
Reset Timing
Rev. 0.1 /Aug 2008
Notes
tRCD
e
tRP
e
tRC
e
tCCD
4
-
4
-
tDAL (min)
tMPRR
nCK
nCK
1
-
1
-
nCK
tRAS
22
e
tRRD
max
(4nCK
, 7.5ns)
-
max
(4nCK, 6ns)
-
e
tRRD
max
(4nCK, 10ns)
-
max
(4nCK,
7.5ns)
-
e
tFAW
37.5
-
30
-
ns
e
tFAW
50
-
45
-
ns
e
tIS (base)
125
65
ps
b, 16
tIH (base)
200
140
ps
b, 16
tIS (base)
AC150
-
-
65+125
ps
b, 16,
27
tZQinit
512
-
512
-
nCK
tZQoper
256
-
256
-
nCK
tZQCS
64
-
64
-
nCK
23
54
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
Parameter
Exit Reset from CKE HIGH to
a valid command
Symbol
Min
tXPR
max
(5nCK, tRFC
(min) + 10ns)
DDR3-1333
Max
Min
Max
Units
-
max
(5nCK,
tRFC
(min) +
10ns)
-
tXS
max
(5nCK, tRFC
(min) + 10ns)
-
max
(5nCK,
tRFC
(min) +
10ns)
-
tXSDLL
tDLLK
(min)
-
tDLLK
(min)
-
tCKESR
tCKE
(min) + 1 nCK
-
tCKE
(min) + 1
nCK
-
tCKSRE
max
(5 nCK, 10
ns)
-
max
(5 nCK, 10
ns)
-
tCKSRX
max
(5 nCK, 10
ns)
-
max
(5 nCK, 10
ns)
-
tXP
max
(3nCK, 7.5ns)
-
max
(3nCK, 6ns)
-
tXPDLL
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
tCKE
max
(3nCK,
5.625ns)
-
max
(3nCK,
5.625ns)
-
tCPDED
1
-
1
-
tPD
tCKE
(min)
9 * tREFI
tCKE
(min)
9 * tREFI
tACTPDEN
1
-
1
-
nCK
tPRPDEN
1
-
1
-
nCK
Notes
Self Refresh Timings
Exit Self Refresh to
commands not requiring a
locked DLL
Exit Self Refresh to
commands requiring a
locked DLL
Minimum CKE low width for
Self Refresh entry to exit
timing
Valid Clock Requirement
after Self Refresh Entry
(SRE) or Power-Down Entry
(PDE)
Valid Clock Requirement
before Self Refresh Exit
(SRX) or Power-Down Exit
(PDX) or Reset Exit
Power Down Timings
Exit Power Down with DLL
on to any valid command;
Exit Precharge Power Down
with DLL frozen to
commands not requiring a
locked DLL
Exit Precharge Power Down
with DLL frozen to
commands requiring a
locked DLL
CKE minimum pulse width
Command pass disable
delay
Power Down Entry to Exit
Timing
Timing of ACT command to
Power Down entry
Timing of PRE or PREA
command to Power Down
entry
Rev. 0.1 /Aug 2008
nCK
2
nCK
15
55
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
Parameter
Timing of RD/RDA command
to Power Down entry
Timing of WR command to
Power Down entry (BL8OTF,
BL8MRS, BC4OTF)
Timing of WRA command to
Power Down entry (BL8OTF,
BL8MRS, BC4OTF)
Timing of WR command to
Power Down entry
(BC4MRS)
Timing of WRA command to
Power Down entry
(BC4MRS)
Timing of REF command to
Power Down entry
Timing of MRS command to
Power Down entry
ODT Timings
ODT high time without write
command or with write
command and BC4
ODT high time with Write
command and BL8
Asynchronous RTT turn-on
delay (Power-Down with DLL
frozen)
Asynchronous RTT turn-off
delay (Power-Down with DLL
frozen)
RTT turn-on
RTT_NOM and RTT_WR
turn-off time from ODTLoff
reference
RTT dynamic change skew
Write Leveling Timings
First DQS/DQS rising edge
after write leveling mode is
programmed
DQS/DQS delay after write
leveling mode is
programmed
Write leveling setup time
from rising CK, CK crossing
to rising DQS, DQS crossing
Rev. 0.1 /Aug 2008
Symbol
tRDPDEN
tWRPDEN
Min
RL + 4
+1
WL4+
(tWR / tCK
(avg))
DDR3-1333
Max
-
Min
RL + 4
+1
WL+4 +
(tWR / tCK
(avg))
Max
Units
Notes
-
nCK
-
nCK
9
tWRAPDEN
WL+4+ WR+
1
-
WL+4 + WR
+1
-
nCK
10
tWRPDEN
WL+2+
(tWR / tCK
(avg))
-
WL+2 +
(tWR / tCK
(avg))
-
nCK
9
tWRAPDEN
WL + 2 + WR
+1
-
WL + 2 +
WR + 1
-
nCK
10
tREFPDEN
1
-
1
-
nCK
,
tMRSPDEN
tMOD
(min)
-
tMOD
(min)
-
ODTH4
4
-
4
-
nCK
ODTH8
6
-
6
-
nCK
tAONPD
1
9
1
9
ns
tAOFPD
1
9
1
9
ns
tAON
-300
300
-250
250
ps
7, a
tAOF
0.3
0.7
0.3
0.7
tCK
(avg)
8, a
tADC
0.3
0.7
0.3
0.7
tCK
(avg)
a
tWLMRD
40
-
40
-
nCK
3
tWLDQSEN
25
-
25
-
nCK
3
tWLS
245
-
195
-
ps
56
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
DDR3-1066
Parameter
Write leveling hold time from
rising DQS, DQS crossing to
rising CK, CK crossing
Write leveling output delay
Write leveling output error
Rev. 0.1 /Aug 2008
DDR3-1333
Symbol
Min
Max
Min
Max
Units
tWLH
245
-
195
-
ps
tWLO
tWLOE
0
0
9
2
0
0
9
2
ns
ns
Notes
57
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
0.1
Jitter Notes
Specific Note a
When the device is operated with input clock jitter, this parameter needs to be derated by
the actual tERR (mper), act of the input clock, where 2 <= m <=12.(output deratings are
relative to the SDRAM input clock.) For example, if the measured jitter into a DDR-800
SDRAM has tERR (mper), act, min = -172 ps and tERR (mper), act, max =+ 193 ps, then
t DQSCK, min (derated) = tDQSCK, min - tERR (mper), act, max = -400 ps - 193 ps = 593 ps and tDQSCK, max (derated) = tDQSCK, max - tERR (mper), act, min = 400 ps+
172 ps = + 572 ps. Similarly, tLZ (DQ) for DDR3-800 derates to tLZ (DQ), min (derated) =
- 800 ps - 193 ps = - 993 ps and tLZ (DQ), max (derated) = 400 ps + 172 ps = + 572 ps.
(Caution on the min/max usage!) Note that tERR (mper), act, min is the minimum measured value of tERR (nper) where 2 <= n <=12, and tERR (mper), act, max is the maximum measured value of tERR (nper) where 2 <= n <= 12
Specific Note b
When the device is operated with input clock jitter, this parameter needs to be derated by
the actual tJIT (per), act of the input clock. (output deratings are relative to the SDRAM
input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK (avg),
act = 2500 ps, tJIT (per), act, min = - 72 ps and tJIT (per), act, max = + 93 ps, then
tRPRE, min (derated) = tRPRE, min + tJIT (per), act, min = 0.9 x tCK (avg), act + tJIT
(per), act, min (derated) = tRPRE, min + tJIT (per), act, min = 0.9 x tCK (avg), act + tJIT
(per), act, min = 0.9 x 2500 ps - 72 ps =+ 2178 ps. Similarly, tQH, min (derated) = tQH,
min + tJIT (per), act, min = 0.38 x tCK (avg), act + tJIT (per), act, min = 0.38 x 2500 ps 72 ps = + 878 ps. (Caution on the min/max usage!)
Specific Note c
These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec values are not affected by
the amount of clock jitter applied (i.e. tJIT (per), tJIT (cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is
present or not.
Specific Note d
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.)
transition edge to its respective data strobe signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU
{tPARAM [ns] / tCK (avg) [ns]}, which is in clock cycles, assuming all input clock jitter
specifications are satisfied.For example, the device will support tnRP = RU {tRP / tCK
(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means:
For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU {tRP / tCK
(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command
at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to
input clock jitter.
Specific Note f
These parameters are specified per their average values, however it is understood that
the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in
Table .
Rev. 0.1 /Aug 2008
58
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
5. Value must be rounded-up to next higher integer value.
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
8. WR in clock cycles as programmed in MR0.
9. The maximum postamble is bound by tHZDQS (max)
10. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter,
this parameter needs to be derated by t.b.d.
11. Value is only valid for RON34
12. Single ended signal parameter. Refer to chapter <t.b.d.> for definition and measurement method.
13. tREFI depends on TOPER
14. tIS (base) and tIH (base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew
rate. Note for DQ and DM signals, VREF(DC) = VRefDQ (DC). For input only pins except RESET,
VRef (DC) = VRefCA (DC). See “Address / Command Setup, Hold and Derating” on page 60.
15. tDS (base) and tDH (base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate.
Note for DQ and DM signals, VREF(DC) = VRefDQ (DC). For input only pins except RESET, VRef (DC) = VRefCA (DC).
See “Data Setup, Hold and Slew Rate Derating” on page 67..
16. Start of internal write transaction is definited as follows:
For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
17. The maximum preamble is bound by tLZDQS (min)
18. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are
in progress, but power-down IDD spec will not be applied until finishing those operations.
19. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN (min) is satisfied, there are
cases where additional time such as tXPDLL (min) is also required.
20. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
21. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and
Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS
commands can be determined from these tables and other application specific parameters. One method for calculating
the interval between ZQCS commands, given the temperature (Tdrifrate) and voltage (Vdriftrate) drift rates that the
SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula.
Rev. 0.1 /Aug 2008
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ZQCorrection
-----------------------------------------------------------------------------------------------------------(Tsens x Tdriftrate)+( VSens x Vdriftrate)
where TSens = max (dRTTdT, dRONdTM) and VSens = max (dRTTdV, dRONdVM) define the SDRAM temperature and
voltage sensitivities. For example, if TSens = 1.5% / oC, VSens = 0.15% / mV, Tdriftrate = 1 oC / sec and Vdriftrate =
15 mV / sec, then the interval between ZQCS commands is calculated as:
0.5
------------------------------------------------------ = 0.133 = 128ms
(1.5 x 1)+(0.15 x 15)
22. n = from 13 cycles to 50 cycles.
23. tCH (abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following fall
ing edge.
24. tCL (abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following risi
ng edge.
25. The tIS (base) AC150 specifications are adjusted from the tIS (base) specification by adding an additional 100 ps of
derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier refer
ence point [(175 mV - 150 mV) / 1 V/ns].
Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base)
and tIH (base) value (see Table 11) to the ∆tIS and ∆tIH derating value (see Table 12) respectively. Example: tIS (total
setup time) = tIS (base) + ∆tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of Vil (ac) max. If the actual signal is always earlier than the nominal slew rate
line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value (see Figure 4). If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the
actual signal from the ac level to dc level is used for derating value (see Figure 6).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil (dc) max and the
first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih (dc) min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line
between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value (see Figure 5). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the
actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 6).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 14).
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Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in Table 12, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 11 - ADD/CMD Setup and Hold Base-Values for 1V/ns
unit [ps]
DDR3-1066
DDR3-1333
reference
tIS (base)
125
65
VIH/L(ac)
tIH (base)
200
140
VIH/L(dc)
tIH(base)AC150
-
65 + 125
VIH/L(dc)
Note: - (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
- The tIS (base) AC150 specifications are adjusted from the tIS (base) specification by adding an additional 100 ps
of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the ear
lier reference point [(175 mV - 150 mV) / 1 V/ns]
Table 12 - Derating values DDR3-800/1066/1333/1600 tIS/tIH - ac/dc based
∆tIS, ∆tIH derating in [ps] AC/DC based
AC175 Threshold -> VIH (ac) = VREF (dc) + 175mV, VIL (ac) = VREF (dc) - 175mV
CK,CK Differential Slew Rate
4.0 V/ns
∆tIS ∆tIH
3.0 V/ns
∆tIS
2.0 V/ns
∆tIH ∆tIS
∆tIH
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH
2.0
88
50
88
50
88
50
96
58
104
66
112
74
120
84
128
100
1.5
59
34
59
34
59
34
67
42
75
50
83
58
91
68
99
84
1.0
CMD
0.9
/
ADD 0.8
Slew
rate 0.7
V/ns
0.6
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
-2
-4
-2
-4
-2
-4
6
4
14
12
22
20
30
30
38
46
-6
-10
-6
-10
-6
-10
2
-2
10
6
18
14
26
24
34
40
-11
-16
-11
-16
-11
-16
-3
-8
5
0
13
8
21
18
29
34
-17
-26
-17
-26
-17
-26
-9
-18
-1
-10
7
-2
15
8
23
24
0.5
-35
-40
-35
-40
-35
-40
-27
-32
-19
-24
-11
-16
-2
-6
5
10
0.4
-62
-60
-62
-60
-62
-60
-54
-52
-46
-44
-38
-36
-30
-26
-22
-10
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Table 13 - Derating values DDR3-1066/1333 tIS/tIH - ac/dc based
∆tIS, ∆tIH derating in [ps] AC/DC based
Alternate AC150 Threshold -> VIH (ac) = VREF (dc) + 150mV, VIL (ac) = VREF (dc) - 150mV
CK,CK Differential Slew Rate
4.0 V/ns
∆tIS ∆tIH
3.0 V/ns
∆tIS
2.0 V/ns
∆tIH ∆tIS
1.8 V/ns
∆tIH
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH
2.0
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0
-4
0
-4
0
-4
8
4
16
12
24
20
32
30
40
46
0
-10
0
-10
0
-10
8
-2
16
6
24
14
32
24
40
40
CMD
0.9
/
ADD 0.8
Slew
rate 0.7
V/ns
0.6
0
-16
0
-16
0
-16
8
-8
16
0
24
8
32
18
40
34
-1
-26
-1
-26
-1
-26
7
-18
15
-10
23
-2
31
8
39
24
0.5
-10
-40
-10
-40
-10
-40
-2
-32
6
-24
14
-16
22
-6
30
10
0.4
-25
-60
-25
-60
-25
-60
-17
-52
-9
-44
-1
-36
7
-26
15
-10
Table 14 - Required time tVAC above VIH (ac) {below VIL (ac)} for valid transition
tVAC @ 175 mV [ps]
Slew Rate
[V/ns]
tVAC @ 150 mV [ps]
min
max
min
max
> 2.0
75
-
175
-
2.0
57
-
170
-
1.5
50
-
167
-
1.0
38
-
163
-
0.9
34
-
162
-
0.8
29
-
161
-
0.7
22
-
159
-
0.6
13
-
155
-
0.5
0
-
150
-
< 0.5
0
-
150
-
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Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
tDH
VDDQ
tVAC
VIH(ac) min
VREF to ac
region
VIH(dc) min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc) max
VREF to ac
region
VIL(ac) max
tVAC
VSS
∆TF
Setup Slew Rate = VREF(dc) - VIL(ac)max
Falling Signal
∆TF
∆TR
Setup Slew Rate VIH(ac)min - VREF(dc)
Rising Signal =
∆TR
Figure 3 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and
tIS (for ADD/CMD with respect to clock).
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Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
tDH
VDDQ
VIH(ac) min
VIH(dc) min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
dc to VREF
region
VIL(dc) max
VIL(ac) max
VSS
∆TR
VREF(dc) - VIL(dc)max
Hold Slew Rate
=
Rising Signal
∆TR
∆TF
VIH(dc)min - VREF(dc)
Hold Slew Rate
=
Falling Signal
∆TF
Figure 4 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
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H5TQ4G83MMR-xxC
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
VDDQ
nominal
line
VIH(ac) min
tDH
tVAC
VREF to ac
region
VIH(dc) min
tangent
line
VREF(dc)
tangent
line
VIL(dc) max
VREF to ac
region
VIL(ac) max
nominal
line
tVAC
VSS
Setup Slew Rate
Rising Signal =
∆TF
∆TR
tangent line [VIH(ac)min - VREF(dc)]
∆TR
Setup Slew Rate tangent line [VREF(dc) - VIL(ac)max]
Falling Signal =
∆TF
Figure 5 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
Rev. 0.1 /Aug 2008
65
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
tDH
VDDQ
VIH(ac) min
nominal
line
VIH(dc) min
dc to VREF
region
tangent
line
VREF(dc)
dc to VREF
region
tangent
line
nominal
line
VIL(dc) max
VIL(ac) max
VSS
Hold Slew Rate
Rising Signal =
∆TR
tangent line [VREF(dc) - VIL(dc)max]
∆TF
∆TR
tangent line [VIH(dc)min - VREF(dc)]
Hold Slew Rate
=
Falling Signal
∆TF
Figure 6 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
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H5TQ4G83MMR-xxC
Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS
(base) and tDH (base) value (see Table 15) to the DtDS and DtDH (see Table 16) derating value respectively. Example:
tDS (total setup time) = tDS (base) + DtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of VIL(ac)max (see Figure 7). If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to
the actual signal from the ac level to dc level is used for derating value (see Figure 9).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of VREF(dc) (see Figure 8). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to
the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 9).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 17).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 15 - Data Setup and Hold Base-Values
Units [ps]
DDR3-1066
DDR3-1333
reference
tDS (base)
25
-10
VIH/L(ac)
tDH (base)
100
65
VIH/L(dc)
Note: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS-slew rate)
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Table 16 - Derating values DDR3-1066 tDS/tDH - ac/dc based
∆tDS, ∆DH derating in [ps] AC/DC based a
DQS, DQS Differential Slew Rate
4.0 V/ns
DQ
Slew
rate
V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
∆tDS
∆tDH
∆tDS
∆tDH
∆tDS
∆tDH
∆tDS
∆tDH
∆tDS
∆tDH
∆tDS
∆tDH
∆tDS
∆tDH
∆tDS
∆tDH
2.0
88
50
88
50
88
50
-
-
-
-
-
-
-
-
-
-
1.5
59
34
59
34
59
34
67
42
-
-
-
-
-
-
-
-
1.0
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
-2
-4
-2
-4
6
4
14
12
22
20
-
-
-
-
0.8
-
-
-
-
-6
-10
2
-2
10
6
18
14
26
24
-
-
0.7
-
-
-
-
-
-
-3
-8
5
0
13
8
21
18
29
34
0.6
-
-
-
-
-
-
-
-
-1
-10
7
-2
15
8
23
24
0.5
-
-
-
-
-
-
-
-
-
-
-11
-16
-2
-6
5
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-30
-26
-22
-10
a.Cell contents shaded in red are defined as ‘not supported’.
Table 17 - Required time tVAC above VIH (ac) {below VIL (ac)} for valid transition
Slew Rate [V/ns]
Rev. 0.1 /Aug 2008
tVAC [ps]
min
max
> 2.0
75
-
2.0
57
-
1.5
50
-
1.0
38
-
0.9
34
-
0.8
29
-
0.7
22
-
0.6
13
-
0.5
0
-
< 0.5
0
-
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H5TQ4G83MMR-xxC
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
tDH
VDDQ
tVAC
VIH(ac) min
VREF to ac
region
VIH(dc) min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc) max
VREF to ac
region
VIL(ac) max
tVAC
VSS
∆TF
Setup Slew Rate = VREF(dc) - VIL(ac)max
Falling Signal
∆TF
∆TR
Setup Slew Rate VIH(ac)min - VREF(dc)
Rising Signal =
∆TR
Figure 7 - Illustration of nominal slew rate and tVAC for hold setup tDS (for DQ with respect to strobe) and
tIS (for ADD/CMD with respect to clock).
Rev. 0.1 /Aug 2008
69
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
tDH
VDDQ
VIH(ac) min
VIH(dc) min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
dc to VREF
region
VIL(dc) max
VIL(ac) max
VSS
∆TR
VREF(dc) - VIL(dc)max
Hold Slew Rate
Rising Signal =
∆TR
∆TF
VIH(dc)min - VREF(dc)
Hold Slew Rate
=
Falling Signal
∆TF
Figure 8 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
Rev. 0.1 /Aug 2008
70
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H5TQ4G83MMR-xxC
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
VDDQ
nominal
line
VIH(ac) min
tDH
tVAC
VREF to ac
region
VIH(dc) min
tangent
line
VREF(dc)
tangent
line
VIL(dc) max
VREF to ac
region
VIL(ac) max
nominal
line
tVAC
VSS
Setup Slew Rate
Rising Signal =
∆TF
∆TR
tangent line [VIH(ac)min - VREF(dc)]
∆TR
Setup Slew Rate tangent line [VREF(dc) - VIL(ac)max]
Falling Signal =
∆TF
Figure 9 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
Rev. 0.1 /Aug 2008
71
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H5TQ4G83MMR-xxC
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
tDS
tDH
tIS
tIH
CK
CK
DQS
DQS
tDS
tDH
VDDQ
VIH(ac) min
nominal
line
VIH(dc) min
dc to VREF
region
tangent
line
VREF(dc)
dc to VREF
region
VIL(dc) max
tangent
line
nominal
line
VIL(ac) max
VSS
Hold Slew Rate
Rising Signal =
∆TR
tangent line [VREF(dc) - VIL(dc)max]
∆TF
∆TR
tangent line [VIH(dc)min - VREF(dc)]
Hold Slew Rate
Falling Signal =
∆TF
Figure 10 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
Rev. 0.1 /Aug 2008
72
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12. Package Dimensions
12.1 Package Dimension(x4/x8); 82Ball Fine Pitch Ball Grid Array Outline
12.200 ± 0.100
A1 CORNER
INDEX AREA
1.250 ± 0.100
(3.050)
13.300 ± 0.100
(3.325)
0.290 ± 0.050
3.0 X 5.0 MIN
FLAT AREA
TOP VIEW
SIDE VIEW
0.800 X 10 = 8.000
0.800
2.100 ± 0.100
A1 BALL MARK
11 10 9 8
4
3
2
1
A
B
C
E
F
G
H
J
K
0.800 X 12 = 9.600
0.800
D
L
M
1.000 ± 0.100
N
82 x φ0.400 ± 0.050
1.600 1.600
BOTTOM VIEW
Rev. 0.1 /Aug 2008
73