NSC DS90CF363AMTD

DS90C363A/DS90CF363A
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link-65 MHz
+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)
Link-65 MHz
General Description
Features
The DS90C363A/DS90CF363A transmitter converts 21 bits
of CMOS/TTL data into three LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fourth
LVDS link. Every cycle of the transmit clock 21 bits of input
data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD
timing and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data channel.
Using a 65 MHz clock, the data throughput is 170 Mbytes/
sec. The DS90C363A transmitter can be programmed for
Rising edge strobe or Falling edge strobe through a dedicated pin. The DS90CF363A is fixed as a Falling edge
strobe transmitter. A Rising edge or Falling edge strobe
transmitter will interoperate with a Falling edge strobe Receiver (DS90CF364) without any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
n 20 to 65 MHz shift clock support
n Rejects > ± 3ns Jitter from VGA chip with less than
225ps output Jitter @65MHz (TJCC)
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption < 130 mW (typ) @65MHz
Grayscale
n > 50% Less Power Dissipation than BiCMOS
Alternatives
n Tx Power-down mode < 200µW (max)
n ESD rating > 7 kV (HBM), > 500V (EIAJ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.3 Gbps throughput
n Up to 170 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
n Improved replacement for:
SN75LVDS85 — DS90C363A
SN75LVDS84 — DS90CF363A
Block Diagrams
DS90C363A/DS90CF363A
DS100138-1
Order Number DS90C363AMTD or DS90CF363AMTD
See NS Package Number MTD48
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100138
www.national.com
DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD)
Link-65 MHz, +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)Link-65 MHz
June 1998
Absolute Maximum Ratings (Note 1)
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
> 7 kV
> 500V
Recommended Operating
Conditions
Supply Voltage (VCC)
−0.3V to +4V
CMOS/TTL Input Voltage
−0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Output Short Circuit
Duration
Continuous
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec)
+260˚C
Maximum Package Power Dissipation Capacity @ 25˚C
MTD48 (TSSOP) Package:
DS90C363A/DS90CF363A
1.98 W
Package Derating:
DS90C363A/DS90CF363A
16 mW/˚C above +25˚C
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage (VCC)
TxCLKIN frequency
Min
3.0
Nom
3.3
Max
3.6
Units
V
−10
0
+25
+70
2.4
100
68
˚C
V
18
mVPP
MHz
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
V
IN
= 0.4V, 2.5V or VCC
V
IN
= GND
−0.79
−1.5
V
+1.8
+10
µA
−10
0
250
345
µA
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
∆VOD
Change in VOD between
complimentary output states
VOS
Offset Voltage (Note 4)
∆VOS
Change in VOS between
complimentary output states
IOS
Output Short Circuit Current
VOUT = 0V, RL = 100Ω
IOZ
Output TRI-STATE ® Current
Power Down = 0V,
VOUT = 0V or VCC
RL = 100Ω
1.125
1.25
450
mV
35
mV
1.375
V
35
mV
−3.5
−5
mA
±1
± 10
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current
Worst Case
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5 MHz
31
43
mA
f = 37.5 MHz
33
45
mA
f = 65 MHz
39
52
mA
Transmitter Supply Current
16 Grayscale
RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figures 2, 4)
f = 32.5 MHz
23
35
mA
f = 37.5 MHz
28
40
mA
f = 65 MHz
33
45
mA
10
55
µA
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE ® under
Power Down Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and T A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD ).
Note 4: VOS previously referred as VCM.
www.national.com
2
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TCIT
TxCLK IN Transition Time (Figure 5 )
TCIP
TxCLK IN Period (Figure 6 )
TCIH
TCIL
Min
Typ
Max
Units
5
ns
14.7
T
55.6
ns
TxCLK IN High Time (Figure 6 )
0.35T
0.5T
0.65T
ns
TxCLK IN Low Time (Figure 6 )
0.35T
0.5T
0.65T
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Typ
Max
Units
LLHT
Symbol
LVDS Low-to-High Transition Time (Figure 4 )
Parameter
Min
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 4 )
0.75
1.5
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
−0.30
0
0.20
ns
TPPos1
Transmitter Output Pulse Position for Bit 1
1.90
2.20
2.40
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
4.10
4.40
4.60
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
6.30
6.60
6.80
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
8.50
8.80
9.00
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
10.70
11.00
11.20
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1
Transmitter Output Pulse Position for Bit 1
TPPos2
Transmitter Output Pulse Position for Bit 2
6.79
7.14
7.49
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
10.36
10.71
11.06
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
13.93
14.28
14.63
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
17.51
17.86
18.21
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
21.08
21.43
21.78
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
−0.40
0
0.40
ns
TPPos1
Transmitter Output Pulse Position for Bit 1
4.00
4.40
4.80
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
8.40
8.80
9.20
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
12.80
13.20
13.60
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
17.20
17.60
18.00
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
21.60
22.00
22.40
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
26.00
26.40
26.80
ns
TSTC
TxIN Setup to TxCLK IN (Figure 6 )
2.5
THTC
TxIN Hold to TxCLK IN (Figure 6 )
0
TCCD
TxCLK IN to TxCLK OUT Delay (Figure 7 ) T A=25˚C, VCC=3.3V
3
TJCC
Transmitter Jitter Cycle-to-Cycle (Figures 12, 13 ) (Note 6)
f = 65 MHz
f = 40 MHz
f = 32.5
MHz
TxCLK IN to TxCLK OUT Delay (Figure 7 )
12.90
13.20
13.40
−0.35
0
0.35
ns
3.22
3.57
3.92
ns
ns
ns
3
f = 65 MHz
f = 40 MHz
f = 32.5
MHz
5.5
ns
7.0
ns
175
225
ps
240
380
ps
260
400
ps
TPLLS
Transmitter Phase Lock Loop Set (Figure 8 )
10
ms
TPDD
Transmitter Power Down Delay (Figure 10 )
100
ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a cycleto-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips
currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.
3
www.national.com
AC Timing Diagrams
DS100138-4
FIGURE 1. “Worst Case” Test Pattern
DS100138-5
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
DS100138-30
FIGURE 3. DS90C363A/DS90CF363A (Transmitter) LVDS Output Load
www.national.com
4
AC Timing Diagrams
(Continued)
DS100138-6
FIGURE 4. DS90C363A/DS90CF363A (Transmitter) LVDS Transition Times
DS100138-8
FIGURE 5. DS90C363A/DS90CF363A (Transmitter) Input Clock Transition Time
DS100138-10
FIGURE 6. DS90C363A/DS90CF363A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
DS100138-12
FIGURE 7. DS90C363A/DS90CF363A (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
DS100138-14
FIGURE 8. DS90C363A/DS90CF363A (Transmitter) Phase Lock Loop Set Time
5
www.national.com
AC Timing Diagrams
(Continued)
DS100138-17
FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
DS100138-18
FIGURE 10. Transmitter Power Down Delay
DS100138-26
FIGURE 11. Transmitter LVDS Output Pulse Position Measurement
www.national.com
6
AC Timing Diagrams
(Continued)
DS100138-27
FIGURE 12. TJCC Test Setup
DS100138-28
FIGURE 13. Timing diagram of the Input cycle-to-cycle clock jitter
DS90C363A Pin Description — FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
21
Description
TxOUT+
O
3
Positive LVDS differentiaI data output.
TxOUT−
O
3
Negative LVDS differential data output.
FPSHIFT IN
I
1
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FB
I
1
Programmable strobe select (See Table 1).
TxCLK OUT+
O
1
Positive LVDS differential clock output.
TxCLK OUT−
O
1
Negative LVDS differential clock output.
PWR DOWN
I
1
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
VCC
I
3
Power supply pins for TTL inputs.
GND
I
4
Ground pins for TTL inputs.
PLL VCC
I
1
Power supply pin for PLL.
PLL GND
I
2
Ground pins for PLL.
LVDS VCC
I
1
Power supply pin for LVDS outputs.
LVDS GND
I
3
Ground pins for LVDS outputs.
7
www.national.com
DS90CF363A Pin Description — FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
21
Description
TxOUT+
O
3
Positive LVDS differential data output.
TxOUT−
O
3
Negative LVDS differential data output.
FPSHIFT IN
I
1
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+
O
1
Positive LVDS differential clock output.
TxCLK OUT−
O
1
Negative LVDS differential clock output.
PWR DOWN
I
1
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
VCC
I
4
Power supply pins for TTL inputs.
GND
I
4
Ground pins for TTL inputs.
PLL VCC
I
1
Power supply pin for PLL.
PLL GND
I
2
Ground pins for PLL.
LVDS VCC
I
1
Power supply pin for LVDS outputs.
LVDS GND
I
3
Ground pins for LVDS outputs.
Applications Information
1.
The DS90C363A/DS90CF363A are backward compatible
with the DS90C363/DS90CF363 and are a pin-for-pin replacement. The device (DS90C363A/DS90CF363A) utilizes
a different PLL architecture employing an internal 7X clock
for enhanced pulse position control.
This device (DS90C363A/DS90CF363A) also features reduced variation of the TCCD parameter which is important
for dual pixel applications. (See AN-1084) TCCD variation
has been measured to be less than 250ps at 65MHz under
normal operating conditions.
This device may also be used as a replacement for the
DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC of the transmitter.
2.
The DS90C363A transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
3. To implement a falling edge device for the DS90C363A,
the R_FB pin (pin 14) may be tied to ground OR left unconnected (an internal pull-down resistor biases this pin
low). Biasing this pin to Vcc implements a rising edge
device.
Transmitter Clock Jitter Cycle-to-Cycle
peated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-tocycle jitter at 2µs period.
Figures 12 and 13 illustrate the timing of the input clock relative to the input data. The input clock (TxCLKin) is intentionally shifted to the left −3ns and +3ns to the right when data
(Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter is re-
www.national.com
8
Pin Diagram
DS90C363A
DS90CF363A
DS100138-23
DS100138-24
Application
DS100138-3
Truth Table
TABLE 1. Programmable Transmitter (DS90C363A)
Pin
Condition
Strobe Status
R_FB
R_FB = VCC
Rising edge strobe
R_FB
R_FB = GND or NC
Falling edge strobe
9
www.national.com
DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD)
Link-65 MHz, +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)Link-65 MHz
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90C363AMTD, DS90CF363AMTD
NS Package Number MTD48
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.