IS31AP2005 2.95W MONO FILTER-LESS CLASS-D AUDIO POWER AMPLIFIER GENERAL DESCRIPTION The IS31AP2005 is a high efficiency, 2.95W mono class-D audio power amplifier. A low noise, filter-less PWM architecture eliminates the output filter, reducing external component count, system cost, and simplifying design. Operating in a single 5V supply, IS31AP2005 is capable of driving 4Ω speaker load at a continuous average output of 2.95W with 10% THD+N. The IS31AP2005 has high efficiency with speaker load compared to a typical class AB amplifier. In cellular handsets, the earpiece, speaker phone, and melody ringer can each be driven by the IS31AP2005. The gain of IS31AP2005 is externally configurable which allows independent gain control from multiple sources by summing signals from each function. FEATURES JULY 2011 5V supply at THD = 10% -2.95W into 4Ω (Typ.) -1.70W into 8Ω (Typ.) Efficiency at 5V: -83% at 400mW with a 4Ω speaker -89% at 400mW with an 8Ω speaker Optimized PWM output stage eliminates LC output filter Fully differential design reduces RF rectification and eliminates bypass capacitor Integrated pop-and-click suppression circuitry 3mm × 3mm DFN-8 and MSOP-8 package RoHS compliant and 100% lead(Pb)-free The IS31AP2005 is available in DFN and MSOP packages. APPLICATIONS Wireless or cellular handsets and PDAs Portable DVD player Notebook PC Portable radio Educational toys USB speakers Portable gaming TYPICAL APPLICATION CIRCUIT Figure 1 Typical IS31AP2005 Application Schematic with Differential Input Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 1 IS31AP2005 Figure 2 Typical IS31AP2005 Application Schematic with Single-ended Input Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 2 IS31AP2005 PIN CONFIGURATION Package Pin Configuration (Top view) DFN-8 MSOP-8 PIN DESCRIPTION DFN-8 MSOP-8 Pin I/O Description 1 1 SDB I Shutdown terminal, active low logic. 2 2 NC - No internal connection. 3 3 IN+ I Positive differential input. 4 4 IN- I Negative differential input. 5 5 OUT+ O Positive BTL output. 6 6 VDD - Power supply. 7 7 GND - High-current ground. 8 8 OUT- O Negative BTL output. No Thermal Pad - Connect to GND. Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 3 IS31AP2005 ORDERING INFORMATION INDUSTRIAL RANGE: -40°C TO +85°C Order Part No. Package QTY/Reel IS31AP2005-DLS2-TR IS31AP2005-SLS2-TR DFN-8, Lead-free MSOP-8, Lead-free 2500 2500 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 4 IS31AP2005 ABSOLUTE MAXIMUM RATINGS (NOTE 1) Supply voltage, VDD Voltage at any input pin Junction temperature, TJMAX Storage temperature range, Tstg ESD susceptibility Lead temperature 1,6 mm (1/16 inch) from case for 10s Thermal resistance θJA (DFN) -0.3V ~ +6.0V -0.3V ~ VDD+0.3V -40°C ~ +150°C -65°C ~ +150°C 6kV 260°C 47°C/W Note: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage, VDD Min. Max. Unit 2.7 5.5 V High-level input voltage, VIH SHUTDOWN 1.4 VDD V Low-level input voltage, VIL SHUTDOWN 0 0.4 V Input resistor, RI Gain 20V/V (26dB) 15 Common mode input voltage range, VIC VDD = 2.7V, 5.5V 0.5 VDD-0.8 V -40 85 °C Operating free-air temperature, TA kΩ ELECTRICAL CHARACTERISTICS TA = 25°C (Note 2) Symbol Parameter Condition Min. Typ. Max. Unit | VOS | Output offset voltage (measured differentially) VI = 0V, AV = 2V/V, VDD = 2.7V ~ 5.5V |IIH | High-level input current VDD = 5.5V, VI = 5.8V 35 μA | IIL | Low-level input current VDD = 5.5V, VI = -0.3V 2 μA VDD = 5.5V, no load 2.6 VDD = 2.7V, no load 1.2 IQ Quiescent current ISD Shutdown current VSHUTDOWN = 0.4V, VDD = 2.7V ~ 5.5V fsw Switching frequency VDD = 2.7V ~ 5.5V Gain 10 VDD = 2.7V ~ 5.5V, RI = 150kΩ Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 mV mA 1 μA 250 kHz 2 V/V 5 IS31AP2005 ELECTRICAL CHARACTERISTICS TA = 25°C, Gain= 2V/V. (Note 3) Symbol PO THD+N Parameter Output power Total harmonic distortion plus noise Condition Min. Typ. VDD = 5.0V THD+N = 10% V = 4.2V f = 1kHz, RL = 8Ω+33μH DD VDD = 3.6V 1.70 VDD = 5.0V THD+N = 10% V = 4.2V f = 1kHz, RL = 4Ω+33μH DD VDD = 3.6V 2.95 VDD = 5.0V THD+N = 1% V = 4.2V f = 1kHz, RL = 8Ω+33μH DD VDD = 3.6V 1.45 VDD = 5.0V THD+N=1% V = 4.2V f = 1kHz, RL = 4Ω+33μH DD VDD = 3.6V 2.50 1.20 Max. Unit W 0.83 2.05 W 1.55 0.95 W 0.66 1.70 W 1.25 VDD = 5.0V, PO =1.0W, RL = 8Ω+33μH f = 1kHz 0.28 VDD = 5.0V, PO =1.2W, RL = 4Ω+33μH f = 1kHz 0.31 % VN Output voltage noise VDD = 3.6V~5V, f =20Hz to 20kHz, inputs ac-grounded with CI = 1μF A-Weighting 68 μVrms tWU Wake-up time from shutdown VDD = 3.6V 36 ms SNR Signal-to-noise ratio PO =1.0W, RL = 8Ω+33μH, VDD = 5.0V 92 dB PSRR Power supply rejection ratio VDD = 2.7V ~ 5.5V -55 dB Notes: 1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. All parts are production tested at TA = 25°C. Other temperature limits are guaranteed by design 3. Guaranteed by design Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 6 IS31AP2005 TYPICAL PERFORMANCE CHARACTERISTICS 20 10 RL = 4Ω+33µH f = 1kHz 10 VDD = 3.6V VDD = 3.6V 5 THD+N(%) 5 THD+N(%) 20 RL = 8Ω+33µH f = 1kHz 2 VDD = 4.2V 1 2 VDD = 4.2V 1 0.5 0.5 0.2 0.2 VDD = 5.0V VDD = 5.0V 0.1 10m 20m 50m 100m 200m 500m 1 2 0.1 10m 3 20m 50m Output Power(W) Figure 3 Figure 4 THD+N(%) THD+N(%) 10 VDD = 5.0V PO = 1W 1 0.2 1 2 3 4 THD+N vs. Output Power RL = 4Ω+33µH VDD = 5.0V PO = 1.2W 2 1 0.2 0.1 0.1 VDD = 3.6V PO = 500mW 0.05 VDD = 3.6V PO = 650mW 0.05 0.02 0.02 20 50 100 200 500 1k 2k 5k 0.01 10k 20k 20 50 100 200 THD+N vs. Frequency Figure 6 1k 2k 5k 10k 20k THD+N vs. Frequency 0 200 RL = 8Ω+33μH Input Grounded VDD = 3.6V~5.0V RL = 8Ω+33µH -20 100 PSRR(dB) 70 50 30 -40 VDD = 3.6V -60 VDD = 4.2V 20 10 20 500 Frequency(H z) Frequency(H z) Figure 5 Output Voltage(uV) 500m 20 RL = 8Ω+33µH 2 0.01 200m Output Power(W) THD+N vs. Output Power 20 10 100m VDD = 5.0V -80 50 100 200 1k 2k 5k 10k 20k -100 20 50 100 Noise vs. Frequency Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 500 1k 2k 5k 20k Frequency(Hz) Frequency(Hz) Figure 7 200 Figure 8 PSRR vs. Frequency 7 IS31AP2005 1.8 RL = 4Ω+33μH f = 1kHz THD+N = 10% 1.4 Output Power(W) 3 THD+N = 10% Output Power(W) 1.6 3.5 RL = 8Ω+33μH f = 1kHz 1.2 1 0.8 THD+N = 1% 0.6 2.5 2 1.5 1 0.4 THD+N = 1% 0.5 0.2 0 2.5 3 3.5 4 4.5 5 0 2.5 3 4 4.5 5 Power Supply(V) Power Supply(V) Figure 9 3.5 Output Power vs. Supply Voltage Figure 10 Output Power vs. Supply Voltage RL=8Ohm Efficiency(%) RL=4Ohm Vcc=5V Gain=2V/V VDD = 5.0V 0 Figure 11 Efficiency vs. Output Power Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 8 IS31AP2005 APPLICATION INFORMATION Fully Differential Amplifier The IS31AP2005 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input. The fully differential IS31AP2005 can still be used with a single-ended input; however, the IS31AP2005 should be used with differential inputs when in a noisy environment, like a wireless handset, to ensure maximum noise rejection. Advantages of Fully Differential Amplifiers The fully differential amplifier does not require a bypass capacitor. This is because any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output. GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. Component Selection Figure 12 shows the IS31AP2005 with differential inputs and optional input capacitors. Input capacitors are used when the common mode input voltage range specs can not be guaranteed or high pass filter is considered. Figure 13 shows the IS31AP2005 with single-ended inputs. The input capacitors have to be used in the single ended case because it is much more susceptible to noise in this case. Figure 12 Typical Application Schematic with Differential Input Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 Figure 13 Typical Application Schematic with Single-Ended Input Input Resistors (RI) The input resistors (RI) set the gain of the amplifier according to equation (1). Gain 2 150k V RI V (1) Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% accuracy resistors or better to keep the performance optimized. Matching is more important than overall accuracy. Place the input resistors close to the IS31AP2005 to reduce noise injection on the high-impedance nodes. For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the IS31AP2005 to operate at its best, and keeps a high voltage at the input making the inputs less susceptible to noise. Decoupling Capacitor (CS) The IS31AP2005 is a high-performance class-D audio amplifier that requires adequate power supply decoupling to ensure high efficiency and low total harmonic distortion (THD). For higher frequency transients, spikes, or digital noises on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1μF, placed as close as possible to the device VDD pin works best. Placing this decoupling capacitor close to the IS31AP2005 is also important for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10μF or greater capacitor placed near the audio power amplifier would also be helpful, but it is not required in most applications because of better PSRR of this device. 9 IS31AP2005 Input Capacitors (CI) The input capacitors and input resistors form a high-pass filter with the corner frequency, fC, determined in equation (2). 1 f c 2R C I I (2) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Equation (3) is reconfigured to solve for the input coupling capacitance. 1 C I 2R f I c For a flat low-frequency response, use large input coupling capacitors (1μF). However, in a GSM phone the ground signal is fluctuating at 217Hz, but the signal from the codec does not have the same 217Hz fluctuation. The difference between the two signals is amplified, sent to the speaker, and heard as a 217Hz hum. RI1 = 3MΩ, and RI2 = 150kΩ Summing a Differential Input Signal and a Single-Ended Input Signal Figure 15 shows how to sum a differential input signal and a single-ended input signal. Ground noise may couple in through IN- with this method. It is better to use differential inputs. The corner frequency of the single-ended input is set by CI2, shown in equation (8). To assure that each input is balanced, the single-ended input must be driven by a low-impedance source even if the input is not in use. Gain1 Summing Input Signals Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain. The IS31AP2005 makes it easy to sum signals or use separate signal sources with different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker. Summing Two Differential Input Signals Two extra resistors are needed for summing differential signals. The gain for each input source can be set independently (see equations (4) and (5), and Figure 14). VO 2 150 k V RI1 VI 1 V V 2 150 k V Gain 2 O RI 2 VI 2 V If summing left and right inputs with a gain of 1V/V, use RI1 = RI2 = 300kΩ. If summing a ring tone and a phone signal, set the ring-tone gain to Gain2 = 2V/V, and the phone gain to Gain1 = 0.1V/V. The resistor values would be. (3) If the corner frequency is within the audio band, the capacitors should have a tolerance of 10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. Gain1 Figure 14 Application Schematic with IS31AP2005 Summing Two Differential Inputs (4) (5) Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 VO 2 150 k V RI 1 VI1 V (6) VO 2 150 k V (7) RI 2 VI 2 V 1 (8) CI 2 2R I 2 f c 2 Gain 2 If summing a ring tone and phone signals, the phone signals should use the differential inputs while the ring tone should use the single-ended input. The phone gain is set at Gain1 = 0.1V/V, and the ring-tone gain is set to Gain2 = 2V/V, the resistor values would be RI1 = 3MΩ, and RI2 = 150kΩ The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less than 20Hz. CI2 1 2 150 k 20 Hz C I 2 53 pF (9) (10) 10 IS31AP2005 C I1 CI 2 1 2RI 1 f c1 1 2RI 2 f c 2 Cp C I 1 C I 2 Rp RI 1 RI 2 R 1 R I 2 (13) (14) (15) (16) Figure 15 Application Schematic with IS31AP2005 Summing Differential Input and Single-Ended Input Signals Summing Two Single-Ended Input Signals The gain and corner frequencies (fC1 and fC2) for each input source can be set independently (see equations (11) through (14), and Figure 16). Resistor, RP, and capacitor, CP, are needed on the IN- terminal to match the impedance on the IN+ terminal. The single-ended inputs must be driven by low impedance sources. V V Gain1 VO 2 150 k RI1 VI 1 Gain 2 VO 2 150 k V RI 2 VI 2 V (11) Figure 16 Application Schematic with IS31AP2005 Summing Two Single-Ended Inputs (12) Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 11 IS31AP2005 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 17 Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 12 IS31AP2005 TAPE AND REEL INFORMATION DFN-8 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 13 IS31AP2005 MSOP-8 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 14 IS31AP2005 PACKAGING INFORMATION DFN-8 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 15 IS31AP2005 MSOP-8 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 07/06/2011 16