ISSI IS41C16257C

IS41C16257C
IS41LV16257C
256Kx16
4Mb DRAM WITH FAST PAGE MODE
FEATURES
•
•
•
•
•
•
•
•
•
Fast access and cycle time
TTL compatible inputs and outputs
Refresh Interval: 512 cycles/8 ms
Refresh Mode: RAS-Only, CAS-before-RAS
(CBR), and Hidden
JEDEC standard pinout
Single power supply:
5V ± 10% (IS41C16257C)
3.3V ± 10% (IS41LV16257C)
Byte Write and Byte Read operation via
two CAS
Lead-free available
Industrial temperature available
ADVANCED INFORMATION
APRIL 2010
DESCRIPTION
The ISSI IS41C16257C/IS41LV16257C is 262,144 x 16-
bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 512 random accesses
within a single row with access cycle time as short as 12
ns per 16-bit word. The Byte Write control, of upper and
lower byte, makes these devices ideal for use in 16- and
32-bit wide data bus systems.
These features make the IS41C16257C /IS41LV16257C
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C16257C/IS41LV16257C are packaged in a 40pin, 400-mil SOJ and TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
-35
-60
Unit
Max. RAS Access Time (trac)
Max. CAS Access Time (tcac)
Max. Column Address Access Time (taa)
Min. Fast Page Mode Cycle Time (tpc)
35
11
18
14
60
15
30
25
ns
ns
ns
ns
Min. Read/Write Cycle Time (trc)
60
110
ns
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
1
IS41C16257C
IS41LV16257C
PIN CONFIGURATIONS
40-Pin SOJ
40-Pin TSOP (Type II)
VDD
1
40
GND
VDD
1
40
GND
I/O0
2
39
I/O15
I/O0
2
39
I/O15
I/O1
3
38
I/O14
I/O2
4
37
I/O13
I/O1
3
38
I/O14
I/O3
5
36
I/O12
I/O2
4
37
I/O13
VDD
6
35
GND
I/O3
5
36
I/O12
I/O4
7
34
I/O11
VDD
6
35
GND
I/O5
8
33
I/O10
I/O4
7
34
I/O11
I/O6
9
32
I/O9
I/O5
8
33
I/O10
I/O7
10
31
I/O8
I/O6
9
32
I/O9
I/O7
10
31
I/O8
NC
11
30
NC
NC
12
29
LCAS
NC
11
30
NC
NC
12
29
LCAS
WE
13
28
UCAS
RAS
14
27
NC
15
A0
16
A1
WE
13
28
UCAS
OE
RAS
14
27
OE
26
A8
NC
15
26
A8
25
A7
A0
16
25
A7
17
24
A6
A1
17
24
A6
A2
18
23
A5
A3
19
22
A4
A2
18
23
A5
VDD
20
21
GND
A3
19
22
A4
VDD
20
21
GND
PIN DESCRIPTIONS
A0-A8 I/O0-I/O15
WE OE RAS UCAS LCAS Vdd
GND
NC
2
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
DATAI/OBUS
COLUMNDECODERS
SENSEAMPLIFIERS
A0-A8
ADDRESS
BUFFERS
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
ROWDECODER
REFRESH
COUNTER
MEMORYARRAY
262,144x16
DATAI/OBUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
I/O0-I/O15
3
IS41C16257C
IS41LV16257C
TRUTH TABLE
Function
RAS
LCAS UCAS WE
OE Address tr/tc
Standby
H
H
H
X
X
X
Read: Word
L
L
L
H
L
ROW/COL
Read: Lower Byte
L
L
H
H
L
ROW/COL
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Read-Write(1,2)
L
L
L
H → L L → H ROW/COL
Hidden Refresh2)
Read L → H → L L
L
H
L
ROW/COL
Write L → H → L L
L
L
X
ROW/COL
RAS-Only Refresh
L
H
H
X
X
ROW/NA
(3)
CBR Refresh H → L
L
L
X
X
X
I/O
High-Z
Dout
Lower Byte, Dout
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, Dout
Din
Lower Byte, Din
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, Din
Dout, Din
Dout
Dout
High-Z
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
4
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
Functional Description
The IS41C16257C/IS41LV16257C is a CMOS DRAM
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched
by the Row Address Strobe (RAS). The column address
is latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used to latch
the latter nine bits.
The IS41C16257C/IS41LV16257C has two CAS controls,
LCAS and UCAS. The LCAS and UCAS inputs internally
generate a CAS signal functioning in an identical manner to
the single CAS input on the other 256K x 16 DRAMs. The
key difference is that each CAS controls its corresponding
I/O tristate logic (in conjunction with OE and WE and RAS).
LCAS controls I/O0 - I/O7 and UCAS controls I/O8 - I/
O15.
The IS41C16257C/IS41LV16257C CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16257C/IS41LV16257C both BYTE
READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is
terminated by returning both RAS and CAS HIGH.To ensure
proper device operation and data integrity any memory
cycle, once initiated, must not be ended or aborted before
the minimum tras time has expired. A new cycle must not
be initiated until the minimum precharge time trp, tcp has
elapsed.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid at
or before the falling edge of CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses and
the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Power-On
After application of the Vdd supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing
a RAS signal).
During power-on, it is recommended that RAS track with
Vdd or be held at a valid Vih to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tar.
Data Out becomes valid only when trac, taa, tcac and toea
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
5
IS41C16257C
IS41LV16257C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vt
Vdd
Iout
Pd
Ta
Tstg
Parameters
Voltage on Any Pin Relative to GND
5V
3.3V
Supply Voltage
5V
3.3V
Output Current
Power Dissipation
Operation Temperature
Com.
Ind.
Storage Temperature
Rating
–1.0 to +7.0
–0.5 to +4.6
–1.0 to +7.0
–0.5 to +4.6
50
1
0 to +70
-40 to +85
–55 to +125
Unit
V
V
V
V
mA
W
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)
Symbol Parameter
Vdd
Supply Voltage
Vih
Input High Voltage
Vil
Input Low Voltage
Iil
Input Leakage Current
Iio
Output Leakage Current
Voh
Output High Voltage Level
Vol
Output Low Voltage Level
Ambient Temperature
Ta
Test Condition
Voltage Min. Typ.
Max.
5V
4.5
5.0
5.5
3.3V
3.0
3.3
3.6
5V
2.0
— Vdd + 1.0
3.3V
2.0
— Vdd + 0.3
5V/3.3V –0.3
—
0.8
Any input 0V < Vin < Vdd
–5
5
Other inputs not under test = 0V
Output is disabled (Hi-Z)
–5
5
0V < Vout < Vdd
Ioh = –5.0 mA
5V
2.4
—
Ioh = –2.0 mA
3.3V
2.4
—
Iol = +4.2 mA
5V
—
0.4
Iol = +2 mA
3.3V
—
0.4
Com.
0
—
+70
Ind.
-40
—
+85
Unit
V
V
V
V
V
µA
µA
V
V
°C
CAPACITANCE(1,2)
Symbol
Cin1
Cin2
Cio
Parameter
Input Capacitance: A0-A8
Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd=3.3V ± 10%.
6
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol
Idd1 Idd2 Idd3 Idd4 Idd5 Idd6 Parameter
Test ConditionVdd/Speed
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ Vih
Com.
5V
3.3V
Ind.
5V
3.3V
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ Vdd – 0.2V 5V
3.3V
Operating Current: RAS, LCAS, UCAS,
-35
Random Read/Write(2,3,4)
Address Cycling, trc = trc (min.)
-60
Average Power Supply Current
Operating Current: RAS = Vil, LCAS, UCAS,
-35
Fast Page Mode(2,3,4)
Cycling tpc = tpc (min.)
-60
Average Power Supply Current
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ Vih RAS-Only(2,3)
trc = trc (min.)
Average Power Supply Current
Refresh Current: RAS, LCAS, UCAS Cycling
CBR(2,3,5)
trc = trc (min.)
Average Power Supply Current
Min.
—
—
—
—
—
—
—
—
Max.
4
4
5
5
1
1
230
170
Unit
mA
—
—
220
160
mA
-35
-60
—
—
230
170
mA
-35
-60
—
­—
230
170
mA
mA
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
7
IS41C16257C
IS41LV16257C
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
-35 -60
Symbol Parameter
Min. Max.
Min. Max.Units
trc
Random READ or WRITE Cycle Time
70 —
110 —
ns
(6, 7)
trac
Access Time from RAS — 35
— 60
ns
tcac
Access Time from CAS(6, 8, 15)
— 11
— 15
ns
(6)
taa
Access Time from Column-Address — 18
— 30
ns
tras
RAS Pulse Width
35 10K
60 10K
ns
trp
RAS Precharge Time
25 —
40 —
ns
tcas
CAS Pulse Width(26)
6 10K
10 10K
ns
tcp
CAS Precharge Time(9, 25)
6 —
10 —
ns
tcsh
CAS Hold Time (21)
35 —
60 —
ns
(10, 20)
trcd
RAS to CAS Delay Time
13 24
20 45
ns
tasr
Row-Address Setup Time
0 —
0 —
ns
trah
Row-Address Hold Time
6
—
10 —
ns
tasc
Column-Address Setup Time(20)
0
—
0
—
ns
(20)
tcah
Column-Address Hold Time 6
—
10 —
ns
tar
Column-Address Hold Time
30 —
45 —
ns
(referenced to RAS)
trad
RAS to Column-Address Delay Time(11)
12 20
15 30
ns
tral
Column-Address to RAS Lead Time
18 —
30 —
ns
trpc
RAS to CAS Precharge Time
0
—
0
—
ns
trsh
RAS Hold Time(27)
10 —
15 —
ns
(15, 29)
tclz
CAS to Output in Low-Z
3
—
3
—
ns
tcrp
CAS to RAS Precharge Time(21)
5
—
5
—
ns
(19, 28, 29)
tod
Output Disable Time
3
15
3
15
ns
toe
Output Enable Time(15, 16)
— 11
— 15
ns
toehc
OE HIGH Hold Time from CAS HIGH
8
—
8
—
ns
toep
OE HIGH Pulse Width
8
—
8
—
ns
toes
OE LOW to CAS HIGH Setup Time
5
—
7
—
ns
trcs
Read Command Setup Time(17, 20)
0
—
0
—
ns
trrh
Read Command Hold Time
0
—
0
—
ns
(referenced to RAS)(12)
trch
Read Command Hold Time
0
—
0
—
ns
(referenced to CAS)(12, 17, 21)
twch
Write Command Hold Time(17, 27)
5
—
10 —
ns
twcr
Write Command Hold Time
30 —
50 —
ns
(referenced to RAS)(17)
twp
Write Command Pulse Width(17)
5
—
10 —
ns
twpz
WE Pulse Widths to Disable Outputs
10 —
10 —
ns
trwl
Write Command to RAS Lead Time(17)
10 —
15 —
ns
tcwl
Write Command to CAS Lead Time(17, 21)
8
—
15 —
ns
twcs
Write Command Setup Time(14, 17, 20)
0
—
0
—
ns
tdhr
Data-in Hold Time (referenced to RAS)
30 —
46 —
ns
8
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
-35
-60
Symbol Parameter
Min.
Max.
Min. Max.
tach
Column-Address Setup Time to CAS
15
— 15
—
Precharge during WRITE Cycle
toeh
OE Hold Time from WE during
8
— 15
—
READ-MODIFY-WRITE cycle(18)
tds
Data-In Setup Time(15, 22)
0
— 0
—
(15, 22)
tdh
Data-In Hold Time
6
— 10
—
trwc
READ-MODIFY-WRITE Cycle Time
80
— 140
—
trwd
RAS to WE Delay Time during
46
— 80
—
READ-MODIFY-WRITE Cycle(14)
tcwd
CAS to WE Delay Time(14, 20)
25
— 36
—
(14)
tawd
Column-Address to WE Delay Time 30
— 49
—
tpc
Fast Page Mode READ or WRITE
14
— 25
—
Cycle Time(24)
trasp
RAS Pulse Width
35
100K
60
100K
tcpa
Access Time from CAS Precharge(15)
—
20 —
35
(24)
tprwc
READ-WRITE Cycle Time 45
— 60
—
toff
Output Buffer Turn-Off Delay from
3
10 3
15
CAS or RAS(13,15,19, 29)
twhz
Output Disable Delay from WE
3
10 3
15
tclch
Last CAS going LOW to First CAS
10
— 10
—
returning HIGH(23)
tcsr
CAS Setup Time (CBR REFRESH)(30, 20)
8
— 10
—
tchr
CAS Hold Time (CBR REFRESH)(30, 21)
8
— 10
—
tord
OE Setup Time prior to RAS during
0
— 0
—
HIDDEN REFRESH Cycle
tref
Refresh Period (512 Cycles)
—
8 —
8
(2, 3)
tt
Transition Time (Rise or Fall) 2
50 2
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vdd = 5.0V ±10%)
One TTL Load and 50 pF (Vdd = 3.3V ±10%)
Input timing reference levels: Vih = 2.0V, Vil = 0.8V (Vdd = 5.0V ±10%);
Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%)
Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%)
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
9
IS41C16257C
IS41LV16257C
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2. Vih (MIN) and Vil (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between Vih
and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih)
in a monotonic manner.
4. If CAS and RAS = Vih, data output is High-Z.
5. If CAS = Vil, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that trcd < trcd (MAX). If trcd is greater than the maximum recommended value shown in this table, trac will increase
by the amount that trcd exceeds the value shown.
8. Assumes that trcd ≥ trcd (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tcp.
10.Operation with the trcd (MAX) limit ensures that trac (MAX) can be met. trcd (MAX) is specified as a reference point only; if trcd
is greater than the specified trcd (MAX) limit, access time is controlled exclusively by tcac.
11.Operation within the trad (MAX) limit ensures that trcd (MAX) can be met. trad (MAX) is specified as a reference point only; if trad
is greater than the specified trad (MAX) limit, access time is controlled exclusively by taa.
12.Either trch or trrh must be satisfied for a READ cycle.
13.toff (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol.
14.twcs, trwd, tawd and tcwd are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs ≥
twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If trwd ≥
trwd (MIN), tawd ≥ tawd (MIN) and tcwd ≥ tcwd (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to Vih) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled)
cycle.
15.Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17.Write command is defined as WE going low.
18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tod and toeh met (OE HIGH during WRITE cycle) in order to
ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains
LOW and OE is taken back to LOW after toeh is met.
19.The I/Os are in open during READ cycles once tod or toff occur.
20.The first χCAS edge to transition LOW.
21.The last χCAS edge to transition HIGH.
22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23.Last falling χCAS edge to first rising χCAS edge.
24.Last rising χCAS edge to next cycle’s last rising χCAS edge.
25.Last rising χCAS edge to first falling χCAS edge.
26.Each χCAS must meet minimum pulse width.
27.Last χCAS to go LOW.
28.I/Os controlled, regardless UCAS and LCAS.
29.The 3 ns minimum is a parameter guaranteed by design.
30.Enables on-chip refresh and address counters.
10
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
FAST-PAGE-MODE READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
ValidData
tOE
tOD
OE
tOES
Don't Care
Note:
1. toff is referenced from rising edge of CAS.
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
11
IS41C16257C
IS41LV16257C
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
tRASP
tRP
RAS
tPRWC
tCAS
tCSH
tCRP
tCAS
tRCD
tRSH
tCAS
tCP
tCRP
tCP
UCAS/LCAS
tAR
tRAH
tRAD
tASC
tASR
ADDRESS
tCPWD
tRAL
tCAH
tCPWD
Row
tCAH
tAR
Column
tASC
Column
tCWL
tRWD
tAWD
tCWD
tRCS
tCAH
tASC
Column
tCWL
tRWL
tCWL
tAWD
tCWD
tWP
tAWD
tCWD
tWP
tWP
WE
tAA
tAA
tCAC
tCAC
tOEA
OE
tCAC
tOEA
tOEZ
tOED
tRAC
OUT
IN
tOEA
tOEZ
tOED
tDH
tDS tCLZ
tCLZ
I/O0-I/O15
tAA
tDS
OUT
IN
tDH
tOEZ
tOED
tCLZ
OUT
tDS
tDH
IN
Don't Care
12
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
ValidData
Don't Care
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
13
IS41C16257C
IS41LV16257C
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
tRAH
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tRCS
tAWD
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
ValidDOUT
tOE
tOD
tDH
ValidDIN
Open
tOEH
OE
Don't Care
14
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
FAST PAGE MODE EARLY WRITE CYCLE
tRASP
tRP
RAS
tCRP
tCAS
tRCD
tRHCP
tRSH
tCAS
tPC
tCAS
tCSH
tCP
tCP
tCRP
UCAS/LCAS
tAR
tRAH
tRAD
tASC
tASR
ADDRESS
Row
tCAH
tASC
tAR
Column
tWCH
tASC
Column
tCWL
tWCS
tRAL
tCAH
Column
tCWL
tCWL
tWCH tWCS
tWCS
tWP
tCAH
tWP
tWCH
tWP
WE
tWCR
OE
tDHR
tDS
I/O0-I/O15
tDH
ValidDIN
tDS
tDH
ValidDIN
tDS
tDH
ValidDIN
Don't Care
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
15
IS41C16257C
IS41LV16257C
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tRAC
tCAC
tCLZ
Open
I/O
tWHZ
tCLZ
ValidData
Open
tOE
tOD
OE
Don't Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS/LCAS
tASR
ADDRESS
I/O
tRAH
Row
Row
Open
Don't Care
16
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tCHR
tRPC
tCP
tCHR
tRPC
tCSR
tCSR
UCAS/LCAS
Open
I/O
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tASR
tRAD
tRAH tASC
tRSH
tCHR
UCAS/LCAS
tAR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
ValidData
Open
tOE
tOD
tORD
OE
Don't Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
17
IS41C16257C
IS41LV16257C
ORDERING INFORMATION: 5V
Industrial Range: -40oC to +85oC
peed (ns)
S
35
Order Part No.
IS41C16257C-35KLI
IS41C16257C-35TLI
Package
400-mil SOJ, Lead-free 400-mil TSOP (Type II), Lead-free
ORDERING INFORMATION: 3.3V
Industrial Range: -40oC to +85oC
peed (ns)
S
35
Order Part No.
Package
IS41LV16257C-35KLI 400-mil SOJ, Lead-free IS41LV16257C-35TLI 400-mil TSOP (Type II), Lead-free
Note:
1. The -35 speed option supports 35ns and 60ns timing specifications.
2. Contact ISSI for leaded package availability.
18
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010
IS41C16257C
IS41LV16257C
Integrated Silicon Solution, Inc.
Rev. 00A
04/092010
19
IS41C16257C
IS41LV16257C
20
Integrated Silicon Solution, Inc.
Rev. 00A
04/09/2010