IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES 512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. HSTL input and output interface. Registered addresses, write and read controls, byte writes, data in, and data outputs. Full data coherency. Boundary scan using limited set of JTAG 1149.1 functions. Byte write capability. Fine ball grid array (FBGA) package: 13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor. Data Valid Pin (QVLD). ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options. IS61DDPB251236A : Don’t care ODT function and pin connection IS61DDPB251236A1 : Option1 IS61DDPB251236A2 : Option2 Refer to more detail description at page 6 for each ODT option. ADVANCED INFORMATION JULY 2012 DESCRIPTION The 18Mb IS61DDPB251236A/A1/A2 and IS61DDPB21M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: Read/write address Read enable Write enable Byte writes Data-in for first burst addresses Data-Out for second burst addresses The following are registered on the rising edge of the K# clock: Byte writes Data-in for second burst addresses Data-Out for first burst addresses Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the third rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second burst are updated with the fourth rising edge of the K clock where read command receives at the first rising edge of K. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 1 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Package ballout and description x36 FBGA Ball Configuration (Top View) A 1 CQ# 2 NC/SA1 3 NC/SA1 4 R/W# 5 BW2# 6 K# 7 BW1# B NC DQ27 C NC NC D NC DQ29 E NC NC F NC G NC H Doff# VREF NC 8 LD# 9 SA DQ18 SA DQ28 VSS BW3# K SA NC DQ19 DQ20 VSS VSS VSS VDDQ VSS VSS DQ30 DQ21 DQ31 DQ22 VDDQ VDD VDDQ VDD VDDQ VDDQ DQ32 VDDQ 10 NC/SA1 11 CQ BW0# SA NC NC DQ8 SA VSS NC DQ17 DQ7 VSS VSS NC NC DQ16 VSS VDDQ NC DQ15 DQ6 VSS VDD VDDQ NC NC DQ5 VSS VDD VDDQ NC NC DQ14 VDD VSS VDD VDDQ VDDQ VREF ZQ VDD VSS VDD VDDQ NC DQ13 DQ4 J NC K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N P R NC NC TDO DQ35 NC TCK DQ25 DQ26 SA VSS SA SA SA SA SA SA QVLD ODT SA SA SA VSS SA SA NC NC SA NC DQ9 TMS DQ10 DQ0 TDI Notes: 1. The following balls are reserved for higher densities: 3A for 36Mb, 10A for 72Mb, and 2A for 144Mb. x18 FBGA Ball Configuration (Top View) Notes: 1. A 1 CQ# 2 1 NC/SA 3 SA 4 R/W# 5 BW1# B NC DQ9 NC SA NC/SA C NC NC NC VSS SA D NC NC DQ10 VSS VSS E NC NC DQ11 VDDQ VSS 1 6 K# 7 NC/SA1 8 LD# 9 SA 10 NC/SA1 11 CQ K BW0# SA NC NC DQ8 NC SA VSS NC DQ7 NC VSS VSS VSS NC NC NC VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff# VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N P R NC NC TDO NC NC TCK DQ16 DQ17 SA VSS SA SA SA SA SA SA QVLD ODT SA SA SA VSS SA SA NC NC SA NC NC TMS NC DQ0 TDI The following balls are reserved for higher densities: 10A for 36Mb, 2A for 72Mb, 7A for 144Mb, and 5B for 288Mb. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 2 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Ball Descriptions Symbol Type K, K# Input CQ, CQ# Output Doff# Input QVLD Output SA Input DQ0 - DQn Bidir R/W# Input LD# Input BWx# Input Description Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running clocks and do not stop when Q tri-states. DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz. Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ#. Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. These inputs are ignored when device is deselected. Data input and output signals. Input data must meet setup and hold times around the rising edges of K and K# during WRITE operations. These pins drive out the requested data when the read operation is active. Valid output data is synchronized to the respective CQ and CQ#. See BALL CONFIGURATION figures for ball site location of individual signals. The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin. The x36 device uses DQ0~DQ35. Synchronous Read or Write input. When LD# is low, this input designates the access type (read when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times around edge of K. Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition includes address and read/write direction. Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and #K for each of the two rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship. HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. VDD Input reference Power VDDQ Power Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. VSS Ground Ground of the device ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. TMS, TDI, TCK Input IEEE 1149.1 input pins for JTAG TDO Output IEEE 1149.1 output pins for JTAG NC N/A No connect: These signals should be left floating or connected to ground to improve package heat dissipation. ODT Input ODT control; Refer to SRAM features for the details. VREF Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 3 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 SRAM Features description Block Diagram 36(18) Data Register Burst2 36x2(18x2) R/W# BWx# 4 (2) Control Logic 512K x 36 (1M x 18) Memory Array 36x2 (18x2) Output Reg 72 (36) 36 (18) Input/Output Driver LD# 18 (19) Sense Amplifiers Add Reg & Burst Control Address Decoder Addresses 18 (19) Output Select 36x2 (18x2) Write Driver 36 (18) DQ(Data-out &Data-In) CQ, CQ# (Echo Clocks) K K# Clock Generator Select Output Control /Doff Note: Numerical values in parentheses refer to the x18 device configuration. Read Operations The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R/W# in active high state at the rising edge of the K clock. K and K#, are also used to control the timing to the outputs. The data corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The data corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock. A set of freerunning echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device. Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high) does not terminate the previous read. The output drivers disable automatically to a high-Z state. Write Operations Write operations can also be initiated at every other rising edge of the K clock whenever R/W# is low. The write address is also registered at that time. When the address needs to change, LD# needs to be low simultaneously to be registered by the rising edge of K. Again, the write always occurs in bursts of two. Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new data-in is presented at the DQ bus. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 4 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of K#. The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array on the third write cycle. A read cycle to the last two write address produces data from the write buffers. Similarly, a read address followed by the same write address produces the latest write data. The SRAM maintains data coherency. During a write, the byte writes independently control which byte of any of the two burst addresses is written. (See X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table) Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory. RQ Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF. The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be connected to VSS. Programmable Impedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances values. The final impedance value is achieved within 1024clock cycles. Valid Data Indicator (QVLD) A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle before the final valid read data arrives. Delay Locked Loop (DLL) Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match the clock frequency. Therefore device can have stable output over the temperature and voltage variation. DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or old QUAD mode. The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K# for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being reset, it gets locked after 2048 cycles of stable clock. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 5 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a SRAM to turn on/off termination resistance for ODT pins. The ODT feature is designed to improve signal integrity of the memory channel by allowing the SRAM controller to turn on/off termination resistance independently for any or all SRAM devices. ODT can have three status, High, Low, and Floating. Each status can have different ODT termination values which tracks the value of RQ (See the picture below) In DDR-IIP devices having common I/O bus, ODT is automatically enabled at the write operation of SRAM and disabled at the read operation of SRAM. Fig1. Functional representation of ODT SRAM In/Out Buffer VDDQ VDDQ VDDQ ODT=L ODT=H R1x2 R2x2 ODT=Floating R3x2 PAD R1x2 R2x2 ODT=L ODT=H VSS Option13 Option24 VSS R1 0.3x RQ1 ODT disable R3x2 ODT=Floating VSS R2 0.6x RQ2 0.6x RQ2 R3 0.6x RQ2 ODT disable Notes 1. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175Ω<RQ<350Ω. 2. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175Ω<RQ<250Ω. 3. ODT control pin is connected to VDDQ through 3.5kΩ. Therefore it is recommended to connect it to VSS through less than 100Ω to make it low. 4. ODT control pin is connected to VSS through 3.5kΩ. Therefore it is recommended to connect it to VDDQ through less than 100Ω to make it high. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 6 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 ODT PINS 1) ODT Pin in option1 . ODT values of K, K#, DQs, and Wx# are controlled by ODT pin. . ODT for DQs will be on and off depending on the status. Read command will turn ODT off as the following rule. Off: First Read Command + Read Latency - 0.5 cycle On: Last Read Command + Read Latency + BL/2 cycle + 0.5 cycle (See below timing chart) Example1) BL=2, RL(Read Latency=2.5) K K# Command RD a DQ(DDRIIP) RD b RD c Read Latency=2.5 RD d WT e Qa Qa Qb Qb Qc Qc Qd Qd RL-0.5 DQ ODT RL Enable BL/2 WT f WT g De De Df WT h RD i RD j Read Latency=2.5 Df Dg Dg Dh Dh Q Q 0.5 Disable Enable Disable Example2) BL=4, RL(Read Latency=2.5) K K# Command RD a DQ(DDRIIP) RD c Read Latency=2.5 WT e Qa Qa Qa Qa Qc Qc Qc Qc RL-0.5 DQ ODT RL Enable BL/2 WT g RD i De De De De Dg Dg Dg Dg Read Latency=2.5 Q Q 0.5 Disable Enable Disable Example3) BL=2, RL(Read Latency=2.0) K K# Command DQ(DDRIIP) RD a RD b Read Latency=2.0 RL-0.5 DQ ODT Enable RD c RD d WT e Qa Qa Qb Qb Qc Qc Qd Qd RL BL/2 Disable WT f WT g De De Df WT h RD i RD j Read Df Dg Dg Dh Dh Latency=2.0 Q Q Q 0.5 Enable Disable 2) ODT Pin in option2 -. Same ODT pin rule of option1 applies except K and K#. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 7 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Power-Up and Power-Down Sequences The recommendation of voltage apply sequence is : VDD → VDDQ 1)→VREF2)→ VIN Notes: VDDQ can be applied concurrently with VDD. VREF can be applied concurrently with VDDQ. After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKClock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be skipped. The following timing pictures are possible examples of power up sequence. Sequence1. /Doff is fixed low After tKC-lock cycle of stable clock, device is ready for normal operation. Power On stage Unstable Clock Period Stable Clock period Read to use K K# VDD >tKC-lock for device initialization VDDQ VREF VIN Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases. Sequence2. /Doff is controlled and goes high after clock being stable. Power On stage Unstable Clock Period Stable Clock period Read to use K K# Doff# >tKC-lock for device initialization VDD VDDQ VREF VIN Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 8 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Sequence3. /Doff is controlled but goes high before clock being stable. Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input. a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKCLock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that. Power On stage Unstable Clock Period K-Stop Stable Clock period Read to use K K# Doff# >30nS >tKC-lock for device initialization VDD VDDQ VREF VIN Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases. a) /Doff Low to reset. If /Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that. Power On stage Unstable Clock Period Doff reset DLL Stable Clock period Read to use K K# Doff# >tDoffLowToReset >tKC-lock for device initialization VDD VDDQ VREF VIN Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off. Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 9 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Application Example The following figure depicts an implementation of four 4M x 18 DDR-IIP SRAMs with common I/Os. Vt R Address SA Read&Write Control R/W# New Address Control LD# BWx# SRAM #1 Byte Write Control K/K# Vt Memory Controller R DQ Data-In&Data Out CQ/CQ# SRAM #1 CQ Input ZQ RQ = 250Ω SRAM #4 CQ Input Source CLK R Vt SA R = 50Ω Vt = V REF R/W# LD# BWx# SRAM #4 K/K# DQ CQ/CQ# ZQ RQ = 250Ω Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 10 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 State Diagram Power-Up /Load NOP Load Load New Read Address /LOAD Read Load DDR-II Read /LOAD Write Load DDR-II Write Notes: 1. Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1. 2. Read refers to read active status with R/W# = High. 3. Write refers to write active status with R/W# = LOW. 4. Load refers to read new address active status with LD# = low. 5. Load is read new address inactive status with LD = high. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 11 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Timing Reference Diagram for Truth Table The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”. Cycle t t+1 t+2 t + 2.5 t+3 t+4 t+5 K# Clock K Clock LD# R/W# BWx# A Address B 2.5 cycles tCHQV DataIn/Out(DQ) QA QA+1 DB DB+1 CQ CQ# Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.) Clock Controls Data Out / Data In Mode K LD# R/W# QA / DB QA+1 / DB+1 Stop Clock Stop X X Previous State Previous State No Operation (NOP) L→H H X High-Z High-Z Read A L→H L H DOUT at K# (t+2.5) ↑ DOUT at K (t+3.0) ↑ Write B L→H L L DB at K (t+5.0) ↑ DB at K# (t+5.5) ↑ Notes: 1. X = “don’t care”; H = logic “1”; L = logic “0”. 2. A read operation is started when control signal R/W# is active high. 3. A write operation is started when control signal R/W# is active low. 4. Before entering into stop clock, all pending read and write commands must be completed. 5. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with respect to switching clocks K and K# Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 12 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 x18 Write Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.) Operation K (t+1.0) Write Byte 0 K (t+1.5) BW0 BW1 DB L→H L H D0-8 (t+4.0) Write Byte 1 L→H H L D9-17 (t+4.0) Write All Bytes L→H L L D0-17 (t+4.0) Abort Write L→H H H Don't Care DB+1 Write Byte 0 L→H L H D0-8 (t+4.5) Write Byte 1 L→H H L D9-17 (t+4.5) Write All Bytes L→H L L D0-17 (t+4.5) Abort Write L→H H H Don't Care Notes: 1. For all cases, R/W# needs to be active low during the rising edge of K occurring at time t. 2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and K#. x36 Write Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.) Operation K (t+1.0) BW0 BW1 BW2 BW3 DB Write Byte 0 L→H K (t+1.5) L H H H D0-8 (t+4.0) Write Byte 1 L→H H L H H D9-17 (t+4.0) Write Byte 2 L→H H H L H D18-26 (t+4.0) Write Byte 3 L→H H H H L D27-35 (t+4.0) Write All Bytes L→H L L L L D0-35 (t+4.0) Abort Write L→H H H H H Don't Care DB+1 Write Byte 0 L→H L H H H D0-8 (t+4.5) Write Byte 1 L→H H L H H D9-17 (t+4.5) Write Byte 2 L→H H H L H D18-26 (t+4.5) Write Byte 3 L→H H H H L D27-35 (t+4.5) Write All Bytes L→H L L L L D0-35 (t+4.5) Abort Write L→H H H H H Don't Care Notes: 1. For all cases, R/W# needs to be active low during the rising edge of K occurring at time t. 2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and K#. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 13 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Min Max Units Power Supply Voltage VDD 0.5 2.9 V I/O Power Supply Voltage VDDQ 0.5 2.9 V DC Input Voltage VIN 0.5 VDD+0.3 V Data Out Voltage VDOUT 0.5 2.6 V Junction Temperature TJ - 110 °C Storage Temperature TSTG 55 +125 °C Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Temperature Range Temperature Range Symbol Min Max Units Commercial TA 0 +70 °C Industrial TA 40 +85 °C DC Electrical Characteristics (Over the Operating Temperature Range, VDD=1.8V±5%) Parameter x36 Average Power Supply Operating Current (IOUT=0, VIN=VIH or VIL ) x18 Average Power Supply Operating Current (IOUT=0, VIN=VIH or VIL ) Power Supply Standby Current (R=VIH, W=VIH. All other inputs=VIH or VIL, IIH=0) Input leakage current ( 0 ≤VIN≤VDDQ for all input balls except VREF, ZQ, TCK, TMS, TDI ball) Output leakage current (0 ≤VOUT ≤VDDQ for all output balls except TDO ball; Output must be disabled.) Output “high” level voltage (IOH=100uA, Nominal ZQ) Output “low” level voltage (IOL= 100uA, Nominal ZQ) Symbol IDD18 IDD20 IDD22 IDD25 IDD18 IDD20 IDD22 IDD25 ISB18 ISB20 ISB22 ISB25 Min Max Units Notes 1100 960 900 800 mA 1,2 mA 1,2 mA 1,2 3,4 1050 910 850 750 380 360 340 320 ILI 2 +2 µA ILO 2 +2 µA VOH VDDQ0.2 VDDQ V VOL VSS VSS+0.2 V Notes: 1. IOUT = chip output current. 2. The numeric suffix indicates the part operating at speed, as indicated in AC Timing Characteristics table (that is, IDD25 indicates 2.5ns cycle time). 3. ODT must be disabled. 4. Balls with ODT and DOFF# do not follow this spec, ILI = ±5uA. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 14 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Recommended DC Operating Conditions (Over the Operating Temperature Range) Parameter Symbol Min Typical Max Units Notes Supply Voltage VDD 1.8–5% 1.8 1.8+5% V 1 Output Driver Supply Voltage VDDQ 1.4 1.5 VDD V 1 Input High Voltage VIH VREF+0.1 - VDDQ+0.2 V 1, 2 Input Low Voltage VIL –0.2 - VREF –0.1 V 1, 3 VREF 0.68 0.75 0.95 V 1, 5 VIN-CLK –0.2 - VDDQ+0.2 V 1, 4 Input Reference Voltage Clock Signal Voltage Notes: 1. All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected. 2. VIH(max) AC = See 0vershoot and Undershoot Timings. 3. VIL(min) AC = See 0vershoot and Undershoot Timings. 4. VIN-CLK specifies the maximum allowable DC excursions of each clock (K and K#). 5. Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF. Overshoot and Undershoot Timings Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 15 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Typical AC Input Characteristics Parameter Symbol Min AC Input Logic HIGH VIH (AC) VREF+0.2 AC Input Logic LOW VIL (AC) Clock Input Logic HIGH VIH-CLK (AC) Clock Input Logic LOW VIL-CLK (AC) Max Units Notes V 1, 2, 3, 4 V 1, 2, 3, 4 V 1, 2, 3 V 1, 2, 3 VREF–0.2 VREF+0.2 VREF–0.2 Notes: 1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. Performance is a function of VIH and VIL levels to clock inputs. 3. See the AC Input Definition diagram. 4. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only. AC Input Definition K# VREF K VRAIL VIH(AC) Setup Time Hold Time VREF VIL(AC) V-RAIL PBGA Thermal Characteristics Parameter Symbol 13x15 BGA 15x17 BGA Units Thermal resistance (junction to ambient at airflow = 1m/s) RθJA 19.6 18.0 °C/W Thermal resistance (junction to pins) RθJB 4.02 3.30 °C/W Thermal resistance (junction to case) RθJC 4.53 4.20 °C/W Note: these parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 16 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Pin Capacitance Parameter Symbol Input or output capacitance except DQ pins CIN ,CO DQ capacitance (DQ0–DQx) CDQ Clocks Capacitance (K, K, C, C) CCLK Test Condition TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Max Units 5 pF 6 pF 4 pF Note: these parameters are guaranteed by design and tested by a sample basis only. Programmable Impedance Output Driver DC Electrical Characteristics (Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V) Parameter Symbol Min Max Units Notes Output Logic HIGH Voltage VOH VDDQ /2 -0.12 VDDQ /2 + 0.12 V 1, 3 Output Logic LOW Voltage VOL VDDQ /2 -0.12 VDDQ /2 + 0.12 V 2, 3 Notes: 1. For 175Ω ≤ RQ ≤ 350Ω: VDDQ 2 | IOH | RQ 5 2. For 175Ω ≤ RQ ≤ 350Ω: VDDQ 2 | IOL | RQ 5 3. Parameter Tested with RQ=250Ω and VDDQ=1.5V AC Test Conditions (Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V) Parameter Symbol Conditions Units VDDQ 1.5/1.8 V Input Logic HIGH Voltage VIH VREF+0.5 V Input Logic LOW Voltage VIL VREF–0.5 V Input Reference Voltage VREF 0.75/0.9 V Input Rise Time TR 2.0 V/ns Input Fall Time TF Output Drive Power Supply Voltage 2.0 V/ns Output Timing Reference Level VREF V Clock Reference Level VREF V Output Load Conditions Notes 1, 2 Notes: 1. See AC Test Loading. 2. Parameter Tested with RQ=250Ω and VDDQ=1.5V Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 17 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 AC Test Loading (a) Unless otherwise noted, AC test loading assume this condition. (b) tCHQZ and tCHQX1 are specified with 5pF load capacitance and measured when transition occurs ±100mV from the steady state voltage. (c)TDO VREF 50Ω Output 50Ω 20pF Test Comparator VREF Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 18 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 AC Timing Characteristics (Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V) Parameter Symbol 18 (550MHz) 20 (500MHz) Min Max Min Max 22 (450MHz) Min Max 25 (400MHz) Min Max Units 1.82 8.40 2.00 8.40 2.2 8.40 2.50 8.40 ns 0.20 ns Notes Clock Clock Cycle Time (K, K#) tKHKH Clock Phase Jitter (K, K#) tKC var 0.15 0.15 0.15 Clock High Time (K, K#) tKHKL 0.4 0.4 0.4 0.4 cycle Clock Low Time (K, K#) tKLKH 0.4 0.4 0.4 0.4 cycle Clock to Clock# (K, K#) tKHK#H 0.82 0.90 0.99 1.13 ns DLL Lock Time (K) tKC lock 2048 2048 2048 2048 cycles Doff Low period to DLL reset K static to DLL reset tDoffLowToReset 5 5 5 5 ns tKCreset 30 30 30 30 ns 4 5 Output Times K, K# High to Output Valid tCHQV K, K# High to Output Hold tCHQX K, K# High to Echo Clock Valid 0.45 -0.45 tCHCQV K, K# High to Echo Clock Hold tCHCQX CQ, CQ# High to Output Valid tCQHQV CQ, CQ# High to Output Hold tCQHQX 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.15 -0.15 0.45 -0.45 0.45 -0.45 0.15 -0.15 0.45 ns ns -0.45 0.2 -0.2 0.45 ns ns 0.2 -0.2 6 ns 6 tCHQZ K, High to Output Low-Z tCHQX1 -0.45 tQVLD -0.15 Address valid to K rising edge tAVKH 0.23 0.25 0.30 0.40 ns R#,W# control inputs valid to K rising edge tIVKH 0.23 0.25 0.30 0.40 ns 2 BWx# control inputs valid to K rising edge tIVKH2 0.18 0.20 0.25 0.28 ns 2 Data-in valid to K, K# rising edge tDVKH 0.18 0.20 0.25 0.28 ns K rising edge to address hold tKHAX 0.23 0.25 0.30 0.40 ns 2 K rising edge to R#,W# control inputs hold tKHIX 0.23 0.25 0.30 0.40 ns 2 K rising edge to BWx# control inputs hold tKHIX2 0.18 0.20 0.25 0.28 ns K, K# rising edge to data-in hold tKHDX 0.18 0.20 0.25 0.28 ns -0.45 0.15 -0.15 0.45 ns K, High to Output High-Z CQ, CQ# High to QVLD Valid 0.45 0.45 -0.45 -0.45 0.15 -0.20 0.45 ns 0.20 ns -0.45 0.20 -0.20 ns Setup Times Hold Times Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. 5. The data sheet parameters reflect tester guard bands and test setup variations. 6. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 19 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Read, Write, and NOP Timing Diagram Notes: 1. Q1-0 refers to the output from address A1. Q1-1 refers to the output from the next burst address following A1. 2. The NOP cycle is not necessary for correct device operation, however, at high clock frequencies, it might be required to prevent bus contention. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 20 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 IEEE 1149.1 Serial Boundary Scan of JTAG These SRAMs incorporate a serial boundary scan Test Access Port (TAP) controller in 165 FBGA package. That is fully compliant with IEEE Standard 1149.1-2001. The TAP controller operates using standard 1.8 V interface logic levels. Disabling the JTAG feature These SRAMs operate without using the JTAG feature. To disable the TAP controller, TCK must be tied Low (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port Signal List: Test Clock (TCK) The test clock is to operate only TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is to set commands of the TAP controller and is sampled on the rising edge of TCK. This pin can be left unconnected at SRAM operation. The pin is pulled up internally to keep logic high level. Test Data-In (TDI) The TDI pin is to receive serially input information into the instruction and data registers. It can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register (Refer to the TAP Controller State Diagram). TDI is internally pulled up and can be unconnected at SRAM. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO pin is to drive serially clock data out from the JTAG registers. The output is active, depending upon the current state of the TAP state machine (Refer to instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 21 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 TAP Controller State and Block Diagram TAP Controller State Machine 1 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 1 0 0 1 1 Capture DR 0 Capture IR 0 0 Shift DR 1 1 1 1 Exit1 DR Exit1 IR 0 0 0 Pause DR 0 Pause IR 1 1 Exit2 DR 0 Exit2 IR 1 0 1 Update DR 1 0 Shift IR Update IR 0 Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 1 0 22 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register This register is loaded during the update-IR state of the TAP controller. Three-bit instructions can be serially loaded into the instruction register. At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register The bypass register is a single-bit register that can be placed between the TDI and TDO balls. It is to skip certain chips without serial boundary scan. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output balls on the SRAM. Several No Connected(NC) balls are also included in the scan register to reserve other product options. The boundary scan register is loaded with the contents of the SRAM input and output ring when the TAP controller is in the capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. Each bit corresponds to one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the shift-DR state. The ID register has a vendor ID code and other information TAP Instruction Set TAP Instruction Set is available to set eight instructions with the three bit instruction register and all combinations are listed in the TAP Instruction Code Table. Three of listed instructions on this table are reserved and must not be used. Instructions are loaded serially into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon powerup or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 23 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 SAMPLE/PRELOAD SAMPLE/PRELOAD is a IEEE 1149.1 basic instruction which connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state.. A snapshot of data on the inputs and output balls is captured in the boundary scan register when the TAP controller is in a Shift-DR state. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition. This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time. The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the shiftDR state. This places the boundary scan register between the TDI and TDO balls. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. PRIVATE Do not use these instructions. They are reserved for future use and engineering mode. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #109. When this scan cell, called the “EXTEST output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Qbus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. JTAG DC Operating Characteristics (Over the Operating Temperature Range, VDD=1.8V±5%) Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Output High Voltage JTAG Output Low Voltage JTAG Output High Voltage JTAG Output Low Voltage JTAG Input Leakage Current JTAG Output Leakage Current Symbol VIH1 VIL1 VOH1 VOL1 VOH2 VOL2 ILIJTAG ILOJTAG Min 1.3 –0.3 1.4 1.6 -100 -5 Max VDD+0.3 0.5 0.4 0.2 +100 +5 Units V V V V V V uA uA Notes |IOH1|=2mA IOL1=2mA |IOH2|=100uA IOL2=100uA 0 ≤ Vin ≤ VDD 0 ≤ Vout ≤ VDD Notes: 1. All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible. Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 24 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 JTAG AC Test Conditions (Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V) Parameter Input Pulse High Level Input Pulse Low Level Input Rise Time Input Fall Time Input and Output Timing Reference Level Symbol VIH1 VIL1 TR1 TF1 Conditions 1.3 0.5 1.0 1.0 0.9 Units V V ns ns V JTAG AC Characteristics (Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V) Parameter TCK cycle time TCK high pulse width TCK low pulse width TMS Setup TMS Hold TDI Setup TDI Hold Capture Setup Capture Hold TCK Low to Valid Data* TCK Low to Invalid Data* Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCVTH tTHCX tTLOV tTLQX Min 50 20 20 5 5 5 5 5 5 – 0 Max – – – – – – – – – 10 – Units ns ns ns ns ns ns ns ns ns ns ns Note: See AC Test Loading(c) JTAG Timing Diagram Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 25 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Instruction Set Code Instruction TDO Output 000 EXTEST Boundary Scan Register 001 IDCODE 32-bit Identification Register 010 SAMPLE-Z Boundary Scan Register 011 PRIVATE Do Not Use 100 SAMPLE(/PRELOAD) Boundary Scan Register 101 PRIVATE Do Not Use 110 PRIVATE Do Not Use 111 BYPASS Bypass Register ID Register Definition Revision Number (31:29) Part Configuration (28:12) Vendor ID Code (11:1) Start Bit (0) 000 0TDEF0WX01PQLBTS0 00011010101 1 Part Configuration Definition: 1. DEF = 001 for 18Mb, 010 for 36Mb, 011 for 72Mb 2. WX = 11 for x36, 10 for x18 3. P = 1 for II+(QUAD-P/DDR-IIP), 0 for II(QUAD/DDR-II) 4. Q = 1 for QUAD, 0 for DDR-II 5. L = 1 for RL=2.5, 0 for RL≠2.5 6. B = 1 for burst of 4, 0 for burst of 2 7. S = 1 for Separate I/O, 0 for Common I/O 8. T = 1 for ODT option, 0 for No ODT option Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 26 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Boundary Scan Exit Order ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal Notes: 1. NC pins as defined on the FBGA Ball Assignments are read as ”don’t cares”. 2. State of internal pin (#109) is loaded via JTAG Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 27 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Ordering Information Commercial Range: 0°C to +70°C Speed 550 MHz 500 MHz 450 MHz 400 MHz Order Part No. IS61DDPB251236A-550M3 IS61DDPB251236A-550M3L IS61DDPB21M18A-550M3 IS61DDPB21M18A-550M3L IS61DDPB251236A-500M3 IS61DDPB251236A-500M3L IS61DDPB21M18A-500M3 IS61DDPB21M18A-500M3L IS61DDPB251236A-450M3 IS61DDPB251236A-450M3L IS61DDPB21M18A-450M3 IS61DDPB21M18A-450M3L IS61DDPB251236A-400M3 IS61DDPB251236A-400M3L IS61DDPB21M18A-400M3 IS61DDPB21M18A-400M3L Organization 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 Package 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 166 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free Organization 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 Package 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 166 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free Commercial Range: °C to +70°C Speed 550 MHz 500 MHz 450 MHz 400 MHz Order Part No. IS61DDPB251236A-550B4 IS61DDPB251236A-550B4L IS61DDPB21M18A-550B4 IS61DDPB21M18A-550B4L IS61DDPB251236A-500B4 IS61DDPB251236A-500B4L IS61DDPB21M18A-500B4 IS61DDPB21M18A-500B4L IS61DDPB251236A-450B4 IS61DDPB251236A-450B4L IS61DDPB21M18A-450B4 IS61DDPB21M18A-450B4L IS61DDPB251236A-400B4 IS61DDPB251236A-400B4L IS61DDPB21M18A-400B4 IS61DDPB21M18A-400B4L Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 28 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Industrial Range: -40°C to +85°C Speed 550 MHz 500 MHz 450 MHz 400 MHz Order Part No. IS61DDPB251236A-550M3I IS61DDPB251236A-550M3LI IS61DDPB21M18A-550M3I IS61DDPB21M18A-550M3LI IS61DDPB251236A-500M3I IS61DDPB251236A-500M3LI IS61DDPB21M18A-500M3I IS61DDPB21M18A-500M3LI IS61DDPB251236A-450M3I IS61DDPB251236A-450M3LI IS61DDPB21M18A-450M3I IS61DDPB21M18A-450M3LI IS61DDPB251236A-400M3I IS61DDPB251236A-400M3LI IS61DDPB21M18A-400M3I IS61DDPB21M18A-400M3LI Organization 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 Package 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 166 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free 165 FBGA (15x17 mm) 165 FBGA (15x17 mm), lead free Industrial Range: -40°C to +85°C Speed 550 MHz 500 MHz 450 MHz 400 MHz Order Part No. IS61DDPB251236A-550B4I IS61DDPB251236A-550B4LI IS61DDPB21M18A-550B4I IS61DDPB21M18A-550B4LI IS61DDPB251236A-500B4I IS61DDPB251236A-500B4LI IS61DDPB21M18A-500B4I IS61DDPB21M18A-500B4LI IS61DDPB251236A-450B4I IS61DDPB251236A-450B4LI IS61DDPB21M18A-450B4I IS61DDPB21M18A-450B4LI IS61DDPB251236A-400B4I IS61DDPB251236A-400B4LI IS61DDPB21M18A-400B4I IS61DDPB21M18A-400B4LI Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 Organization 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 512Kx36 512Kx36 1Mx18 1Mx18 Package 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 166 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 165 FBGA (13x15 mm) 165 FBGA (13x15 mm), lead free 29 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 Package Outline 1. Controlling dimension : mm NOTE : 12/10/2007 Package drawing – 15x17x1.4 BGA 30 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Package drawing – 13x15x1.4 BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 31