IXYS IXD611P7

IXD611
IXD611
600V, 600 mA High & Low-side Driver
for N-Channel MOSFETs and IGBTs
Features
General Description
• Floating High Side Driver with boot-strap Power
supply along with a Low Side Driver.
• Fully operational to 600V
• ± 50V/ns dV/dt immunity
• Gate drive power supply range: 10 - 35V
• Undervoltage lockout for both output drivers
• Outputs are in phase with inputs
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up protected over entire
operating range
• High peak output current: ± 600 mA
• Matched propagation delay for both outputs
• Low output impedance
• Low power supply current
• Immune to negative voltage transients
The IXD611, with its two inputs referenced to ground, has high
speed low side and high side gate ouptuts to drive either a pair
of N-channel MOSFETs or IGBTs in a half-bridge totem pole
configuration. The High Side driver can control a MOSFET or
IGBT connected to a positive high voltage up to 600V. The logic
input stages are compatible with TTL or CMOS, have built-in
hysteresis and are fully immune to latch up over the entire
operating range. The IXD611 can withstand dV/dt on the output
side up to ± 50V/ns.
The IXD611 comes in either the 8-PIN PDIP (IXD611P1), 8-PIN
SOIC (IXD611S1), 14-PIN PDIP (IXD611P7), or the 14-PIN
SOIC (IXD611S7) packages.
Ordering Information
Applications
•
•
•
•
•
•
Driving MOSFETs and IGBTs in half-bridge circuits
High voltage, high side and low side drivers
Motor Controls
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Class D Switching Amplifiers
Part Number
Package Type
IXD611P1
IXD611P7
IXD611S1
IXD611S7
8-PIN DIP
14-PIN DIP
8-PIN SOIC
14-PIN SOIC
Warning: The IXD611 is ESD sensitive.
Figure 1A. Typical Circuit for IXD611P7/S7
Figure 1B. Typical Circuit for IXD611P1/S1
Up to 600V
VCC
VCL
HGO
VCH
HIN
HIN
HS
LIN
LIN
Up to 600V
VCC
VCL
HGO
VCH
HIN
HIN
HS
LIN
LIN
GND
LS
To Load
To Load
LS
GND
DG
LGO
© 2007 IXYS CORPORATION All rights reserved
LGO
DS99198A(10/07)
1
First Release
IXD611
Figure 2. IXD611 Functional Block Diagram
Pin Description And Configuration
SYMBOL
VCL
HIN
LIN
DG
VCH
HGO
HS
LGO
LS
FUNCTION
DESCRIPTION
Supply Voltage Low side power supply.
HS Input
High side Input signal, TTL or CMOS compatible; HGO in phase
LS Input
Low side Input signal, TTL or CMOS compatible; LGO in phase
Ground
Logic reference ground (Not available for IXD611P1, IXD611S1)
Supply Voltage High side floating power supply, referenced to HS
Output
High side driver output
Return
High side floating ground
Output
Low side driver output
Ground
Low side ground
IXYS reserves the right to change limits, test conditions, and dimensions.
2
IXD611
Figure 3A. Pin configuration for IXD611P1 (8 pin DIP) and IXD611S1 (8 pin SOIC)
VCH
2
HIN
3
LIN
4
IXD611P1
VCL
8
VCL
HGO
7
2
HIN
6
3
LIN
HS
4
LS
VCH
8
HGO
7
HS
6
LGO
5
5
LGO
LS
1
IXD611S1
1
8 pin DIP
8 pin SOIC
Figure 3B. Pin configuration for IXD611P7 (14 pin DIP) and IXD611S7 (14 pin SOIC)
NC
14
HIN
VCH
13
3
LIN
HGO
12
11
4
NC
HS
11
NC
10
5
DG
NC
10
LS
NC
9
6
LS
NC
9
LGO
NC
8
7
LGO
NC
8
1
HIN
VCH
13
2
3
LIN
HGO
12
4
NC
HS
5
DG
6
7
2
14 pin DIP
© 2007 IXYS CORPORATION All rights reserved
VCL
IXD611S7
14
VCL
IXD611P7
NC
1
14 pin SOIC
3
IXD611
Absolute Maximum Ratings
Symbol
VHS
Definition
High side floating supply offset voltage
Min
-200
Max
650
VCH
High side floating absolute voltage
-0.3
35
V
VHGO
High side floating output voltage
VHS - 0.3
VCH + 0.3
V
VCL
Low side fixed supply voltage
-0.3
35
V
V LGO
Low side output voltage
-0.3
VCL + 0.3
V
VDG
Logic supply offset voltage (P7, S7 only)
VLS - 0.7
VLS + 0.7
V
VIN
Logic input voltage(HIN & LIN)
LS - 0.3
VCL + 0.3
V
dVHS/dt
Allowable offset supply voltage transient
PD
Package power [email protected] TA ≤ 25C
8 pin PDIP
8 pin SOIC
14 pin PDIP
14 pin SOIC
1.0
0.625
1.6
1.0
RTHJA
Thermal resistance, junction-to-ambient
8 pin PDIP
125
o
C/W
8 pin SOIC
200
o
C/W
14 pin PDIP
75
o
C/W
14 pin SOIC
120
o
C/W
150
o
150
o
300
o
TJ
Junction Temperature
TS
Storage temperature
TL
50
-55
Lead temperature (soldering, 10 s)
Units
V
V/ns
W
W
W
W
C
C
C
Recommended Operating Conditions
Symbol
Definition
Min
Max
Units
VHS
High side floating supply offset voltage
-200
600
V
VCH
High side floating supply absolute voltage
10
30
V
VHGO
High side floating output voltage
VHS
VCH
V
VCL
Low side fixed supply voltage
10
30
V
V LGO
Low side output voltage
0
VCL
V
VDG
Logic supply offset voltage (P7, S7 only)
VLS - 0.3
VIN
Logic input voltage(HIN, LIN)
VDG or LS
VCL
V
TA
Ambient Temperature
-40
125
o
IXYS reserves the right to change limits, test conditions, and dimensions.
4
VLS + 0.3
V
C
IXD611
Dynamic Electrical Characteristics
Symbol
Definition
Test Conditions
ton
Turn-on propagation delay
toff
Min
Typ
Max
Units
VCL= VCH = 15V, CLOAD= 1nF
180
200
ns
Turn-off propagation delay
VCL= VCH = 15V, CLOAD= 1nF
170
190
ns
tr
Turn-on rise time
VCL= VCH = 15V, CLOAD= 1nF
28
35
ns
tf
Turn-off fall time
VCL= VCH = 15V, CLOAD= 1nF
18
25
ns
t dm
Delay matching, HS & LS turn-on/off
CLOAD= 1nF
10
20
ns
Typ
Max
Static Electrical Characteristics
Symbol
Definition
Test Conditions
Min
VINH
Logic “1” input voltage
VCL = VCH= 15V
2.7
VINL
Logic “0” input voltage
VCL= VCH = 15V
VHLGO // VHHGO High level output voltage,
Units
V
2.4
V
IO = 20mA
0.22
0.3
V
IO = 20mA
0.16
0.25
V
VCH-VHGO or VCL-VLGO
VLLGO // VLHGO Low level output voltage,
VHGO or VLGO
I HL
HS to LS bias current.
VHS = 600V
0.12
0.2
mA
I QHS
Quiescent VCH supply current
VCH= 15V VIN= 0V or VIN = 5 V
0.7
0.8
mA
I QLS
Quiescent VCL supply current
VCL= 15V VIN= 0V or VIN = 5 V
0.18
0.3
mA
IIN+
Logic “1” input bias current
VIN = VSUPPLY = 15V
11
20
uA
I IN-
Logic “0” input bias current
VIN = 0V
1
2
uA
VCHUV+
VCH supply undervoltage positive going threshold.
7.5
8
8.5
V
VCHUV-
VCH supply undervoltage negative going threshold.
7
7.3
8
V
VCLUV+
VCL supply undervoltage positive going threshold
7.5
8
8.5
V
VCLUV-
VCL supply undervoltage negative going threshold.
7
7.5
8
V
0.3
0.6
V
I GO+
HS or LS Output high short circuit current; VGO= 15V, VIN= 5V, PW<10us 0.5
0.6
A
I GO-
HS or LS Output low short circuit current; VGO= 15V, VIN= 0V, PW<10us
-0.6
VCHUVH, VCLUVH Undervoltage Hysteresis
Precaution : When performing the high voltage tests, adequate safety precautions should be taken.
© 2007 IXYS CORPORATION All rights reserved
5
-0.5
A
IXD611
Timing Waveform Definitions
Figure 4. INPUT/OUPUT Timing Diagram
50%
50%
50%
HIN
LIN
tr
tdoff
tdon
90%
50%
HIN
LIN
tf
90%
LGO
HGO
90%
tdm
10%
HGO
LGO
10%
LGO
HGO
tdm
10%
Outgoing Signal
Figure 5. Definitions of Switching Time Waveforms
Figure 6. Definitions of Delay Matching Waveforms
500V
Sa
mp
le
400V
Te
ste
d
~
0
for
Op
era
tio
~
V++ Buss (V HS )
600V
100kHz 300kHz
~
n
1MHz
fPWM
Figure 7. Device operating range: Buss voltage vs. Frequency
Tested in typical circuit configuration (refer to Figure 9 & 10)
IXYS reserves the right to change limits, test conditions, and dimensions.
6
IXD611
10V
DC_DC Boost
Vout+
10V
10uF
Low ESR
100uF 25V
Low ESR
NDY1215C
Up to 600V
Vout-
GND
1.5k 2W
15V
VCL
HIN
VCH
HGO
IXD611
10uF
TX 30:1
HS
50
20uF 10x0.1uF
1kV 1kV
LGO N/C
LIN
0.1uF
HGO Out
1nF
LS
Measure dV/dt
dv/dt slope adjustment
Drive Input
IXDN414
100 ohm
multi turn
Figure 8. Test circuit for allowable offset supply voltage transient.
1
VCL
11
1uF/35V MLCC
12
VOUTVOUT+
GND
NDY1215C
10uF/35V
10
VIN+
Up to 500V
3
1
VOUT- 15
14
VOUT+
1k
IXCP
10M90S
2
30
5.1
10uF/35V
1
1k
2
1k
3
4
1N5817
15
VCL
HIN
LIN
LS
IXD611S1
VCL
HIN
LIN
1uF/35V MLCC
VCH
HGO
HS
LGO
IXTH14N60P
8
7
18uH
0.1uF/1kV
6
5
5.1
1N5817
0.47uF
0.47uF
15
IXTH14N60P
© 2007 IXYS CORPORATION All rights reserved
7
20/5W
20/5W
Figure 9. Test circuit for high frequency, 750kHz, operation.
VCH, VCL = 15V
IXD611
1
VCL
11
1uF/35V MLCC
12
VOUTVOUT+
GND
NDY1215C
10uF/35V
10
VIN+
Up to 600V
3
1
VOUT- 15
14
VOUT+
1k
IXCP
10M90S
2
30
5.1
10uF/35V
1
1k
2
1k
3
4
1N5817
51
VCL
HIN
LIN
LS
IXD611S1
VCL
HIN
LIN
1uF/35V MLCC
VCH
HGO
HS
LGO
IXTH14N60P
8
7
0.1uF/1kV
6
5
5.1
1N5817
51
Figure 10. Test circuit for low frequency, 75kHz, operation.
VCH, VCL = 15V
IXYS reserves the right to change limits, test conditions, and dimensions.
8
IXTH14N60P
IXD611
Fig. 11
Fig.12
Rise Times vs. Supply Voltage
Fall Times vs. Supply Voltage
25
40
35
Fall Time (ns)
Rise Time (ns)
20
30
25
1000 pF
20
15
1000 pF
15
10
10
100 pF
5
5
100 pF
0
0
0
5
10
15
20
25
30
35
40
0
5
10
Supply Voltage (V)
Fig. 13
15
20
25
30
35
40
Supply Voltage (V)
Fig. 14
Rise / Fall Times vs. Temperature
VIN = VSUPPLY = 15V CLOAD = 1000pF
Propagation Delay vs. Supply Voltage
CL = 1000pF VIN = VSUPPLY
40
260
Propagation Delay (ns)
Rise / Fall Times (ns)
35
30
Rise
25
Fall
20
15
10
240
220
200
Low side positive going
180
Low side negative going
160
140
High side positive going
120
High side negative going
5
100
0
0
-50
0
50
100
5
10
150
Temperature (C)
Fig.15
15
20
25
30
35
40
Supply Voltage (V)
Fig. 16
Propagation Delay vs. Temperature
VIN = VSUPPLY = 15V CLOAD = 1000pF
Under Voltage Lock Out vs. Temperature
10
190
Lock Out Threshold (V)
Propagation Delay(ns)
9.5
185
180
Pos. going input
175
170
Neg. going input
165
160
155
150
-100
9
Pos. going supply voltage
8.5
8
7.5
Neg. going supply voltage
7
6.5
6
5.5
-50
0
50
100
5
-100
150
Temperature (C)
© 2007 IXYS CORPORATION All rights reserved
-50
0
50
Temperature (C)
9
100
150
IXD611
Fig. 17
Input Threshold Level vs. Temperature
VSUPPLY = 15V
Fig. 18
4
4
3.5
Threshold Level (V)
Threshold Level (V)
Input Threshold Level vs. Supply Voltage
4.5
3.5
3
Positve going
2.5
Negative going
2
1.5
1
3
Pos. going input
2.5
Neg. going input
2
1.5
1
0.5
0.5
0
0
0
5
10
15
20
25
30
35
-50
40
0
50
Supply Voltage (V)
Fig.19
Fig. 20
Quiescent Supply Current vs. Supply Voltage
VIN = "0"
1.2
100
150
Temperature (C)
Quiescent Current vs. Temperature
VIN = "0" VSUPPLY = 15V Both Drivers Combined
0.57
Quiescent Current (mA)
Quiescent Current (mA)
0.56
1
0.8
High side
0.6
0.4
Low side
0.2
0.55
0.54
0.53
0.52
0.51
0.5
0.49
0
0.48
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
-50
50
100
150
Temperature (C)
Fig.21
LIN / HIN Bias Current vs. Supply Voltage
V IN = Supply Voltage
Fig.22
30
LIN / HIN Bias Current vs. Temperature
V SUPPLY = 15V
16
Input Bias Current (uA)
Input Bias Current (uA)
0
25
20
15
Logic "1" either input pin
10
5
Logic "0" 2uA
max.
0
14
V IN = 15V
12
10
8
6
V IN = 5V
4
2
0
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
IXYS reserves the right to change limits, test conditions, and dimensions. 10
-50
0
50
Temperature (C)
100
150
IXD611
Fig. 23
Fig. 24
Low Level Output Voltage vs. Supply Voltage
Io = 20mA
300
180
High Level Ouput Voltage (mV)
Low Level Output Voltage (mV)
200
160
Low Side
140
120
High Side
100
80
60
40
20
High Level Ouput Voltage vs. Supply Voltage
Io = 20mA
250
Low Side
200
High Side
150
100
50
0
0
0
5
10
15
20
25
30
10
20
25
30
35
Output Sink Current vs. Supply Voltage
0
1.8
-0.2
Output Sink Current (A)
2
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
0
0
5
10
15
20
25
30
35
0
40
5
10
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
Fig. 27
Fig. 28
Output Sink Current vs. Temeprature
VSUPPLY = 15V
Output Source Current vs. Temperature
VSUPPLY = 15V
0.9
0
0.8
-0.1
0.7
-0.2
Sink Current (A)
Source Current (A)
15
Fig. 26
Output Source Current vs. Supply Voltage
Output Source Current (A)
5
Supply Voltage (V)
Supply Voltage (V)
Fig. 25
0
35
0.6
0.5
0.4
0.3
0.2
0.1
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
0
-0.9
-50
0
50
100
150
-50
Temperature (C)
© 2007 IXYS CORPORATION All rights reserved
0
50
Temperature (C)
11
100
150
IXD611
Fig. 29
Supply Current vs. Supply Voltage
CLOAD = 100pF VIN = VSUPPLY 50% Duty Cycle
Supply Current vs. Supply Voltage
CLOAD = 1000pF VIN = VSUPPLY 50% Duty Cycle
Fig. 30
100
100
2MHz
1MHz
10
High side 100KHz
Low side 100KHz
High side 10KHz
1
Low side 10KHz
Supply Current (mA)
Supply Current (mA)
1MHz
2MHz
10
100KHz
High Side10KHz
1
Low Side10KHz
0.1
0.1
0
5
10
15
20
25
30
35
0
40
Supply Voltage (V)
5
15
20
25
30
35
40
Supply Voltage (V)
Fig. 32
Fig. 31
10
High to Low Side Leakage Current vs. Temperature
VOFFSET = 600V VCL = VCH = 15V
High To Low Side Leakage Current vs.High Side VOFFSET
0.16
130
Leakage Current (uA)
Leakage Current (mA)
132
0.14
0.12
0.1
0.08
0.06
0.04
0.02
128
126
124
122
120
118
116
0
114
0
100
200
300
400
500
600
700
-50
0
High Side Offset Voltage (V)
100
150
Temperature (C)
Pulse Width Stability vs. Temperature
VCL = VCH = 15V Input PW = 300ns
Fig. 34
Fig. 33
Output Resistance vs. Supply Voltage
14
305
12
10
High State / Low Side
High State / High Side
8
Low State / Low Side
6
Low State / High Side
4
Pulse Width Out (ns)
Output Resistance (Ohms)
50
300
High Side
295
290
Low Side
285
2
280
0
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
IXYS reserves the right to change limits, test conditions, and dimensions. 12
-50
0
50
Temperature (C)
100
150
IXD611
Fig. 35
Fig. 36
Normalized PW Out vs. PW In (Low Side)
VIN = VSUPPLY = 10V, 20V, 30V CLOAD = 1000pF
Normalized PW Out vs. PW In (High Side)
VIN = VSUPPLY = 10V, 20V, 30V CLOAD = 1000pF
1.2
1.2
1
Normalized PW Out
Normalized PW Out
1
20V
10V
0.8
0.6
0.4
0.2
0.8
30V
0.6
0.4
0.2
0
0
0
50
100
150
200
250
300
350
0
400
100
150
200
250
Pulse Width In (ns)
Pulse Width In (ns)
© 2007 IXYS CORPORATION All rights reserved
50
13
300
350
400
IXD611
IXD611S1 Package
IXD611P1 Package
IXD611P7 Package
IXD611S7 Package
SYM
14 13 12 11 10
9
8
INCHES
MILLIMETERS
MIN
MAX
MIN
A
.053
.069
1.35
1.75
A1
.004
.010
0.10
0.25
.013
.020
0.33
0.51
.008
.010
0.19
0.25
.337
.344
8.55
8.75
.150
.157
3.80
4.00
.050 BSC
1
2
3
4
5
6
7
MAX
1.27 BSC
.228
.244
5.80
6.20
.010
.020
0.25
0.50
.016
.050
0.40
1.27
0
8
0
8
NOTE: This drawing will meet all dimensions requirement of JEDEC MS-012 AB.
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
www.ixys.com
IXYS reserves the right to change limits, test conditions, and dimensions. 14
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]