Agilent HCPL-7860/HCPL-786J Optically Isolated Σ−∆ Sigma-Delta (Σ−∆ Σ−∆) Modulator Data Sheet Description The HCPL-7860/HCPL-786J Optically Isolated Modulator and HCPL-0872 Digital Interface IC or digital filter together form an isolated programmable two-chip analog-to-digital converter. The isolated modulator allows direct measurement of motor phase currents in power inverters. 2 3 SIGMA DELTA MOD./ ENCODE 7 DECODE 4 Features • 12-bit Linearity • 200 ns Conversion Time (PreTrigger Mode 2 with HCPL-0872) • 12-bit Effective Resolution with 5 µs Signal Delay (14-bit with 102 µs) (with HCPL-0872) • Fast 3 µs Over-Range Detection (with HCPL-0872) • ± 200 mV Input Range with Single 5 V Supply • 1% Internal Reference Voltage Matching • Offset Calibration (with HCPL0872) • -40°C to +85°C Operating Temperature Range • 15 kV/µ µs Isolation Transient Immunity • Safety Approval: UL 1577, CSA and IEC/EN/DIN EN 60747-5-2 8 1 Input Current In operation, the HCPL-7860/ HCPL-786J Isolated Modulator (optocoupler with 3750 VRMS dielectric withstand voltage rating) converts a lowbandwidth analog input into a high-speed one-bit data stream by means of a Sigma-Delta (Σ− ∆) over-sampling modulator. This modulation provides for high noise margins and excellent immunity against isolation-mode transients. The modulator data and on-chip sampling clock are encoded and transmitted across the isolation boundary where they are recovered and decoded into separate high-speed clock and data channels. 6 HCPL-0872 or Digital Filter 5 HCPL-7860 MCU or DSP Applications • Motor Phase and Rail Current Sensing • Data Acquisition Systems • Industrial Process Control • Inverter Current Sensing • General Purpose Current Sensing and Monitoring A 0.1 µF bypass capacitor must be connected between pins VDD and Ground CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD. SPI and QSPI are trademarks of Motorola Corp. Microwire is a trademark of National Semiconductor Inc. Pin Description ISOLATION BOUNDARY V DD1 V IN+ V DD1 1 V IN+ 2 V IN- 3 8 SIGMADELTA MOD./ ENCODE GND1 4 7 V DD2 MCLK DECODE SHIELD 6 MDAT 5 GND2 1 16 GND2 2 15 NC V IN- 3 NC 4 NC 5 NC 6 NC GND1 14 V DD2 13 MCLK 12 NC 11 MDAT 7 10 NC 8 9 GND2 SIGMADELTA MOD./ ENCODER HCPL-7860 DECODER HCPL-786J Symbol Description Symbol Description VDD1 Supply voltage input (4.5 V to 5.5 V) VDD2 Supply voltage input (4.5 V to 5.5 V) VIN+ Positive input (± 200 mV recommended) MCLK Clock output (10 MHz typical) VIN- Negative input (normally connected to GND1) MDAT Serial data output GND1 Input ground GND2 Output ground Ordering Information Specify part number followed by option number (if desired). Example: HCPL-7860#XXXX No option = Standard DIP package, 50 units per tube. 300 = Gull Wing Surface Mount Option, 50 units per tube. 500 = Tape and Reel Packaging Option, 1000 units per reel. XXXE = Lead-Free Option HCPL-786J#XXXX No option = Standard DIP package, 45 units per tube. 500 = Tape and Reel Packaging Option, 850 units per reel. XXXE = Lead-Free Option Option data sheets available. Contact Agilent sales representative or authorized distributor. Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–” 2 Package Outline Drawings 8-pin DIP Package 9.80 ± 0.25 (0.386 ± 0.010) TYPE NUMBER 8 7 6 5 A 7860X REFERENCE VOLTAGE MATCHING SUFFIX* DATE CODE YYWW PIN ONE 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 6.35 ± 0.25 (0.250 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. 2.54 ± 0.25 (0.100 ± 0.010) 5˚ TYP. 0.20 (0.008) 0.33 (0.013) DIMENSIONS IN MILLIMETERS AND (INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20mils) MAX. NOTE: INITIAL OR CONTINUED VARIATION IN THE COLOUR OF THE HCPL-7860/HCPL-786J’S WHITE MOLD COMPOUND IS NORMAL AND DOES NOT AFFECT DEVICE PERFORMANCE OR RELIABILITY. *ALL UNITS WITHIN EACH HCPL-7860 STANDARD PACKAGING INCREMENT (EITHER 50 PER TUBE OR 1000 PER REEL) HAVE A COMMON MARKING SUFFIX TO REPRESENT AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF ± 1%. AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF ± 4% IS GUARANTEED BETWEEN STANDARD PACKAGING INCREMENTS. 3 8-pin Gull Wing Surface Mount Option 300 LAND PATTERN RECOMMENDATION 9.80 ± 0.25 (0.386 ± 0.010) 6 7 8 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 3 2 10.9 (0.430) 4 2.0 (0.080) 1.27 (0.050) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 0.20 (0.008) 0.33 (0.013) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 2.540 (0.100) BSC 12˚ NOM. 0.51 ± 0.130 (0.020 ± 0.005) LEAD COPLANARITY MAXIMUM: 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 16-Lead Surface Mount LAND PATTERN RECOMMENDATION 0.457 (0.018) 1.270 (0.050) 16 15 14 13 12 11 10 0.64 (0.025) 9 TYPE NUMBER DATE CODE A 786J YYWW 7.493 ± 0.254 (0.295 ± 0.010) 11.63 (0.458) 2.16 (0.085) 1 2 3 4 5 6 7 8 10.312 ± 0.254 (0.406 ± 0.10) ALL LEADS TO BE COPLANAR ± 0.002 8.986 ± 0.254 (0.345 ± 0.010) 9˚ 0.457 (0.018) 3.505 ± 0.127 (0.138 ± 0.005) 0-8˚ 0.025 MIN. 10.160 ± 0.254 (0.408 ± 0.010) 0.203 ± 0.076 (0.008 ± 0.003) STANDOFF DIMENSIONS IN MILLIMETERS AND (INCHES). NOTE: Initial and continued variation in the color of the HCPL-786J's white mold compound is normal and does not affect device performance or reliability. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 4 Solder Reflow Temperature Profile 300 PREHEATING RATE 3˚C + 1˚C/-0.5˚C/SEC. REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC. PEAK TEMP. 240˚C PEAK TEMP. 230˚C 200 TEMPERATURE (˚C) PEAK TEMP. 245˚C 2.5˚C ± 0.5˚C/SEC. 30 SEC. 160˚C 150˚C 140˚C SOLDERING TIME 200˚C 30 SEC. 3˚C + 1˚C/-0.5˚C 100 PREHEATING TIME 150˚C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 250 TIME (SECONDS) Recommended Lead Free IR Profile tp TIME WITHIN 5˚C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 260 +0/-5˚C TEMPERATURE (˚C) Tp TL T smax 217˚C RAMP-UP 3˚C/SEC. MAX. 150 - 200˚C RAMP-DOWN 6˚C/SEC. MAX. T smin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. 25 t 25˚C to PEAK TIME (SECONDS) NOTES: THE TIME FROM 25˚C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200˚C, Tsmin = 150˚C Regulatory Information The HCPL-7860/HCPL-786J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. 5 UL Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Description Symbol HCPL-7860/786J Unit Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 Vrms for rated mains voltage ≤ 600 Vrms I - IV I - III I - II Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 891 Vpeak Input to Output Test Voltage, Method b VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1670 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,Partial discharge < 5 pC VPR 1336 Vpeak Highest Allowable Overvoltage(Transient Overvoltage tini = 10 sec) VIOTM 6000 Vpeak Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 175 400 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS >109 Ω  Notes: 1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. Surface Mount Classifications is Class A in accordance with CECC00802. 2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. 3. Refer to the following figure for dependence of PS and IS on ambient temperature. OUTPUT POWER - PS, INPUT CURRENT - IS VIORM Maximum Working Insulation Voltage 800 P S (mW) 700 IS (mA) 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - oC Insulation and Safety Related Specifications Option 300 - surface mount classification is Class A in accordance with CECC 00802. Parameter Symbol DIP-8 SO-16 Units Conditions Minimum External Air Gap L(101) (Clearance) 7.4 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) 8.0 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. >175 >175 V DIN IEC 112/VDE 0303 Part 1 IIIa IIIa L(102) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group 6 CTI Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Ambient Operating Temperature TA -40 85 °C Supply Voltages VDD1, VDD2 0 5.5 V Steady-State Input Voltage VIN+, VIN- -2.0 VDD1 + 0.5 V VDD2 + 0.5 V Two Second Transient Input Voltage Note 1 -6.0 Output Voltages MCLK, MDAT -0.5 Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Maximum Solder Reflow Thermal Profile section 2 Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA -40 +85 °C Supply Voltages VDD1, VDD2 4.5 5.5 V Input Voltage VIN+, VIN- -200 +200 mV Note 1 Electrical Specifications (DC) Unless otherwise noted, all specifications are at VIN+ = 0 V and VIN- = 0 V, all Typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply over the following ranges: TA = -40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V. Parameter Symbol Average Input Bias Current IIN -0.8 µA Average Input Resistance RIN 450 kΩ 3 Input DC Common-Mode Rejection Ratio CMRRIN 60 dB 4 Output Logic High Voltage VOH 4.9 V IOUT = -100 µA Output Logic Low Voltage VOL 0.1 V IOUT = 1.6 mA Output Short Circuit Current |IOSC| 30 mA VOUT = VDD2 or GND2 Input Supply Current IDD1 10 15 mA Output Supply Current IDD2 10 15 mA VIN+ = -350 mV to +350 mV Output Clock Frequency fCLK 10 13.2 MHz Data Hold Time tHDDAT 7 Min. 3.9 8.2 Typ. 15 Max. 0.6 Units ns Conditions Fig. Note 1 3 5 2 3 4 6 Electrical Specifications (Tested with HCPL-0872 or Sinc3 Filter) Unless otherwise noted, all specifications are at VIN+ = -200 mV to +200 mV and VIN- = 0 V; all Typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply over the following ranges: TA = 40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V. STATIC CHARACTERISTICS Parameter Symbol Resolution Min. Typ. Max. 15 Integral Nonlinearity INL Units Conditions Fig. bits 7 3 30 LSB 5 8 0.01 0.14 % 6 8 1 LSB 0 3 mV VIN+ = 0 V 7 10 µV/°C VIN+ = 0 V 7 VIN+ = 0 V 7 Differential Nonlinearity DNL Uncalibrated Input Offset VOS Offset Drift vs. Temperature dVOS/dTA 2 Offset drift vs. VDD1 dVOS/dVDD1 0.12 mV/V Internal Reference Voltage VREF 320 mV 8 8 -3 Note Absolute Reference Voltage Tolerance -4 4 % Reference Voltage Matching HCPL-7860 -1 1 % HCPL-786J -2 2 % 9 TA = 25°C. See Note 11 8 VREF Drift vs. Temperature dVREF/dTA 60 ppm/°C. 8 VREF Drift vs. VDD1 dVREF/dVDD1 0.2 % 8 Full Scale Input Range -VREF +VREF mV Recommended Input Voltage Range -200 +200 mV 10 DYNAMIC CHARACTERISTICS (Digital Interface IC HCPL-0872 is set to Conversion Mode 3.) Parameter Symbol Min. Typ. Signal-to-Noise Ratio SNR 62 Total Harmonic Distortion Units Conditions Fig. 73 dB 9,10 THD -67 dB Signal-to-(Noise + Distortion) SND 66 dB VIN+ = 35 Hz, 400 mVpk-pk (141 mVrms) sine wave. Effective Number of Bits ENOB 12 bits Conversion Time tC2 0.2 0.8 µs tC1 19 23 tC0 39 Signal Delay tDSIG Over-Range Detect Time tOVR1 Threshold Detect Time (default configuration) tTHR1 Signal Bandwidth BW Isolation Transient Immunity CMR 8 10 2.0 Max. Note 11 12 Pre-Trigger Mode 2 1,12 13 µs Pre-Trigger Mode 1 1,12 13 47 µs Pre-Trigger Mode 0 1,12 19 23 µs 3.0 4.2 µs 10 µs 18 22 kHz 15 20 kV/µs VIN+ = 0 to 400mV step waveform 13 14 14 15 16 15 VISO = 1 kV 17 18 Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage* VISO 3750 Input-Output Resistance RI-O 1012 Typ. 1013 Max. Units Conditions Note Vrms RH ≤ 50%, t = 1 min; TA = 25°C 19, 20 Ω VI-O = 500 Vdc 20 1011 TA = 100°C Input-Output Capacitance CI-O 1.4 pF f = 1 MHz Input IC Junction-to-Case Thermal Resistance θjci 96 °C/W Thermocouple located at center underside of package Output IC Junction-to-Case Thermal Resistance θjco 114 °C/W 20 *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an inputoutput continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level safety specification, or Agilent Application Note 1074, “Optocoupler Input-Output Endurance Voltage.” Notes: 1. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an internal opticalcoupling test mode may be activated. This test mode is not intended for customer use. 2. Agilent recommends the use of nonchlorinated solder fluxes. 3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown. 4. CMRRIN is defined as the ratio of the gain for differential inputs applied between VIN+ and VIN- to the gain for common-mode inputs applied to both VIN+ and VIN- with respect to input ground GND1. 5. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or GND2. Use under these conditions is not recommended. 6. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK. 7. Resolution is defined as the total number of output bits. The useable accuracy of any A/ D converter is a function of its linearity and signal-to-noise ratio, rather than how many total bits it has. 8. Integral nonlinearity is defined as one-half the peak-to-peak deviation of the best-fit line through the transfer curve for VIN+ = 200 mV to +200 mV, expressed either as the number of LSBs or as a percent of measured input range (400 mV). 9. Differential nonlinearity is defined as the deviation of the actual difference from the ideal difference between midpoints of successive output codes, expressed in LSBs. 10. Data sheet value is the average magnitude of the difference in offset voltage from TA =25°C to TA= 85°C, expressed in microvolts 9 11. 12. 13. 14. per °C. Three standard deviation from typical value is less than 6 µV/°C. Beyond the full-scale input range the output is either all zeroes or all ones. The effective number of bits (or effective resolution) is defined by the equation ENOB = (SNR-1.76)/6.02 and represents the resolution of an ideal, quantization-noise limited A/D converter with the same SNR. Conversion time is defined as the time from when the convert start signal CS is brought low to when SDAT goes high, indicating that output data is ready to be clocked out. This can be as small as a few cycles of the isolated modulator clock and is determined by the frequency of the isolated modulator clock and the selected Conversion and PreTrigger modes. For determining the true signal delay characteristics of the A/D converter for closed-loop phase margin calculations, the signal delay specification should be used. Signal delay is defined as the effective delay of the input signal through the Isolated A/D converter. It can be measured by applying a -200 mV to ± 200 mV step at the input of modulator and adjusting the relative delay of the convert start signal CS so that the output of the converter is at mid scale. The signal delay is the elapsed time from when the step signal is applied at the input to when output data is ready at the end of the conversion cycle. The signal delay is the most important specification for determining the true signal delay characteristics of the A/D converter and should be used for determining phase margins in closed-loop applications. The signal delay is determined by the frequency of the modulator clock and which Conversion Mode is selected, and is 15. 16. 17. 18. 19. 20. independent of the selected Pre-Trigger Mode and, therefore, conversion time. The minimum and maximum overrange detection time is determined by the frequency of the channel 1 isolated modulator clock. The minimum and maximum threshold detection time is determined by the userdefined configuration of the adjustable threshold detection circuit and the frequency of the channel 1 isolated modulator clock. See the Applications Information section for further detail. The specified times apply for the default configuration. The signal bandwidth is the frequency at which the magnitude of the output signal has decreased 3 dB below its low-frequency value. The signal bandwidth is determined by the frequency of the modulator clock and the selected Conversion Mode. The isolation transient immunity (also known as Common-Mode Rejection) specifies the minimum rate-of-rise of an isolation-mode signal applied across the isolation boundary beyond which the modulator clock or data signals are corrupted. In accordance with UL1577, for devices with minimum VISO specified at 3750 Vrms, each isolated modulator (optocoupler) is prooftested by applying an insulation test voltage greater than 4500 Vrms for one second (leakage current detection limit II-O< 5µA). This test is performed before the Method b, 100% production test for partial discharge shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table. This is a two-terminal measurement: pins 14 are shorted together and pins 5-8 are shorted together. 1 10.5 -1 9.4 -40 ˚C 25 ˚C 85 ˚C 0 10.0 9.2 9.0 -4 -5 9.5 IDD2 - mA IDD1 - mA IIN - mA -2 -3 9.0 -6 8.2 -4 -2 0 2 8.0 -400 6 4 -200 200 0 V IN - V 8.0 -400 400 Figure 3. IDD2 vs. VIN . 7 V DD1 = 4.5 V V DD1 = 5.0 V V DD1 = 5.5 V 6 9.6 INL-LSB 9.4 9.2 0.02 V DD1 = 4.5 V V DD1 = 5.0 V V DD1 = 5.5 V V DD1 = 4.5 V V DD1 = 5.0 V V DD1 = 5.5 V 0.018 0.016 5 INL-% 10.0 400 200 V IN - mV Figure 2. IDD1 vs. VIN. 9.8 0 -200 V IN - mV Figure 1. IIN vs. VIN . CLOCK FREQUENCY - MHz -40 ˚C 25 ˚C 85 ˚C 8.5 -8 4 0.014 0.012 0.01 9.0 3 0.008 8.8 -15 10 35 60 2 -40 85 Figure 4. Clock Frequency vs. Temperature. 60 0.006 -40 85 0.6 50 0.4 V REF CHANGE - % 100 -50 V DD1 = 4.5 V V DD1 = 5.0 V V DD1 = 5.5 V -15 10 60 TEMPERATURE - ˚C Figure 7. Offset Change vs. Temperature 85 35 85 60 Figure 6. INL (%) vs. Temperature 68 V DD1 = 4.5 V V DD1 = 5.0 V V DD1 = 5.5 V 67 66 65 0.2 0 -0.4 -40 64 63 -0.2 35 10 -15 TEMPERATURE - ˚C 0.8 0 10 35 Figure 5. INL (Bits) vs. Temperature 150 -150 -40 10 TEMPERATURE - ˚C TEMPERATURE - ˚C -100 -15 SNR 8.6 -40 OFFSET CHANGE - µV 8.6 8.4 -7 -9 -6 8.8 62 -15 10 35 60 TEMPERATURE - ˚C Figure 8. VREF Change vs. Temperature 85 61 -40 V DD1 = 4.5 V V DD1 = 5.0 V V DD1 = 5.5 V -15 10 35 TEMPERATURE - ˚C Figure 9. SNR vs. Temperature 60 85 14 200 80 PRE-TRIGGER MODE 0 PRE-TRIGGER MODE 1 PRE-TRIGGER MODE 2 180 75 70 SNR 12 SNR 160 CONVERSION TIME - µs 13 11 10 65 60 55 9 50 8 45 1 2 3 4 5 Figure 10. SNR vs. Conversion Mode. 60 40 0 1 2 3 4 5 1 Figure 11. Effective Resolution vs. Conversion Mode. 2 3 4 5 CONVERSION MODE # Figure 12. Conversion Time vs. Conversion Mode. 100 90 V IN+(200 mV/DIV.) 80 70 OVR1 (200 mV/DIV.) 60 THR1 (2 V/DIV.) 50 40 30 20 SIGNAL BANDWIDTH - kHz 90 SIGNAL DELAY - µs 80 20 100 80 70 60 50 40 30 20 10 10 0 1 2 3 4 5 2 µs/DIV. CONVERSION MODE # Figure 13. Signal Delay vs. Conversion Mode. 11 120 100 CONVERSION MODE # CONVERSION MODE # 0 140 Figure 14. Over-Range and Threshold Detect Times. 1 2 3 4 CONVERSION MODE # Figure 15. Signal Bandwidth vs. Conversion Mode. 5 Applications Information Digital Current Sensing As shown in Figure 16, using the Isolated 2-chip A/D converter to sense current can be as simple as connecting a current-sensing resistor, or shunt, to the input and reading output data through the 3-wire serial output interface. By choosing the appropriate shunt resistance, any range of current can be monitored, from less than 1 A to more than 100 A. Even better performance can be achieved by fully utilizing the more advanced features of the Isolated A/D converter, such as the pre-trigger circuit, which can reduce conversion time to less than 1 µs, the fast over-range detector for quickly detecting short circuits, different conversion modes giving various resolution/speed trade-offs, offset calibration mode to eliminate initial offset from measurements, and an adjustable threshold detector for detecting non-short circuit overload conditions. NON-ISOLATED +5V ISOLATED +5V INPUT CURRENT + V DD1 V DD2 R SHUNT 0.02 V IN+ MCLK V IN- MDAT C1 0.1 µF GND1 GND2 HCPL-7860/ HCPL-786J C2 0.1 µF CCLK V DD CLAT CHAN CDAT SCLK MCLK1 SDAT MDAT1 CS MCLK2 THR1 MDAT2 OVR1 GND RESET HCPL-0872 Figure 16. Typical Application Circuit. 12 3-WIRE SERIAL INTERFACE + C3 10 µF Product Description The HCPL-7860/HCPL-786J Isolated Modulator (optocoupler) uses sigma-delta modulation to convert an analog input signal into a high-speed (10 MHz) single-bit digital data stream; the time average of the modulator’s single-bit data is directly proportional to the input signal. The isolated modulator’s other main function is to provide galvanic isolation between the analog input and the digital output. An internal voltage reference determines the full-scale analog input range of the modulator (approximately ± 320 mV); an input range of ± 200 mV is recommended to achieve optimal performance. HCPL-7860/HCPL-786J can be used together with HCPL-0872, Digital Interface IC or a digital filter. The primary functions of the HCPL-0872 Digital Interface IC are to derive a multi-bit output signal by averaging the single-bit modulator data, as well as to provide a direct microcontroller interface. The effective resolution of the multi-bit output signal is a function of the length of time (measured in modulator clock cycles) over which the average is taken; averaging over longer periods of time results in higher resolution. The Digital Interface IC can be configured for five conversion modes, which have different combinations of speed and resolution to achieve the desired level of performance. Other functions of the HCPL0872 Digital Interface IC include a Phase Locked Loop based pre-trigger circuit that can either give more precise control of the effective sampling time or reduce conversion time to less than 1 ìs, a fast over-range detection circuit that rapidly indicates when the magnitude of the input signal is beyond fullscale, an adjustable threshold detection circuit that indicates when the magnitude of the input signal is above a user adjustable threshold level, an offset calibration circuit, and a second multiplexed input that allows a second Isolated Modulator to be used with a single Digital Interface IC. The digital output format of the Isolated A/D Converter is 15 bits of unsigned binary data. The input full-scale range and code assignment is shown in Table 1 below. Although the output contains 15 bits of data, the effective resolution is lower and is determined by selected conversion mode as shown in Table 2 below. Table 1. Input Full-Scale Range and Code Assignment. Analog Input Voltage Input Digital Output 640 mV 32768 LSBs 20 µV 1 LSB +320 mV 111111111111111 0 mV 100000000000000 -320 mV 000000000000000 Full Scale Range Minimum Step Size +Full Scale Zero -Full Scale Table 2. Isolated A/D Converter Typical Performance Characteristics. Conversion Time (µs) Signal Delay(µs) Signal Bandwidth (kHz) 102 102 3.4 103 51 51 6.9 11.9 39 19 19 22 66 10.7 20 10 10 45 53 8.5 10 5 5 90 Signal-toNoise Ratio (dB) Effective Resolution (bits) 0 1 1 83 13.5 205 2 79 12.8 3 73 4 5 Conversion Mode Notes: Bold italic type indicates Default values. 13 Pre-Trigger Mode 2 0.2 Power Supplies and Bypassing The recommended application circuit is shown in Figure 17. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple zener diode (D1); the value of resistor R1 should be chosen to supply sufficient current from the existing floating supply. The voltage from the current sensing resistor or shunt (Rsense) is applied to the input of the HCPL-7860/ HCPL-786J (U2) through an RC anti-aliasing filter (R2 and C2). And finally, the output clock and data of the isolated modulator are connected to the digital interface IC. Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. The power supply for the isolated modulator is most often obtained from the same supply used to power the power transistor gate drive circuit. If a dedicated supply is required, in many cases it is possible to add an additional winding on an existing transformer. Otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency DC-DC converter. An inexpensive 78L05 threeterminal regulator can also be used to reduce the floating supply voltage to 5 V. To help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a lowpass filter with the regulator’s input bypass capacitor. FLOATING POSITIVE SUPPLY As shown in Figure 17, 0.1 µF bypass capacitors (C1 and C3) should be located as close as possible to the input and output power-supply pins of the isolated modulator (U2). The bypass capacitors are required because of the highspeed digital nature of the signals inside the isolated modulator. A 0.01 µF bypass capacitor (C2) is also recommended at the input due to the switched-capacitor nature of the input circuit. The input bypass capacitor also forms part of the anti-aliasing filter, which is recommended to prevent high-frequency noise from aliasing down to lower frequencies and interfering with the input signal. +5V HV+ GATE DRIVE CIRCUIT R1 D1 5.1 V C1 0.1 µF R2 39 Ω MOTOR + C2 0.01 µF R SENSE CCLK V DD CLAT CHAN V DD1 V DD2 CDAT SCLK V IN+ MCLK MCLK1 SDAT V IN- MDAT MDAT1 CS GND1 GND2 MCLK2 THR1 HCPL-7860/ HCPL-786J C3 0.1 µF MDAT2 GND OVR1 RESET HCPL-0872 HV- Figure 17. Recommended Application Circuit. 14 TO CONTROL CIRCUIT PC Board Layout Shunt Resistors The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). Choosing a particular value for the shunt is usually a compromise between minimizing power dissipation and maximizing accuracy. Smaller shunt resistances decrease power dissipation, while larger shunt resistances can improve circuit accuracy by utilizing the full input range of the isolated modulator. The first step in 15 selecting a shunt is determining how much current the shunt will be sensing. The graph in Figure 18 shows the RMS current in each phase of a three-phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. The maximum value of the shunt is determined by the current being measured and the maximum recommended input voltage of the isolated modulator. The maximum shunt resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the shunt should see during normal operation. For example, if a motor will have a maximum RMS current of 10 A and can experience up to 50% overloads during normal operation, then the peak current is 21.1 A (= 10 x 1.414 x 1.5). Assuming a maximum input voltage of 200 mV, the maximum value of shunt resistance in this case would be about 10 mΩ. 40 MOTOR OUTPUT POWER - HORSEPOWER The design of the printed circuit board (PCB) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. In addition, the layout of the PCB can also affect the isolation transient immunity (CMR) of the isolated modulator, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the PC board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the PC board does not pass directly below or extend much wider than the body of the isolated modulator. 440 380 220 120 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 MOTOR PHASE CURRENT - A (rms) Figure 18. Motor Output Horsepower vs. Motor Phase Current and Supply Voltage. The maximum average power dissipation in the shunt can also be easily calculated by multiplying the shunt resistance times the square of the maximum RMS current, which is about 1 W in the previous example. If the power dissipation in the shunt is too high, the resistance of the shunt can be decreased below the maximum value to decrease power dissipation. The minimum value of the shunt is limited by precision and accuracy requirements of the design. As the shunt value is reduced, the output voltage across the shunt is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. The selected value of the shunt will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specific design. When sensing currents large enough to cause significant heating of the shunt, the temperature coefficient (tempco) of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. The effect increases as the shunt-to-ambient thermal resistance increases. This effect can be minimized either by reducing the thermal resistance of the shunt or by using a shunt with a lower tempco. Lowering the thermal resistance can be accomplished by repositioning the shunt on the PC board, by using larger PC board traces to carry away more heat, or by using a heat sink. For a two-terminal shunt, as the value of shunt resistance decreases, the resistance of the leads becomes a significant percentage of the total shunt resistance. This has two primary effects on shunt accuracy. First, the effective resistance of the shunt can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the lead during assembly (these issues will be discussed in more detail shortly). Second, the leads are typically made from a material such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco for the shunt overall. Both of these effects are eliminated when a fourterminal shunt is used. A fourterminal shunt has two additional terminals that are Kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. Because of the Kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. Several four-terminal shunts from Isotek (Isabellenhütte) suitable for sensing currents in motor drives up to 71 Arms (71 hp or 53 kW) are shown in Table 3; the maximum current and motor power range for each of the PBV series shunts are indicated. For shunt resistances from 50 mΩ down to 10 mΩ, the maximum current is limited by the input voltage range of the isolated modulator. For the 5 mΩ and 2 mΩ shunts, a heat sink may be required due to the increased power dissipation at higher currents. When laying out a PC board for the shunts, a couple of points should be kept in mind. The Kelvin connections to the shunt should be brought together under the body of the shunt and then run very close to each other to the input of the isolated modulator; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. If the shunt is not located on the same PC board as the isolated modulator circuit, a tightly twisted pair of wires can accomplish the same thing. Also, multiple layers of the PC board can be used to increase current carrying capacity. Numerous plated-through vias should surround each nonKelvin terminal of the shunt to help distribute the current between the layers of the PC board. The PC board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 A. Making the current carrying traces on the PC board fairly large can also improve the shunt’s power dissipation capability by acting as a heat sink. Liberal use of vias where the load current enters and exits the PC board is also recommended. Table 3. Isotek (Isabellenhütte) Four-Terminal Shunt Summary. Shunt Resistance Tol. Maximum RMS Current mΩ % A hp kW PBV-R050-0.5 50 0.5 3 0.8 - 3 0.6 - 2 PBV-R020-0.5 20 0.5 7 2-7 0.6 - 2 PBV-R010-0.5 10 0.5 14 4 - 14 3 - 10 PBV-R005-0.5 5 0.5 25  7 - 25 [8 - 28] 5 - 19 [6 - 21] PBV-R002-0.5 2 0.5 39  Shunt Resistor Part Number Note: Values in brackets are with a heatsink for the shunt. 16 Motor Power Range 120 Vac-440 Vac 11 - 39 [19 - 71] 8 - 29 [14 - 53] Shunt Connections The recommended method for connecting the isolated modulator to the shunt resistor is shown in Figure 17. VIN+ (pin 2 of the HPCL-7860/ HCPL-786J) is connected to the positive terminal of the shunt resistor, while VIN- (pin 3) is shorted to GND1 with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of wires or PC board traces to connect the isolated modulator circuit to the shunt resistor. By referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the shunt are seen as a common-mode signal and will not interfere with the currentsense signal. This is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are relatively large compared to the small voltages that are being measured across the current shunt. If the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from GND1 of the isolated modulator to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. The only direct connection between the isolated modulator circuit and the gate drive circuit should be the positive power supply line. 17 In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting VIN+ and VIN- directly across the shunt resistor with two conductors, and connecting GND1 to the shunt resistor with a third conductor for the power-supply return path, as shown in Figure 19. When connected this way, both input pins should be bypassed. To minimize electromagnetic interference of the sense signal, all of the conductors (whether two or three are used) connecting the isolated modulator to the sense resistor should be either twisted pair wire or closely spaced traces on a PC board. The 39 Ω resistor in series with the input lead (R2) forms a lowpass anti-aliasing filter with the 0.01 µF input bypass capacitor (C2) with a 400 kHz bandwidth. The resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the inductance of wires or traces connecting the two. Undamped ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device. FLOATING POSITIVE SUPPLY HV+ GATE DRIVE CIRCUIT R1 D1 5.1 V R2a 39 Ω C1 0.1 µF R2b 39 Ω MOTOR + C2a C2b 0.01 µF 0.01 µF R SENSE HV- Figure 19. Schematic for Three Conductor Shunt Connection. V DD1 V DD2 V IN+ MCLK V IN- MDAT GND1 GND2 HCPL-7860/ HCPL-786J Voltage Sensing The HCPL-7860/HCPL-786J Isolated Modulator can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 kΩ) so that the input www.agilent.com/ semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright © 2004 Agilent Technologies, Inc. Obsolete 5989-1485EN December 21, 2004 5989-2166EN resistance (280 kΩ) and input bias current (1 µA) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 39 Ω series damping resistor is not (the resistance of the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. To obtain higher bandwidth, the input bypass capacitor (C2) can be reduced, but it should not be reduced much below 1000 pF to maintain adequate input bypassing of the isolated modulator.