LSI/CSI UL ® LS7766 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 October 2007 32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER GENERAL DESCRIPTION: The LS7766 consists of two identical modules of 32-bit programmable up/down counters (CNTR) with direct interface to incremental encoders. The modules can be configured to operate as quadrature-clock counters or non-quadrature up/down counters. In both quadrature and non-quadrature modes, the modules can be further configured into free-running, non-recycle, modulo-n and range-limit count modes. The mode configuration is made via two octal read/write addressable mode control registers, MCR0 and MCR1. Data can be written into a 32-bit input data register (IDR), organized in addressable Word segments using the hex IO bus or in byte segments using the octal IO Bus. The IDR can be used to store target encoder positions and compared with the CNTR for generating marker flags when the CNTR reaches the target value. A 32-bit digital comparator is included for monitoring the equality of the CNTR to the IDR. Snapshots of the CNTR value can be stored in a read-addressable 32-bit output data register (ODR). The ODR can be read in Word segments or byte segments in accordance with the selected bus width. Data transfers among the registers and various register reset functions are performed by means of a write-addressable octal transfer control register (TCR). A read-addressable octal status register (STR), stores the count related status information such as CNTR overflow, underflow, count direction, etc. 7766-102307-1 1 RS1 2 RS0 48 V DD 47 PCKO 3 46 PCKI NC 4 45 RD/ DB0 5 44 WR/ DB1 6 43 CS/ DB2 7 42 NC DB3 8 41 x1B DB4 9 40 x1A DB5 10 39 x1INDX/ 38 x1FLGa 37 x1FLGb 36 x1CKO LS7766DH LS7766DH-TS; LS7766DO, LS7766DO-S, LS7766DO-TS; LS7766SO, LS7766SO-S, LS7766SO-TS; LS7766SH-TS P/N = DIP; P/N-S = SOIC; P/N-TS = TSSOP RS2 LSI FEATURES: • Direct interface with Incremental Encoders • Read/write registers for count and I/O modes. Count modes include: non-quadrature (Up/Down), quadrature (x1, x2, x4.) free-run, non-recycle, modulo-n and range limit • Programmable IOs for Index and Marker Flags • Separate mode-control registers for each axis • 40MHz count frequency at 5V; 20MHz count frequency at 3V • Sets of 32-bit counters, input registers, output registers, comparators and octal Status registers for each axis • Digital filtering of the input quadrature clocks for noise immumity. • Pin selectable 3-state Hex / Octal bus • 3V to 5.5V operating voltage range • Available in four different configurations identified by the following suffixes: DH = Dual-axis with pin selectable Hex/Octal IO Bus DO = Dual-axis Octal IO Bus SH = Single-axis pin selectable Hex/Octal IO Bus SO = Single axis Octal IO Bus DB6 11 DB7 12 DB8 13 DB9 14 35 V SS DB10 15 34 IO16/ DB11 16 33 x0/_x1 DB12 17 32 x0CKO DB13 18 31 x0FLGb DB14 19 30 x0FLGa DB15 20 29 NC NC 21 28 x0INDX/ NC 22 27 x0A NC 23 26 x0B V SS 24 25 NC Pin Assignment - Top View 27 x1FLGa CS/ 3 26 x1FLGb WR/ 4 25 x0/_x1 RD/ 5 24 x0FLGb PCKI 6 23 x0FLGa V DD 7 22 x0INDX/ RS2 8 21 x0A RS1 9 20 x0B RS0 10 19 V SS DB0 11 18 DB7 DB1 12 17 DB6 DB2 13 16 DB5 DB3 14 15 DB4 LS7766DO RS2 1 RS1 38 V DD 2 37 PCKO RS0 3 36 PCKI DB0 4 35 RD/ DB1 5 34 NC DB2 6 33 WR/ DB3 7 32 CS/ DB4 8 31 NC DB5 9 30 NC DB6 10 29 NC 28 IO16/ 27 NC 26 CKO DB7 11 Pin Assignment - Top View DB8 12 DB9 13 LS7766SH 2 x1B LSI x1INDX/ 1 LSI 28 x1A DB10 14 25 FLGb V DD DB11 15 24 FLGa 23 PCKO DB12 16 23 INDX/ 3 22 PCKI DB13 17 22 A DB0 4 21 RD/ DB14 18 21 B DB1 5 20 WR/ DB15 19 20 V SS DB2 6 19 CS/ DB3 7 18 CKO DB4 8 17 FLGb DB5 9 16 FLGa DB6 10 15 INDX/ DB7 11 14 A V SS 12 13 B 1 RS1 2 RS0 LSI 24 RS2 LS7766SO Pin Assignment - Top View 7766-110806-2 Pin Assignment - Top View REGISTER DESCRIPTION: Following is a list of the hardware registers for the single-axis device. For the dual axis device, these registers are duplicated for the second axis. IDR The IDR is a 32-bit data register directly addressable for write. In the octal bus-configuration, the input data is written in byte segments of byte0 (IDR0), byte1 (IDR1), byte2 (IDR2) and byte3 (IDR3). In the hex busconfiguration the data is written in word segments of word0 (IDR1:IDR0) and word1 (IDR3:IDR20). B31------------------------------------------------------------------- B0 IDR: IDR3 IDR2 IDR1 IDR0 B7------------B0 B7-----------B0 B7-----------B0 B7---------B0 -----byte3------ -----byte2----- -----byte1----- -----byte0------------------- word1---------------- --------------- word0 ------------ The IDR serves as the input portal for the counter (CNTR) since the CNTR is not directly addressable for either read or write. In order to preset the CNTR to any desired value the data is first written into the IDR and then transferred to the CNTR. In mod-n and range-limit count modes the IDR serves as the repository for the division factor n and the count range-limit, respectively. The IDR can also be used to hold a target position data for comparing with the running CNTR. A compare equality flag is generated at IDR = CNTR to signal the event of arriving at the target. CNTR: The CNTR is a 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at A and B inputs or alternatively, in nonquadrature mode, pulses applied at the A input. The CNTR is not directly accessible for read or write; instead it can be preloaded with data from the IDR or it can port its own data out to the ODR which in turn can be accessed by read operation. In both quadrature and nonquadrature modes, the CNTR can be further configured into either free-running or single-cycle or mod-n or range-limit mode. In quadrature mode, the count resolution is programmable to be x1 or x2 or x4 of the A quad B cycles. ODR: The ODR is a 32-bit data register directly addressable for read. In the octal bus-configuration, the output data is read in byte segments of byte0 (ODR0), byte1 (ODR1), byte2 (ODR2), and byte3 (ODR3). In the hex busconfiguration the data is read in word segments of word0 (ODR1:ODR0) and word1 (ODR3:ODR2). B31------------------------------------------------------------------- B0 ODR: ODR3 ODR2 ODR1 ODR0 B7------------B0 B7-----------B0 B7-----------B0 B7---------B0 -----byte3------ -----byte2----- -----byte1----- -----byte0------------------- word1---------------- --------------- word0 -----------7766-042407-3 STR: The STR is an 8-bit status register indicating count related status. STR: CY BW CMP IDX CEN 0 B7 B6 B5 B4 B3 U/D B2 B1 S B0 An individual STR bit is set to 1 when the bit related event has taken place. The STR is cleared to 0 at power-up. The STR can also be cleared through the control register TCR with the exception of bit_1(U/D) and bit3_(CEN). These two STR bits always indicate the instantaneous status of the count_direction and count_enable assertion/de-assertion. The STR bits are described below: B7 (CY): Carry; set by CNTR overflow B6 (BW): Borrow; set by CNTR underflow B5 (CMP): Set when CNTR = PR B4 (IDX): Set when INDX input is at active level B3 (CEN): Set when counting is enabled, reset when counting is disabled B2 (0): Always 0 B1 (U/D): Set when counting up, reset when counting down B0 (S): Sign of count value; set when negative, reset when positive TCR: The TCR is a write only register, which when written into, generates transient signals to perform load and reset operations as described below: TCR: B7 B6 B5 B4 B3 B2 B1 B0 B0 = 0: Nop = 1: Reset CNTR to 0. (Should not be combined with load_CNTR operation). B1 = 0: Nop = 1: Load CNTR from IDR. Affects all 32 bits. (Should not be combined with reset_CNTR operation) B2 = 0: Nop = 1: Load ODR from CNTR. Affects all 32 bits. B3 = 0: Nop = 1: Reset STR. Affects status bits for carry, borrow, compare and index. Status bits corresponding to count_enable, count direction and sign are not affected B4 = 0: Nop. 1: Master reset. Resets MCR0, MCR1, IDR, ODR, STR B5 = 0: Nop 1: Set sign bit (STR bit0) B6 = 0: Nop 1: Reset sign bit (STR bit0) B7 = x: Not used. MCR0 : The MCR0 is an 8-bit read/write register which configures the counting modes and the index input functionality. Upon power-up, the MCR0 is cleared to zero. MCR0: B7 B6 B5 B4 B3 B2 B1 B0 B1B0 = 00: = 01: = 10: = 11: B3B2 = 00: = 01: = 10: Non-quadrature count mode (A = clock, B = direction). x1 quadrature count mode (one count per quadrature cycle). x2 quadrature count mode (two counts per quadrature cycle). x4 quadrature count mode (four counts per quadrature cycle). Free-running count mode. Single-cycle count mode (CNTR disabled with carry and borrow, re-enabled with reset or load) Range-limit count mode (up and down count ranges are limited between IDR and zero, respectively. Counting freezes at these limits but resumes when the direction is reversed) = 11: Modulo-n count mode (input count clock frequency is divided by a factor of [n+1], where n = IDR. In up direction, the CNTR is cleared to 0 at CNTR = IDR and up count continues. In down direction, the CNTR is preset to the value of IDR at CNTR = 0 and down count continues. A mod-n rollover marker pulse is generated at each limit at the FLGa output). B5B4 = 00: Disable INDX/ input. = 01: Configure INDX/ input as the load_CNTR input (transfers IDR to CNTR). = 10: Configure INDX/ as the reset _CNTR input (clears CNTR to 0). = 11: Configure INDX/ as the load_ODR input (transfers CNTR to ODR). B6 = 0: Asynchronous index. = 1: Synchronous index (overridden in non-quadrature mode). B7 = 0: Input filter clock (PCK) division factor = 1. Filter clock frequency = fPCK. = 1: Input filter clock division factor = 2. Filter clock frequency = fPCK/2. MCR1: The MCR1 is an 8-bit read/write register which configures the FLGa and FLGb output functionality. In addition, the MCR1 can be used to enable/disable counting.Upon power-up, the MCR1 is cleared to zero: MCR1: B7 B6 B5 B4 B3 B2 B1 B0 B0 B1 B2 = 1: Enable Carry on FLGa (flags CNTR overflow; latched or unlatched logic low on carry). = 1: Enable Borrow on FLGa (flags CNTR underflow, latched or unlatched logic low on borrow). = 1: Enable Compare on FLGa (In free-running count mode a latched or unlatched logic low is generated in both up and down count directions at CNTR = IDR. In contrast, in range-limit and mod-n count modes a latched or unlatched low is generated at CNTR = IDR in the up-count direction only. B3 = 1: Enable index on FLGa (flags index, latched or unlatched logic low when INDX input is at active level) B5B4 = 00: FLGb disabled (fixed high) = 01: FLGb = Sign, high for negative signifying CNTR underflow, low for positive. = 10: FLGb = Up/Down count direction, high in count-up, low in count-down. B6 = 0: Enable counting. = 1: Disable counting. B7 = 0: FLGa is latched. = 1: FLGa is non-latched and instantaneous. NOTE: Carry, Borrow, Compare and Index can all be simultaneously enabled on FLGa. 7766-111406-4 I/O PINS: The following is a description of the input/out pins. RS0, RS1, RS2 Inputs. These three inputs select the hardware registers for read/write access according to Table 1 and Table 2. Table 1 applies to Octal bus configuration. Table 2 applies to Hex bus configuration. TABLE 1 CS/ 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS2 x 0 0 0 0 1 1 1 0 0 0 0 1 1 1 RS1 x 0 0 1 1 0 0 1 0 0 1 1 0 0 1 RS0 x 0 1 0 1 0 1 0 0 1 0 1 0 1 0 RD/ x 0 0 0 0 0 0 0 1 1 1 1 1 1 1 WR/ x 1 1 1 1 1 1 1 0 0 0 0 0 0 0 DATABUS SELECTED REGISTER REGISTER MAP none none MCR0 DBL MCR1 DBL ODR0 DBL ODR1 DBL ODR2 DBL ODR3 DBL STR DBL MCR0 DBL MCR1 DBL IDR0 DBL IDR1 DBL IDR2 DBL IDR3 DBL TCR DBL OPERATION none READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE WRITE WRITE TABLE 2 CS/ 1 0 0 0 0 0 0 0 0 RS2 x 0 0 1 1 0 0 1 1 RS1 x 0 1 0 1 0 1 0 1 RS0 x 0 0 0 0 0 0 0 0 RD/ x 0 0 0 0 1 1 1 1 WR/ x 1 1 1 1 0 0 0 0 DATABUS SELECTED REGISTER REGISTER MAP OPERATION none none none [MCR1:MCR0] [DBH:DBL] READ [ODR1:ODR0] [DBH:DBL] READ [ODR3:ODR2] [DBH:DBL] READ [STR] [DBL] READ [MCR1:MCR0] [DBH:DBL] WRITE [IDR1:IDR0] [DBH:DBL] WRITE [IDR3:IDR2] [DBH:DBL] WRITE [TCR] [DBL] WRITE Note 1. x indicates don’t care case. Note 2. DBL stands for DB <7:0> ; DBH stands for DB <15:8>. 7766-111406-5 x0/_x1 Input. The x0/_x1 input selects between axis-0 and axis-1 for Read and Write operations. A low at this input selects axis-0 while a high selects axis-1. RD/ Input. A low on RD/ input accesses an addressed register(s) for read and places the data on the databus, DB<15:0> in accordance with Table 1 and Table 2. CS/ Input. A low on the CS/ input enables the chip for read or write operation. When the CS/ input is high, read and write operations are disabled and the databus, DB<15:0> is placed in a high impedance state. WR/ Input. A low pulse on the WR/ input writes the data on the databus, DB<15:0> into the addressed register according to Table 1 and Table 2. The write operation is completed at the trailing edge of the WR/ pulse. PCKI, PCKO. Input, Output. A clock applied at PCKI input is used for validating the logic states of the A and B quadrature clocks and the INDX/ input. Alternatively, a crystal oscillator connected between PCKI and PCKO can be used to generate the filter clock. The PCK input frequency, fPCK is divided down by a factor of 1 or 2 according to bit7 of MCR0. The resultant clock is used to sample the logic levels of the A, the B and the INDX inputs. If a logic level at any of these inputs remains stable for a minimum of two filter clock periods, it is validated as a correct logic state. The PCKI input is common to both axes, but the filter clock frequency for any axis is set by its associated MCR0 register. In non-quadrature mode, no filter clock is used and the PCKI input should be connected to either VDD or GND. x0A, x0B Inputs. These are the A and B count inputs in axis-0. These inputs can be configured to function either in quadrature mode or in non-quadrature mode. The configuration is made through MCR0. In quadrature mode, A and B clocks are 90 degrees out of phase such as the output from an Incremental Encoder. When A leads B in phase, the CNTR counts up and when B leads A in phase, the CNTR counts down. In non-quadrature mode, A serves as the count input while B controls the count direction. When B is high, positive transitions at the A input causes the CNTR to count up. Conversely, when B is low, the positive transition at the A input causes the CNTR to count down. In quadrature mode, A and B inputs are sampled by an internal filter clock generated from the PCKI input. In non-quadrature mode, A and B inputs are not sampled and the count clocks are applied to the CNTR, bypassing the filter circuit. 7766-110806-6 x1A , x1B: These are the A and B inputs corresponding to axis-1, . Functionally, they are identical with the A and B inputs of axis-0. x0INDX/ Input. The INDX/ input in axis-0. The INDX/ input can be configured to function as load_CNTR or reset_CNTR or load_ODR input via MCR0. In quadrature mode the INDX/ input can be configured to operate in either synchronous or asynchronous mode. In the synchronous mode the INDX/ input is sampled with the same filter clock used for sampling the A and the B inputs and must satisfy the phase relationship with A and B in which INDX/ is at the active level during a minimum of a quarter cycle of both A and B high or both A and B low. The active level of the INDX/ input is logic low. In non-quadrature mode the INDX/ input is unconditionally set to the asynchronous mode. In the asynchronous mode the INDX/ input is not sampled and can be applied in any phase relationship with respect to the A and B inputs. The INDX/ input can be either enabled or disabled in both quadrature and non-quadrature modes. x1INDX/. The INDX/ input corresponding to axes-1. Functionally, it is identical with the INDX/ input of axis-0. IO16/ Input. When low, hex databus configuration is invoked in accordance with Table 2. When high, octal databus configuration is invoked in accordance with Table 1. This input has an internal pull-up. x0FLGa Output. The FLGa output in axis-0. The FLGa output is configured by MCR1 register to function as Carry and/or Borrow and/or Compare and/or Index flag. A Carry flag is generated when the CNTR overflows, a Borrow flag is generated when the CNTR underflows, a Compare flag is generated by the condition, CNTR = IDR and Index flag is generated when Index input is at active level. The FLGa output can be configured to produce outputs in either latched mode or instantaneous mode. In the latched mode when the selected event of Carry or Borrow or Compare or index has taken place, FLGa switches low and remains low until the status register, STR is cleared. In the instantaneous mode, a negative pulse is generated instantaneously when the event takes place. The FLGa output can be disabled to remain at a fixed logic high. x1FLGa Output. The FLGa output corresponding to axes-1. Functionally, it is identical with the FLGa output of axis-0. x0FLGb Output. The FLGb output in axis-0. The FLGb output is configured by MCR1 to function as either Sign or Up/Down count direction indicator. When configured as Sign, the FLGb output remains high when CNTR is in an underflow state (caused by down counts at or below zero), indicating a negative number. When the CNTR counts up past zero, FLGb switches low, indicating a positive number. x1FLGb Output. The FLGb output of axis-1. Functionally, it is identical with the FLGb output of axis-0. x0CKO Output. Axis-0 count clock output. In nonquadrature mode, the CKO output is identical with the input-A clock. In quadrature mode, CKO is derived from the filtered and decoded quadrature clocks applied at the A and B inputs. In either mode CKO is a true representative of the internal count clock. When configured as Up/Down indicatior, a high at the FLGb indicates that the current count direction is up (incremental) whereas a low indicates that the direction is down or decremental. x1CKO Output. Axis-1 count clock output. Functionally, it is identical with the CKO output of axis-0. The FLGb output can be disabled to remain at a fixed logic high. GND. Supply voltage. Negative terminal. VDD. Supply voltage. Positive terminal. The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7766-062207-7 Absolute Maximum Ratings: Parameter Voltage at any input Supply Voltage Operating Temperature Storage Temperature Symbol VIN VDD TA TSTG Values VSS - 0.3 to VDD + 0.3 +7.0 -25 to +80 -65 to +150 Unit V V oC oC DC Electrical Characteristics. (TA = -25oC to +80oC, VDD = 3V to 5.5V) Parameter Supply Voltage Supply Current Input Logic Low Input Logic High Input Leakage Current Data Bus Leakage Current Data Bus Source Current Data Bus Sink Current FLGa, FLGb, INT/ Source FLGa, FLGb, INT/ Sink Symbol VDD IDD VIL VIH IILK IDLK IDBH IDBL IOSRC IOSNK Min. Value 3.0 0.5VDD 2.0 -6.0 1.0 -6.0 Max.Value 5.5 800 0.15VDD 30 60 - Unit V µA V V nA nA mA mA mA mA Remarks All clocks off Data bus off VO = VDD - 0.5V, VDD = 5V VO = 0.5V, VDD = 5V VO = VDD - 0.5V, VDD = 5V VO = 0.5V, VDD = 5V Transient Characteristics. (TA = -25o to +80oC, VDD = 3V to 5.5V) Parameter Read Cycle (See Fig. 2) RD/ Pulse Width CS/ Set-up Time CS/ Hold Time RS<2:0> Set-up Time RS<2:0> Hold Time x0/_x1 Set-up Time x0/_x1 Hold Time DB<15:0> AccessTime Min. Value Max.Value tr1 tr2 tr3 tr4 tr5 tr6 tr7 tr8 80 80 0 80 10 80 10 80 - ns ns ns ns ns ns ns ns DB<15:0> Release Time tr9 - 35 ns Back to Back Read delay tr10 10 - ns Access starts when both RD/ and CS/ are low. Release starts when either RD/ or CS/ is terminated. - Write Cycle (See Fig. 3) WR/ Pulse Width CS/ Set-up Time CS/ Hold Time RS<2:0> Set-up Time RS<2:0> Hold Time x0/_x1 Set-up Time x0/_x1 Hold Time DB<15:0> Set-up Time DB<15:0> Hold Time Back to Back Write Delay tW1 tW2 tW3 tW4 tW5 tW6 tW7 tW8 tW9 tW10 45 45 0 45 10 45 10 45 10 90 - ns ns ns ns ns ns ns ns ns ns - 7766-110806-8 Symbol Unit Remarks For VDD = 3.3V ±10% Parameter Symbol Quadrature Mode (See Fig. 4 - 6) PCKI High Pulse Width t1 PCKI Low Pulse Width t2 PCKI Frequency fpCK Filter Clock (ff) Period t3 t3 Max.Value Unit Remarks 24 24 50 100 20 - ns ns MHz ns ns t3 = t1+ t2, MDR0 <7> = 0 t3 = t1+ t2, MDR0 <7> = 1 52 105 4t3 25 20 4.5 5t3 - MHz ns ns MHz ns ff = 1/t3 t4 > t3 t5 > 2t3 fQA = fQB < 1/4t3 tQ2 = t3/2 Filter Clock frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1, x2, x4 Count Clock Pulse Width Quadrature Clock to FLGa delay Quadrature Clock to FLGb delay INDX/ Input Pulse Width INDX/ set-up time INDX/ hold time FLGa Output Width tfda 4.5t3 5.5t3 ns - tfdb tid tis tih tfw 3t3 60 10 10 50 4t3 - ns ns ns ns ns tid > t4 tfw ≈ t4 Non-Quadrature Mode (See Fig. 7 - 8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock Frequency Clock to FLGa Out Delay FLGa Out Pulse Width INDX/ Pulse Width t6 t7 t8s t8 fA t9 t10 t11 24 24 24 20 24 30 20 40 - ns ns ns ns MHz ns ns ns fA = (1/(t6 + t7)) t10 = t7 - For VDD = 5V ±10% Parameter Quadrature Mode (See Fig. 4 - 6) PCK High Pulse Width PCK Low Pulse Width PCK frequency Filter Clock (ff) period ff t4 t5 fQA, fQB tQ1 tQ2 Min. Value Symbol Min. Value Max.Value Unit Remarks t1 t2 fpCK t3 t3 12 12 25 50 40 - ns ns MHz ns ns t3 = t1+ t2, MDR0 <7> = 0 t3 = t1+ t2, MDR0 <7> = 1 ff t4 t5 fQA, fQB tQ1 tQ2 26 52 4t3 12 40 9.6 5t3 - MHz ns ns MHz ns t4 > t3 t5 > 2t3 fQA = fQB < 1/4t3 tQ2 = t3/2 Filter Clock frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1, x2, x4 Count Clock Pulse Width Quadrature Clock to FLGa delay Quadrature Clock to FLGb delay INDX/ Input Pulse Width INDX/ set-up time INDX/ hold time FLGa Output Width tfda 4.5t3 5.5t3 ns - tfdb tid tis tih tfw 3t3 32 5 5 24 4t3 - ns ns ns ns ns tid > t4 tfw ≈ t4 Non-Quadrature Mode (See Fig. 7 - 8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock frequency Clock to FLGa Out Delay FLGa Out Pulse Width INDX/ Pulse Width t6 t7 t8 t8 fA t9 t10 t11 12 12 12 10 12 15 40 20 - ns ns ns ns MHz ns ns ns fA = (1/(t6 + t7)) t10 = t7 - 7766-110806-9 tr10 tr1 RD/ tr3 tr2 CS/ tr4 tr5 tr6 tr7 RS x0/_x1 tr8 tr9 DB VALID DATA VALID DATA FIGURE 2. READ CYCLE tw10 tw1 WR/ tw2 tw3 CS/ tw4 tw5 tw6 tw7 tw8 tw9 RS x0/_x1 DB INPUT DATA INPUT DATA FIGURE 3. WRITE CYCLE t1 t2 PCKI t3 f f (Note 3) t3 (MCR0 <7> = 0) f f (Note 3) t5 (MCR0 <7> = 1) A B INDX/ t4 t5 t4 t4 tih tis Note 1 tid Note 1. Synchronous mode index coincident with both A and B high. Note 2. Synchronous mode index coincident with both A and B low. Note 3. fF is the internal effective filter clock. FIGURE 4. PCKI, A, B AND INDX/ 7766-110806-10 t4 tis tih Note 2 DOWN UP tQ1 A B CKO (x4 Mode) CKO (x2 Mode) tQ2 CKO (x1 Mode) NOTE. CKO is identical with internal count clock. FIGURE 5. A/B QUADRATURE CLOCKS vs OUTPUT CLOCK, CKO DOWN UP A B CKO (x4 Mode) CNTR FFFFFC FFFFFD FFFFFE FFFFFF 000000 t fda 000002 000001 000000 FFFFFF tfw CMP tfdb FLGb (up/dn) FLGb (sign) BW negative positive NOTE. FLGa is in non-latched mode. FIGURE 6. QUADRATURE CLOCKS vs FLGa, FLGb OUTPUTS 7766-042407-11 FFFFFE (SHOWN WITH PR=000OO1) CY FLGa 000001 FFFFFD DOWN UP DOWN B t6 t8H t8S t7 A FIGURE 7. COUNT (A) AND DIRECTION (B) INPUTS IN NON-QUADRATURE MODE B A (Shown with PR= 2) CNTR FFFFFFC FFFFFFD FFFFFFE FFFFFFF 0 2 1 0 FFFFFFF t9 FLGa CY t10 CNTR DISABLED CNTR DISABLED t11 INDX (LOAD CNTR) CNTR ENABLED FIGURE 8. SINGLE-CYCLE, NON-QUADRATURE DOWN UP B A (Shown with PR = 3) CNTR 0 1 2 FLGa 3 0 1 2 1 3 0 2 1 BW BW BW CMP FIGURE 9. MODULO-N, NON-QUADRATURE B DOWN UP A (Shown with PR = 3) CNTR 000000 000001 000002 FLGa 000003 CMP CMP 000002 000001 CMP CMP 000000 BW FIGURE 10. RANGE-LIMIT, NON-QUADRATURE 7766-110806-12 0 CY, BW, CMP, INDX, SIGN, UP/DOWN READ STR (8) OUT-BUS<15:0> CLOCK BUFFER CK0 MUX FLAG-MASKS FLGa AND/OR/BUF FLGb IN-BUS<15:0> WRITE READ MCR1(8) IDR3(8) MCR0(8) IDR2(8) IDR1(8) IDR0(8) TCR(8) LD/SET/RESET OUT-BUS<15:0> MODES, FLAG-MASKS C O M P MODE LOGIC CLOCK A B INDX/ PCKI PCK0 RD/ WR/ CS/ COUNT CLOCK & INDEX GENERATOR WRITE ODR3(8) ODR2(8) ODR1(8) REGISTER SELECT LOGIC OUTPUT 3-STATE BUFFER WRITE IN-BUS<15:0> FIGURE 11. LS7766 BLOCK DIAGRAM FOR SINGLE-AXIS 7766-110806-13 ODR0(8) READ INPUT BUFFER CY, BW, SIGN OUT-BUS<15:0> READ IO16/ DB<15:0> MARKER LOGIC READ x0/_x1 RS<2:0> CMP INDX OSC READ/WRITE & AXIS SELECT LOGIC CNTR (32) ISA / EISA BUS IOW/ WR/ IOR/ RD/ D<15:0 > DB<15:0> PC LS7766 IO16/ A<4> A<3> A< 4:1 > A< 7:5> AEN x0/_x1 RS2 A<2> RS1 A<1> RS0 ADDRESS DECODE CS/ FIGURE 12. LS7766 TO ISA / EISA INTERFACE with HEX BUS R/W RD/ LDS 15pF PCKI WR/ D<7> D<6> D<5> DTACK/ D<4> D<3> MC68HC000 D<2> D<7:0> D<7:0> D<1> D<0> DB7 DB6 1MΩ PCKO DB5 DB4 DB3 DB2 DB1 DB0 LS7766 A2 A3 - A 0 A1 A0 A3 A<23:20> A<23:A0 > ADDRESS DECODE RS2 RS1 RS0 x0/_x1 CS/ FIGURE 13. LS7766 TO MC68HC000 INTERFACE with OCTAL BUS 7766-111406-14 40MHz 15pF