MICRON MT29F2G16AADWPDTR

Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Features
NAND Flash Memory
MT29F2G08AAD, MT29F2G16AAD,
MT29F2G08ABD, MT29F2G16ABD
Features
Figure 1:
• Open NAND Flash Interface (ONFI) 1.0-compliant
• Single-level cell (SLC) technology
• Organization
– Page size:
• x8: 2,112 bytes (2,048 + 64 bytes)
• x16: 1,056 words (1,024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 2Gb: 2,048 blocks
• READ performance
– Random READ: 25µs
– Sequential READ: 25ns (3.3V)
– Sequential READ: 35ns (1.8V)
• WRITE performance
– PROGRAM PAGE: 220µs (TYP, 3.3V)
– PROGRAM PAGE: 300µs (TYP, 1.8V)
– BLOCK ERASE: 500µs (TYP)
• Data retention: 10 years
• Endurance: 100,000 PROGRAM/ERASE cycles
• First block (block address 00h) guaranteed to be
valid with ECC when shipped from factory1
• Industry-standard basic NAND Flash command set
• Advanced command set:
– PROGRAM PAGE CACHE MODE
– PAGE READ CACHE MODE
– One-time programmable (OTP) commands
– BLOCK LOCK (1.8V only)
– PROGRAMMABLE DRIVE STRENGTH
– READ UNIQUE ID
• Operation status byte provides a software method of
detecting:
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: write protect entire device
• RESET required as first command after power-up
• INTERNAL DATA MOVE operations supported
• Alternate method of device initialization
(Nand_Init) after power up4 (Contact Factory)
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59a__1.fm - Rev. A 8/08 EN
63-Ball VFBGA
Options
• Density2: 2Gb (single die)
• Device width: x8, x16
• Configuration:
# of die
# of CE# # of R/B#
I/O
1
1
1
Common
• VCC: 2.7–3.6V
• VCC: 1.65–1.95V
• Package
– 48-pin TSOP type I CPL3 (lead-free plating, 3.3V
only)
– 63-ball VFBGA (lead-free, 1.8V only)
• Operating temperature:
– Commercial (0°C to +70°C)
– Extended (–40°C to +85°C)
1. See “Error Management” on page 61.
2. For part numbering and markings, see
Figure 2 on page 2 and Figure 3 on page 3.
3. CPL = center parting line
4. Available only in 1.8V VFBGA package.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Part Numbering Information
Part Numbering Information
Micron® NAND Flash devices are available in several different configurations and
densities (see Figure 2).
Figure 2:
Part Number Chart (3.3V)
MT 29F 2G 08
A
A
D WP
ES
D
Design Revision
Micron Technology
D = Fourth revision
Product Family
Production Status
29F = Single-supply NAND Flash memory
Blank = Production
Density
ES = Engineering sample
2G = 2Gb
MS = Mechanical sample
QS = Qualification sample
Device Width
08 = 8 bits
Operating Temperature Range
16 = 16 bits
Blank = Commercial (0°C to +70°C)
ET = Extended (–40°C to +85°C)
Classification
# of die # of CE# # of R/B#
A
1
1
1
Reserved for Future Use
I/O
Blank
Common
Flash Performance
Blank = Standard
Operating Voltage Range
A = 3.3V (2.7–3.6V)
Package Code
WP = 48-pin TSOP CPL
Feature Set
D = Feature set D
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59a__1.fm - Rev. A 8/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Part Numbering Information
Figure 3:
Part Number Chart (1.8V)
MT 29F 2G 08
A
B
D
HC
ES :D
Design Revision
Micron Technology
D = Fourth revision
Product Family
Production Status
29F = Single-supply NAND Flash memory
Blank = Production
Density
ES = Engineering sample
2G = 2Gb
MS = Mechanical sample
QS = Qualification sample
Device Width
08 = 8 bits
Operating Temperature Range
16 = 16 bits
Blank = Commercial (0°C to +70°C)
ET = Extended (–40°C to +85°C)
Classification
# of die # of CE# # of R/B#
A
1
1
Reserved for Future Use
I/O
1
Blank
Common
Flash Performance
Blank = Standard
Operating Voltage Range
B = 1.8V (1.65–1.95V)
Package Code
HC = 63-ball VFBGA (lead-free)
Feature Set
D = Feature set D
Valid Part Number Combinations
After building the part number from the part numbering chart, verify that the part
number is offered and valid by using the Micron Parametric Part Search Web site at
www.micron.com/products/parametric. If the device required is not on this list, contact
the factory.
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59a__1.fm - Rev. A 8/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RANDOM DATA READ 05h-E0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PAGE READ CACHE MODE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
READ UNIQUE ID EDh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
READ PARAMETER PAGE ECh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Internal Data Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PROGRAM for INTERNAL DATA MOVE 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Block Lock Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
WP# and Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
UNLOCK 23h-24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LOCK 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LOCK-TIGHT 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
BLOCK LOCK READ STATUS 7Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
One-Time Programmable (OTP) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
OTP DATA PROGRAM A0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
OTP DATA PROTECT A5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
OTP DATA READ AFh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GET FEATURES EEh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SET FEATURES EFh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59aTOC.fm - Rev. A 8/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Table of Contents
WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59aTOC.fm - Rev. A 8/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
List of Figures
List of Figures
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63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Number Chart (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Part Number Chart (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignment 48-Pin TSOP Type 1 CPL (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ball Assignment: 63-Ball VFBGA (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ball Assignment: 63-Ball VFBGA (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Map (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory Map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Array Organization for MT29F2G08AxD (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Array Organization for MT29F2G16AxD (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
t
Fall and tRise (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
t
Fall and tRise (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IOL vs. Rp (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IOL vs. Rp (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PAGE READ CACHE MODE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
READ UNIQUE ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
READ PARAMETER PAGE ECh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INTERNAL DATA MOVE with Optional RANDOM DATA Output and RANDOM DATA Input . 39
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Flash Array Protected: Inverted Area Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash Array Protected: Invert Area Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
UNLOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LOCK-TIGHT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PROGRAM/ERASE Issued to Locked Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
BLOCK LOCK READ STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
BLOCK LOCK Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
OTP DATA PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
OTP PROGRAM with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
OTP DATA PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
OTP DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
OTP DATA READ with RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GET FEATURES (EEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SET FEATURES (EFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PROGRAM for INTERNAL DATA MOVE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PROGRAM for INTERNAL DATA MOVE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59aLOF.fm - Rev. A 8/08 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
List of Figures
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
Figure 71:
Figure 72:
Figure 73:
Figure 74:
Figure 75:
Figure 76:
Figure 77:
SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Serial Access Cycle After READ (EDO Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
READ Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PAGE READ CACHE MODE Operation, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PAGE READ CACHE MODE Operation, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PAGE READ CACHE MODE Operation Without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PAGE READ CACHE MODE Operation Without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 80
READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Program Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PROGRAM PAGE CACHE MODE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PROGRAM PAGE CACHE MODE Operation Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
48-Pin TSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
63-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59aLOF.fm - Rev. A 8/08 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operational Example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operational Example (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Array Addressing: MT29F2G08AxD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Array Addressing: MT29F2G16AxD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block-Lock Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device ID and Configuration Codes for Address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Device ID and Configuration Codes for Address 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ONFI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block Lock Address Cycle Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Block Lock Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Feature Address 01h: Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Feature Address 80h: Programmable I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Feature Address 81h: Programmable R/B# Pull-down Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Error Management Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DC and Operating Characteristics (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DC and Operating Characteristics (1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC Characteristics: Command, Data, and Address Input (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AC Characteristics: Command, Data, and Address Input (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AC Characteristics: Normal Operation (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AC Characteristics: Normal Operation (1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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NDA_2gb_nand_m59aLOT.fm - Rev. A 8/08 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
General Description
General Description
NAND Flash technology provides a cost-effective solution for applications requiring
high-density, solid-state storage. The MT29F2GxxAxD is a 2Gb NAND Flash memory
device. Micron NAND Flash devices include standard NAND Flash features as well as
new features designed to enhance system-level performance.
Micron NAND Flash devices use a highly multiplexed 8-bit bus (I/O[7:0]) to transfer
data, addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#)
implement the NAND Flash command bus interface protocol. Additional pins control
hardware write protection (WP#), monitor the device ready/busy (R/B#) state, and
enable block lock functionality (LOCK).
This hardware interface creates a low-pin-count device with a standard pinout that is
the same from one density to another, allowing future upgrades to higher densities without board redesign.
The MT29F2G device contains 2,048 blocks. Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes. The pages are further divided into a
2,048-byte data storage region with a separate 64-byte area. The 64-byte area is typically
used for error management functions.
The contents of each page can be programmed in tPROG (TYP), and an entire block can
be erased in tBERS (TYP). On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. PROGRAM/ERASE endurance is specified at
100,000 cycles using appropriate error correction code (ECC) and error management.
Figure 4:
Pin Assignment 48-Pin TSOP Type 1 CPL (Top View)
x16
x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
DNU
DNU
NC
NC
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
DNU
DNU
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
x8
x16
Vss2
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
Vcc2
DNU
Vcc
Vss
NC
Vcc2
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
Vss2
Vss
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
Vcc
DNU
Vcc
Vss
NC
Vcc
I/O11
I/O3
I/O2
I/O1
I/O0
I/O10
I/O9
I/O8
Vss
Notes: 1. For package dimensions, see Figure 91 on page 99.
2. These pins might not be bonded in the package. However, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
PDF: 09005aef82784784 / Source: 09005aef82784840
NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
General Description
Figure 5:
Ball Assignment: 63-Ball VFBGA (x8)
1
2
A
NC
NC
B
NC
3
4
5
6
7
8
C
WP#
ALE
Vss
CE#
WE#
R/B#
D
Vcc2
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
Vss2
NC
G
DNU
Vcc2
LOCK
NC
NC
NC
H
NC
I/O0
NC
NC
NC
Vcc
J
NC
I/O1
NC
Vcc
I/O5
I/O7
K
Vss
I/O2
I/O3
I/O4
I/O6
Vss
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
Top View, Ball Down
Notes: 1. For package dimensions, see Figure 77 on page 87
2. These pins might not be bonded in the package. However, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
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2Gb x8, x16: NAND Flash Memory
General Description
Figure 6:
Ball Assignment: 63-Ball VFBGA (x16)
1
2
A
NC
NC
B
NC
3
4
5
6
7
8
C
WP#
ALE
Vss
CE#
WE#
R/B#
D
Vcc
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
Vss
NC
G
DNU
Vcc
LOCK
I/O13
I/O15
NC
H
I/O8
I/O0
I/O10
I/O12
I/O14
Vcc
J
I/O9
I/O1
I/O11
Vcc
I/O5
I/O7
K
Vss
I/O2
I/O3
I/O4
I/O6
Vss
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
Top View, Ball Down
Notes: 1. For package dimensions, see Figure 77 on page 87.
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2Gb x8, x16: NAND Flash Memory
General Description
Table 1:
Signal Descriptions
Symbol
Type
Description
ALE
Input
CE#
Input
CLE
Input
LOCK
Input
RE#
WE#
WP#
Input
Input
Input
I/O[7:0]
(x8)
I/O[15:0]
(x16)
R/B#
I/O
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register on the rising edge of
WE#. When address information is not being loaded, ALE should be driven LOW.
Chip enable: This gates transfers between the host system and the NAND Flash
device. After the device starts a PROGRAM or ERASE operation, CE# can be deasserted. See “Bus Operation” on page 18 for additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, CLE should be driven LOW.
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To
disable the BLOCK LOCK, connect LOCK to VSS during power-up, or leave it
disconnected (internal pull-down).
Read enable: This gates transfers from the NAND Flash device to the host system.
Write enable: This gates transfers from the host system to the NAND Flash device.
Write protect: This protects against inadvertent PROGRAM and ERASE operations.
All PROGRAM and ERASE operations are disabled when WP# is LOW.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction
information. Data is output only during READ operations; at other times the I/Os
are inputs.
Output
VCC
VSS
NC
Supply
Supply
–
DNU
–
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Ready/busy: This is an open-drain, active-LOW output that uses an external pullup resistor. R/B# is used to indicate when the chip is processing a PROGRAM or
ERASE operation. It is also used during READ operations to indicate when data is
being transferred from the array into the serial data register. When these
operations have completed, R/B# returns to the high-impedance state.
VCC: This is the power supply.
VSS: This is the ground connection.
No connect: NCs are not internally connected. They can be driven or left
unconnected.
Do not use: DNUs must be left unconnected.
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2Gb x8, x16: NAND Flash Memory
Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
This provides a memory device with a low pin count. The commands received at the I/O
control circuits are latched by a command register and are transferred to control logic
circuits for generating internal signals to control device operations. The addresses are
latched by an address register and sent to a row decoder or a column decoder to select a
row address or a column address, respectively.
The data are transferred to or from the NAND Flash memory array, byte by byte (x8) or
word by word (x16), through a data register and a cache register. The cache register is
closest to I/O control circuits and acts as a data buffer for the I/O data, whereas the data
register is closest to the memory array and acts as a data buffer for the NAND Flash
memory array operation.
The NAND Flash memory array is programmed and read in page-based operations and
is erased in block-based operations. During normal page operations, the data and cache
registers are tied together and act as a single register. During cache operations the data
and cache registers operate independently to increase data throughput.
These devices also have a status register that reports the status of device operation.
Figure 7:
NAND Flash Functional Block Diagram
VCC
I/Ox
I/O
Control
VSS
Address Register
Status Register
Command Register
CE#
Column Decode
CLE
WE#
Control
Logic
Row Decode
ALE
RE#
WP#
LOCK1
NAND Flash
Array
Data Register
R/B#
Cache Register
Notes: 1. LOCK pin is used for 1.8V device.
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2Gb x8, x16: NAND Flash Memory
Addressing
Addressing
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using
a 5-cycle sequence as shown in Tables 4 and 5, on pages 16 and 17. See Figure 8 for additional memory mapping and addressing details.
Memory Mapping
Figure 8:
Memory Map (x8)
Blocks
2Gb: BA[16:6]
0
1
2
• • • • • • • • • • • • 2,047
Pages
PA[5:0]
0
1
2
• • •
Bytes
CA[11:0]
0
1
2
• • • • • • • • • • • • • • • • • • •
63
2,047
•••
2,111
Spare area
Table 2:
Operational Example (x8)
Block
Page
Min Address in Page
Max Address in Page
Out of Bounds Addresses in Page
0
0
0
…
2,046
2,047
0
1
2
…
62
63
0x0000000000
0x0000010000
0x0000020000
…
0x01FFFE0000
0x01FFFF0000
0x000000083F
0x000001083F
0x000002083F
…
0x01FFFE083F
0x01FFFF083F
0x0000000840–0x0000000FFF
0x0000010840–0x0000010FFF
0x0000020840–0x0000020FFF
0x01FFFE0840–0x01FFFE0FFF
0x01FFFF0840–0x01FFFF0FFF
Notes: 1. As shown in Table 4 on page 16, the high nibble of ADDRESS cycle 2 has no assigned
address bits; however, these 4 bits must be held LOW during the ADDRESS cycle to ensure
that the address is interpreted correctly by the NAND Flash device. These extra bits are
accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to
them.
2. The 12-bit column address is capable of addressing from 0 to 2,047 bytes on a x8 device;
however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are
“out of bounds,” do not exist in the device, and cannot be addressed.
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2Gb x8, x16: NAND Flash Memory
Memory Mapping
Figure 9:
Memory Map x16
Blocks
BA[16:6]
0
1
2
• • • • • • • • • • • • 2,047
Pages
PA[5:0]
0
1
2
• • •
Words
CA[10:0]
0
1
2
• • • • • • • • • • • • • • • • • • •
63
1,023
•••
1,055
Spare area
Table 3:
Operational Example (x16)
Block
Page
Min Address in Page
Max Address in Page
Out of Bounds Addresses in Page
0
0
0
…
2,046
2,047
0
1
2
…
62
63
0x0000000000
0x0000010000
0x0000020000
…
0x01FFFE0000
0x01FFFF0000
0x000000041F
0x000001041F
0x000002041F
…
0x01FFFE041F
0x01FFFF041F
0x0000000420–0x0000000FFF
0x0000010420–0x0000010FFF
0x0000020420–0x0000020FFF
0x01FFFE0420–0x01FFFE0FFF
0x01FFFF0420–0x01FFFF0FFF
Notes: 1. As shown in Table 5 on page 17, the upper 5 bits of ADDRESS cycle 2 have no assigned
address bits; however, these 5 bits must be held LOW during the ADDRESS cycle to ensure
that the address is interpreted correctly by the NAND Flash device. These extra bits are
accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to
them.
2. The 11-bit column address is capable of addressing from 0 to 2,047 words on x16 devices;
however, only words 0 through 1,055 are valid. Words 1,056 through 2,048 of each page
are “out of bounds,” do not exist in the device, and cannot be addressed.
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2Gb x8, x16: NAND Flash Memory
Array Organization
Array Organization
Figure 10:
Array Organization for MT29F2G08AxD (x8)
2,112 bytes
I/O 0
Cache Register
2,048
64
Data Register
2,048
64
64 pages = 1 block
(128K + 4K) bytes
1 block
2,048 blocks
per device
I/O 7
1 page
= (2K + 64) bytes
1 block
= (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 device = (2K + 64) bytes x 64 pages
x 2,048 blocks
= 2,112Mb
Table 4:
Array Addressing: MT29F2G08AxD
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
First
Second
Third
Fourth
Fifth
CA7
LOW
BA7
BA15
LOW
CA6
LOW
BA6
BA14
LOW
CA5
LOW
PA5
BA13
LOW
CA4
LOW
PA4
BA12
LOW
CA3
CA111
PA3
BA11
LOW
CA2
CA10
PA2
BA10
LOW
CA1
CA9
PA1
BA9
LOW
CA0
CA8
PA0
BA8
BA16
Notes: 1. If CA11 is “1,” then CA[10:6] must be “0.”
2. Block address concatenated with page address = actual page address; CAx = column
address; PAx = page address; BAx = block address.
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2Gb x8, x16: NAND Flash Memory
Array Organization
Figure 11:
Array Organization for MT29F2G16AxD (x16)
1,056 words
I/O 0
Cache Register
1,024
32
Data Register
1,024
32
64 pages = 1 block
(64K + 2K) words
1 block
2,048 blocks
per device
I/O 15
1 page
= (1K + 32) words
1 block
= (1K + 32) words x 64 pages
= (64K + 2K) words
1 device = (1K + 32) words x 64 pages
x 2,048 blocks
= 2,112Mb
Table 5:
Cycle
First
Second
Third
Fourth
Fifth
Array Addressing: MT29F2G16AxD
I/O[15:8]
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
LOW
LOW
LOW
LOW
LOW
CA7
LOW
BA7
BA15
LOW
CA6
LOW
BA6
BA14
LOW
CA5
LOW
PA5
BA13
LOW
CA4
LOW
PA4
BA12
LOW
CA3
LOW
PA3
BA11
LOW
CA2
CA101
PA2
BA10
LOW
CA1
CA9
PA1
BA9
LOW
CA0
CA8
PA0
BA8
BA16
Notes: 1. If CA10 is “1,” then CA[9:5] must be “0.”
2. Block address concatenated with page address = actual page address. CAx = column
address; PAx = page address; BAx = block address.
3. I/O[15:8] are not used during the addressing sequence and should be driven LOW.
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2Gb x8, x16: NAND Flash Memory
Bus Operation
Bus Operation
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins. I/O[15:8] are used only for data in the x16 configuration.
Addresses and commands are always supplied on I/O[7:0].
The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS
INPUT cycles, and one or more DATA cycles—either READ or WRITE.
Control Signals
CE#, WE#, RE#, CLE, ALE and WP# control NAND Flash device READ and WRITE operations.
CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the NAND Flash memory will accept command, address, and data information.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power consumption. See Figure 61 on page 75 and Figure 69 on page 81 for examples of CE# “Don’t
Care” operations.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Commands
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are LOW, and
• CLE is HIGH, and
• The device is not busy
As exceptions, the device accepts the READ STATUS and RESET commands when busy.
Commands are transferred to the command register on the rising edge of WE# (see
Figure 54 on page 71).
Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be
written with zeros when a command is issued.
Address Input
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are LOW, and
• ALE is HIGH
Addresses are input on I/O[7:0]. Bits not part of the address space must be LOW.
For devices with a x16 interface, I/O[15:8] must be written with zeros when an address is
issued (see Figure 55 on page 71).
The number of ADDRESS cycles required for each command varies. Refer to the command descriptions to determine addressing requirements (see Table 7 on page 24).
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2Gb x8, x16: NAND Flash Memory
Bus Operation
Data Input
Data is written to the data register on the rising edge of WE# when:
• CE#, CLE, and ALE are LOW, and
• the device is not busy
Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices. See Figure 56 on
page 72 for additional data input details.
READs
After a READ command is issued, data is transferred from the memory array to the data
register on the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after the
transfer is complete. When data is available in the data register, it is clocked out of the
part by RE# going LOW. See Figure 60 on page 74 for detailed timing information.
The READ STATUS (70h) command or the R/B# signal can be used to determine when
the device is ready.
If a controller is using a timing of 30ns or longer for tRC, use Figure 57 on page 72 for
proper timing.
Ready/Busy#
The R/B# output provides a hardware method of indicating the completion of PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for proper
operation. The signal is typically HIGH, and transitions to LOW after the appropriate
command is written to the device. The signal pin’s open-drain driver enables multiple
R/B# outputs to be OR-tied. The READ STATUS command can be used in place of R/B#.
Typically, R/B# is connected to an interrupt pin on the system controller (see Figure 12
on page 20).
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# pin. The actual value used for Rp depends on the system timing
requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10- to
90-percent points on the R/B# waveform, rise time is approximately two time constants
(TC).
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# pin and the total load capacitance and may be changed if R/B pull-down strength
is not set to “full.”
Figure 15 on page 21 and Figures 16 and 17 on page 22 depict approximate Rp values
using a circuit load of 100pF.
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2Gb x8, x16: NAND Flash Memory
Bus Operation
The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCC.
V CC ( MAX ) – V OL ( MAX )
1.85V
Rp ( MIN, 1.8V part ) = --------------------------------------------------------------- = --------------------------I OL + ΣI L
3mA + ΣI L
Where ΣI L is the sum of the input currents of all devices tied to the R/B# pin.
Figure 12:
READY/BUSY# Open Drain
Rp
VCC
R/B#
Open drain output
IOL
GND
Device
Figure 13:
t
Fall and tRise (3.3V)
3.50
3.00
2.50
tFall
tRise
2.00
V
1.50
1.00
0.50
0.00
-1
0
2
4
0
2
4
6
TC
Vcc 3.3
Notes: 1.
2.
3.
4.
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t
Fall and tRise calculated at 10 percent and 90 percent points.
is primarily dependent on external pull-up resistor and external capacitive loading.
tFall ≈ 7ns at 1.8V.
See TC values in Figure 17 on page 22 for approximate Rp value and TC.
tRise
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2Gb x8, x16: NAND Flash Memory
Bus Operation
Figure 14:
t
Fall and tRise (1.8V)
3.50
3.00
2.50
V
tRise
tFall
2.00
1.50
1.00
0.50
0.00
-1
0
2
4
0
2
4
6
TC
Notes: 1.
2.
3.
4.
Figure 15:
VCC 1.8
tFall
and tRise calculated at 10 percent and 90 percent points.
is primarily dependent on external pull-up resistor and external capacitive loading.
tFall ≈ 7ns at 1.8V.
See TC values in Figure 17 on page 22 for approximate Rp value and TC.
tRise
IOL vs. Rp (3.3V)
3.50
3.00
2.50
2.00
T (μs)
1.50
1.00
0.50
0.00
0
2,000
4,000
6,000
8,000
10,000
12,000
Rp (:)
IOL at 3.6V (mA)
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2Gb x8, x16: NAND Flash Memory
Bus Operation
Figure 16:
IOL vs. Rp (1.8V)
3.50mA
3.00mA
2.50mA
2.00mA
I
1.50mA
1.00mA
0.50mA
0.00mA
0
2,000
4,000
6,000
8,000
10,000
12,000
Rp (:)
IOL at 1.95V (MAX)
Figure 17:
TC vs. Rp
1.20μs
1.00μs
800ns
T
600ns
400ns
200ns
0ns
0
2,000
4,000
6,000
8,000
Rp (:)
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22
10,000
12,000
IOL at VCC (MAX)
RC = TC
C = 100pF
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2Gb x8, x16: NAND Flash Memory
Bus Operation
Table 6:
Mode Selection
RE#
WP#
LOCK3
L
H
X
X
H
L
H
X
X
H
L
L
H
H
X
L
H
L
H
H
X
L
L
L
H
H
X
Data input
L
L
L
H
X
X
Sequential read and data output
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
X
H
H
L
0V/VCC1
X
X
X
X
X
During read (busy)
During program (busy)
During erase (busy)
Write protect
Standby
CLE
ALE
CE#
H
L
L
WE#
H
X
X
X
X
Mode
Read mode
Command input
Address input
Write mode
Command input
Address input
Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby.
2. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW;
X = VIH or VIL.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Command Definitions
Table 7:
Command Set
Command
PAGE READ
PAGE READ CACHE MODE RANDOM
PAGE READ CACHE MODE SEQUENTIAL
PAGE READ CACHE MODE LAST
READ for INTERNAL DATA MOVE
RANDOM DATA READ
READ ID
READ UNIQUE ID
READ PARAMETER PAGE
READ STATUS
PROGRAM PAGE
PROGRAM PAGE CACHE MODE
PROGRAM for INTERNAL DATA MOVE
RANDOM DATA INPUT
BLOCK ERASE
RESET
OTP DATA PROGRAM
OTP DATA PROTECT
OTP DATA READ
GET FEATURES
SET FEATURES
Command
Cycle 1
Number
of
Address
Cycles
00h
00h
31h
3Fh
00h
05h
90h
EDh
ECh
70h
80h
80h
85h
85h
60h
FFh
A0h
A5h
AFh
EEh
EFh
5
5
–
–
5
2
1
1
1
–
5
5
5
2
3
–
5
5
5
1
1
Data
Cycles
Command
Required1
Cycle 2
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Optional
Yes
No
No
Yes
No
No
No
4
30h
31h
–
–
35h
E0h
–
–
–
–
10h
15h
10h
–
D0h
–
10h
10h
30h
–
–
Valid
During
Busy
Notes
No
No
No
No
No
No
No
No
No
Yes
No
No
No
No
No
Yes
No
No
No
No
No
2
3
Notes: 1. Indicates required data cycles between command cycle 1 and command cycle 2.
2. RANDOM DATA READ command limited to use within a single page.
3. RANDOM DATA INPUT command limited to use within a single page.
Table 8:
Block-Lock Command Set
Command
UNLOCK
BLOCK LOCK
BLOCK LOCK-TIGHT
BLOCK LOCK READ STATUS
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
Command
Cycle 1
Number of
Address Cycles
Command
Cycle 2
Number of
Address Cycles
Valid During
Busy
23h
2Ah
2Ch
7Ah
3
–
–
3
24h
–
–
–
3
–
–
–
No
No
No
No
24
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2Gb x8, x16: NAND Flash Memory
Command Definitions
READ Operations
PAGE READ 00h-30h
At power-on, the device defaults to READ mode. To enter READ mode while in operation, write the 00h command to the command register, then write 5 ADDRESS cycles,
and conclude with the 30h command.
To determine the progress of the data transfer from the NAND Flash array to the data
register (tR), monitor the R/B# signal; or alternatively, issue a READ STATUS (70h) command. If the READ STATUS command is used to monitor the data transfer, the user must
reissue the READ (00h) command to receive data output from the data register. See
Figure 65 on page 79 and Figure 66 on page 80 for examples. After the READ command
has been reissued, pulsing the RE# line will result in outputting data, starting from the
initial column address.
A serial page read sequence outputs a complete page of data. After 30h is written, the
page data is transferred to the data register, and R/B# goes LOW during the transfer.
When the transfer to the data register is complete, R/B# returns HIGH. At this point, data
can be read from the device. Starting from the initial column address to the end of the
page, read the data by repeatedly pulsing RE# at the maximum tRC rate (see Figure 18).
Figure 18:
PAGE READ Operation
CLE
CE#
WE#
ALE
tR
R/B#
RE#
I/Ox
00h
30h
Address (5 cycles)
Data output (Serial access)
Don’t Care
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2Gb x8, x16: NAND Flash Memory
Command Definitions
RANDOM DATA READ 05h-E0h
The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h-30h) sequence.
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (2 cycles).
The RANDOM DATA READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially
(see Figure 19).
Figure 19:
RANDOM DATA READ Operation
tR
R/B#
RE#
I/Ox
00h
Address
(5 cycles)
30h
Data output
05h
Address
(2 cycles)
E0h
Data output
PAGE READ CACHE MODE Operations
Micron NAND Flash devices have a cache register that can be used to increase the READ
operation speed. Data can be output from the device's cache register while a page is
concurrently moved from the NAND Flash array to the data register.
To begin a PAGE READ CACHE MODE command sequence, issue the PAGE READ (00h30h) command to read a page from the NAND Flash array to the cache register. R/B#
goes LOW during tR (status register bits 6 and 5 = 00). After tR (R/B# is HIGH and status
register bits 6 and 5 = 11), issue either:
• the PAGE READ CACHE MODE SEQUENTIAL (31h) command to begin copying the
next sequential page from the NAND Flash array to the data register, or
• the PAGE READ CACHE MODE RANDOM (00h-31h) command to begin copying the
page specified in this command from the NAND Flash array to the data register.
After the PAGE READ CACHE MODE SEQUENTIAL or PAGE READ CACHE MODE RANDOM command has been issued, R/B# goes LOW (status register bits 6 and 5 = 00) for
t
DCBSYR1 while the device begins to copy the next page into the data register. After
t
DCBSYR1, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the
cache register is available. At this point, data can be output from the cache register by
toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device.
After the desired number of bytes are output from the cache register, it is possible to
either begin an additional PAGE READ CACHE MODE (31h or 00h-31h) operation or
issue the PAGE READ CACHE MODE LAST (3Fh) command.
If an additional PAGE READ CACHE MODE (31h or 00h-31h) operation is issued, R/B#
goes LOW (status register bits 6 and 5 = 00) for tDCBSYR2 while the data register is copied to the cache register and the device begins to copy the next page into the data register. After tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that
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2Gb x8, x16: NAND Flash Memory
Command Definitions
the cache register is available. At this point, data can be output from the cache register
by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h)
command can be used to change the column address of the data being output by the
device.
If the PAGE READ CACHE MODE LAST (3Fh) command is issued, R/B# goes LOW (status
register bits 6 and 5 = 00) for tDCBSYR2 while the data register is copied into the cache
register. After tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 11, indicating
that the cache register is available and that the NAND Flash array is ready for another
command. At this point, data can be output from the cache register by toggling RE#
beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be
used to change the column address of the data being output by the device.
During busy times (tDCBSYR1 and tDCBSYR2), the only valid commands are READ STATUS (70h) and RESET (FFh). Until status register bit 5 = 1, the only valid commands during PAGE READ CACHE MODE operations are READ STATUS (70h), PAGE READ CACHE
MODE (31h and 00h-31h), RANDOM DATA READ (05h-E0h), and RESET (FFh).
PAGE READ CACHE MODE SEQUENTIAL 31h
The PAGE READ CACHE MODE SEQUENTIAL (31h) command reads the next sequential
page within a block into the data register while the previous page is output from the
cache register.
To issue this command, write 31h to the command register.
When this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for
either tDCBSYR1 or tDCBSYR2. After tDCBSYR1 or tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is available. At this point,
data can be output from the cache register by toggling RE# beginning at column address
0. The RANDOM DATA READ (05h-E0h) command can be used to change the column
address of the data being output by the device.
PAGE READ CACHE MODE RANDOM 00h-31h
The PAGE READ CACHE MODE RANDOM (00h-31h) command reads the specified page
into the data register while the previous page is output from the cache register.
To issue this command, write 00h to the command register. Then write 5 address cycles
to the address register. Conclude the sequence by writing 31h to the command register.
The column address in the address specified is ignored.
When this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for
either tDCBSYR1 or tDCBSYR2. After tDCBSYR1 or tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is available. At this point,
data can be output from the cache register by toggling RE# beginning at column address
0. The RANDOM DATA READ (05h-E0h) command can be used to change the column
address of the data being output by the device.
PAGE READ CACHE MODE LAST 3Fh
The PAGE READ CACHE MODE LAST (3Fh) command copies a page from the data register to the cache register without beginning a new cache read.
To issue this command, write 3Fh to the command register.
When this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for
tDCBSYR2. After tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 11, indicating that the cache register is available and that the NAND Flash array is ready for
another command. At this point, data can be output from the cache register by toggling
RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command
can be used to change the column address of the data being output by the device.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 20:
PAGE READ CACHE MODE Operations
CLE
CE#
WE#
ALE
tDCBSYR1
tR
R/B#
RE#
I/Ox
00h
Address (5 cycles)
30h
31h
Data output
PAGE READ CACHE MODE
SEQUENTIAL operation
1
Repeat as many times as necessary
CLE
CE#
WE#
ALE
tDCBSYR2
tDCBSYR2
R/B#
RE#
I/Ox
00h
1
Address (5 cycles)
31h
Data output
3Fh
Data output
PAGE READ CACHE MODE
RANDOM operation
Repeat as many times as necessary
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2Gb x8, x16: NAND Flash Memory
Command Definitions
READ ID 90h
The READ ID command is used to read the 5 bytes of identifier code programmed into
the NAND Flash devices. The READ ID command reads a 5-byte table that includes
manufacturer ID, device configuration, and part-specific information (see Table 9 on
page 30).
Writing 90h to the command register puts the device into the read ID mode. The command register stays in this mode until the next command cycle is issued (see Figure 21).
Figure 21:
READ ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tWHR
I/Ox
90h
00h
tREA
Byte 1
Byte 0
Byte 2
Byte 3
Byte 4
(or 20h)
Address, 1 cycle
Note:
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See Table 9 on page 30 for byte definitions.
29
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Table 9:
Device ID and Configuration Codes for Address 00h
Address = 00h
Options
Byte 0
Byte 1
MT29FG08AAD
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
Byte 2
Number of die per CE
Cell type
Number of
simultaneously
programmed pages
Interleaved operations
between multiple die
Cache programming
Byte value
Byte 3
Page size
Spare area size (bytes)
Block size (w/o spare)
Organization
Serial access (MIN)
Serial access (MIN)
Byte value
Byte value
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value1
0
0
1
0
1
1
0
0
2Ch
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
DAh
CAh
AAh
BAh
0
0
00b
00b
01b
Manufacturer ID
Micron
Device ID
2Gb, x8, 3V
2Gb, x16, 3V
2Gb, x8, 1.8V
2Gb, x16, 1.8V
1
SLC
1
0
0
Not supported
0
Supported
MT29F2Gxxxxx
1
1
2KB
64B
128KB
x8
x16
25ns
35ns
MT29F2G08AAD
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
Byte 4
Reserved
Planes per CE#
Plane size
Reserved
Byte value
0
0
0b
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
0
0
0
1
0
1
1
2Gb
0
0
MT29F2Gxx
0
0
0
0
1
1
1
1
1
0
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1b
80h
01b
1b
01b
0b
1b
1xxxb
0xxx0b
95h
D5h
15h
55h
00b
00b
101b
0b
50h
Notes: 1. b = binary; h = hex.
Table 10:
Device ID and Configuration Codes for Address 20h
Address = 20h
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
“O”
“N”
“F”
“I”
Undefined
0
0
0
0
X
1
1
1
1
X
0
0
0
0
X
0
0
0
0
X
1
1
0
1
X
1
1
1
0
X
1
1
1
0
X
1
0
0
1
X
4Fh
4Eh
46h
49h
XXh
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30
Notes
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Command Definitions
READ UNIQUE ID EDh
Micron offers the READ UNIQUE ID command to provide a method for uniquely identifying a NAND Flash device.
The READ UNIQUE ID operation uses standard command and address timing. The format of the ID is arbitrary; however, this ID is guaranteed to be unique for every NAND
Flash device manufactured.
Many controllers use proprietary error correction code (ECC) schemes; thus, it is not
possible for Micron to protect unique ID data with factory-programmed ECC. However,
to ensure data integrity, Micron programs the noted NAND Flash devices with a 16-byte
unique ID, beginning at byte 0 of the page, then follows with 16 bytes of complement ID.
These 32 bytes of data are then repeated a total of 16 times, such that the last byte of the
last copy of complement unique ID resides at byte 511 in the page. The user can simply
XOR the first copy of the unique ID and its complement. If the result is “1,” the unique ID
is good. In the unlikely event that the result is non-zero, the user can repeat the XOR
operation on a subsequent copy of the unique ID data. Figure 22 shows timing for the
device.
The upper eight I/Os on an x16 device are not used and are a “Don’t Care” for x16
devices.
Figure 22:
READ UNIQUE ID Operation
CLE
WE#
ALE
RE#
I/O[7:0]
EDh
00h
Byte 0
tR
Byte 1
…
Byte 14
Byte 15
Unique ID data
R/B#
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2Gb x8, x16: NAND Flash Memory
Command Definitions
READ PARAMETER PAGE ECh
The READ PARAMETER PAGE function retrieves the data structure that describes the
device's organization, features, timings, and other behavioral parameters. The data
structure is repeated at least three times. Figure 23 defines the READ PARAMETER PAGE
behavior.
The RANDOM DATA READ (05h-E0h) command is permitted during data output.
The upper eight I/Os on an x16 device are not used and are a “Don’t Care” for x16
devices.
Figure 23:
READ PARAMETER PAGE ECh
CLE
WE#
ALE
RE#
I/O[7:0]
ECh
00h
P0
P1
…
P1022
P1023
tR
R/B#
Table 11:
Byte
0–3
4–5
6-7
ONFI Parameters
Description
8-9
10–31
Parameter page signature
Revision number
Features supported
MT29F2G08AAD
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
Optional commands supported
Reserved
32–43
44–63
Device manufacturer
Device model
MT29F2G08AAD
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
64
65–66
67–79
80–83
Manufacturer ID
Date code
Reserved
Number of data bytes per page
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
Value
4Fh, 4Eh, 46h, 49h
02h, 00h
10h, 00h
11h, 00h
10h, 00h
11h, 00h
3Fh, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h
4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h, 20h
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 30h, 38h, 41h, 41h, 44h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 31h, 36h, 41h, 41h, 44h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 30h, 38h, 41h, 42h, 44h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 31h, 36h, 41h, 42h, 44h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h
2Ch
00h,00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
00h, 08h, 00h, 00h
32
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Table 11:
ONFI Parameters (Continued)
Byte
Description
84–85
86–89
90–91
92–95
96-99
100
101
102
103–104
105–106
107
Number of spare bytes per page
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
Number of blocks per unit
Number of logical units
Number of address cycles
Number of bits per cell
Bad blocks maximum per unit
Block endurance
Guaranteed valid blocks at beginning
of target
Block endurance for guaranteed
valid blocks
Number of programs per page
Partial programming attributes
Number of ECC bits
Number of interleaved address bits
Interleaved operation attributes
Reserved
I/O pin capacitance
Timing mode support MT29F2G08AAD
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
Program cache
MT29F2G08AAD
timing
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
tPROG maximum
MT29F2G08AAD
page program time
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
tBERS maximum block erase time
tR maximum page read time
tCCS minimum
MT29F2G08AAD
MT29F2G16AAD
MT29F2G08ABD
MT29F2G16ABD
Reserved
108–109
110
111
112
113
114
115–127
128
129–130
131–132
133–134
135–136
137–138
139–140
141–163
164–165 Vendor-specific revision number
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
Value
40h, 00h
00h, 02h, 00h, 00h
10h, 00h
40h, 00h, 00h, 00h
00h, 08h, 00h, 00h
01h
23h
01h
28h, 00h
01h, 05h
01h
00h, 00h
04h
00h
01h
00h
00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
0Ah
1Fh, 00h
1Fh, 00h
07h, 00h
07h, 00h
1Fh, 00h
1Fh, 00h
07h, 00h
07h, 00h
F4h, 01h
F4h, 01h
BCh, 02h
BCh, 02h
B8h, 0Bh
19h, 00h
46h, 00h
46h, 00h
64h, 00h
64h, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
01h, 00h
33
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Table 11:
ONFI Parameters (Continued)
Byte
Description
Value
166–253 Vendor specific
254–255
256–511
512–767
768+
Integrity CRC
Value of bytes 0–255
Value of bytes 0–255
Additional redundant parameter pages
00h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h, 01h, 0Ah, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h
Set at TEST.
READ STATUS 70h
These NAND Flash devices have an 8-bit status register the software can read during
device operation. On the x16 device, I/O[15:8] are “0” when the status register is being
read. Table 12 describes the status register.
After a READ STATUS command, all READ cycles will be from the status register until a
new command is issued. Changes in the status register will be seen on I/O[7:0] as long
as CE# and RE# are LOW; it is not necessary to start a new READ STATUS cycle to see
these changes.
While monitoring the status register to determine when the tR (transfer from NAND
Flash array to data register) is complete, the user must reissue the READ (00h) command
to make the change from status to read mode. After the READ command has been reissued, pulsing the RE# line will result in outputting data, starting from the initial column address.
Table 12:
Status Register Bit Definition
SR
Bit
Program
Page
Program Page
Cache Mode
Page Read
Page Read
Cache Mode
Block Erase
0
Pass/fail
Pass/fail (N)
–
–
Pass/fail
1
–
Pass/fail (N-1)
–
–
2
3
4
5
–
–
–
Ready/busy
–
–
–
Ready/busy1
–
–
–
Ready/busy
–
–
–
Ready/busy1
6
Ready/busy
Ready/busy
7
Write protect
Ready/busy
cache2
Write protect
Ready/busy
cache2
Write protect Write protect
Definition
0 = Successful PROGRAM/ERASE
1 = Error in PROGRAM/ERASE
–
0 = Successful PROGRAM
1 = Error in PROGRAM
–
0
–
0
–
0
Ready/busy
0 = Busy
1 = Ready
Ready/busy
0 = Busy
1 = Ready
Write protect 0 = Protected
1 = Not protected
Notes: 1. Status register bit 5 is “0” during the actual programming operation. If cache mode is
used, this bit will be “1” when all internal operations are complete.
2. Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6.
See Figure 27 on page 37 and Figure 73 on page 84.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 24:
Status Register Operation
CE#
tCLR
CLE
WE#
tREA
RE#
I/Ox
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70h
Status output
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2Gb x8, x16: NAND Flash Memory
Command Definitions
PROGRAM Operations
PROGRAM PAGE 80h-10h
Micron NAND Flash devices are inherently page-programmed devices. Pages must be
programmed consecutively within a block, from the least significant page address to
most significant page address (i.e., 0, 1, 2, …, 63). Random page address programming is
prohibited.
Micron NAND Flash devices also support partial-page programming operations. This
means that any single bit can only be programmed one time before an erase is required;
however, the page can be partitioned such that a maximum of four programming operations are supported before an erase is required.
SERIAL DATA INPUT 80h
PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command
into the command register, followed by 5 ADDRESS cycles, then the data. Serial data is
loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h)
command is written after the data input is complete. The control logic automatically
executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects “1s” that are not successfully written
to “0s.”
R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS
(70h) command and the RESET (FFh) command are the only commands valid during the
programming operation. Bit 6 of the status register will reflect the state of R/B#. When
the device reaches ready, read bit 0 of the status register to determine if the program
operation passed or failed (see Figure 25). The command register stays in read status
register mode until another valid command is written to it.
RANDOM DATA INPUT 85h
After the initial data set is input, additional data can be written to a new column address
with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuing the PAGE
WRITE (10h) command. See Figures 25 for the proper command sequence.
Figure 25:
PROGRAM and READ STATUS Operation
tPROG
R/B#
I/Ox
80h
Address (5 cycles)
DIN
70h
10h
Status
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
Figure 26:
RANDOM DATA INPUT
tPROG
R/B#
I/Ox
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80h Address (5 cycles)
DIN
85h Address (2 cycles)
36
DIN
10h
70h
Status
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2Gb x8, x16: NAND Flash Memory
Command Definitions
PROGRAM PAGE CACHE MODE 80h-15h
Cache programming is actually a buffered programming mode of the standard PROGRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by 5 cycles of address, and a full or
partial page of data. The data is initially copied into the cache register, and the CACHE
PROGRAM (15h) command is then latched to the command register. Data is transferred
from the cache register to the data register on the rising edge of WE#. R/B# goes LOW
during this transfer time. After the data has been copied into the data register and R/B#
returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and subsequent programming passes, transfer from the cache register to the data register is held
off until current data register content has been programmed into the array.
The PROGRAM PAGE CACHE MODE command can cross block address boundaries.
RANDOM DATA INPUT (85h) commands are permitted with PROGRAM PAGE CACHE
MODE operations.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h)
command to determine when the cache register is ready to accept new data. The R/B#
pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual programming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE
PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every
time, including the last page of the programming sequence, status register bit 5 must be
used to determine when programming is complete (see Figure 27 on page 37).
Bit 1 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM operation is returned with bit 0 of the status register when bit 5 of the status register is a “1”
(ready state) as shown in Figure 27 on page 37.
Figure 27:
PROGRAM PAGE CACHE MODE Example
tCBSY
tCBSY
tCBSY
tLPROG1
R/B#
I/Ox
80h
Address &
data input
15h
80h
Address &
data input
15h
80h
Address &
data input
15h
80h
Address &
data input
10h
A: Without status reads
tCBSY
tLPROG1
R/B#
I/Ox
80h
Address &
data input
15h
70h
Status
output2
80h
Address &
data input
10h
70h
Status
output2
B: With status reads
Notes: 1. See Note 3, Table 32 on page 70.
2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass/fail status. RE# can stay LOW
or pulse multiple times after a 70h command.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Internal Data Move
An internal data move requires two command sequences. Issue a READ for INTERNAL
DATA MOVE (00h-35h) command first, then the PROGRAM for INTERNAL DATA MOVE
(85h-10h) command.
READ FOR INTERNAL DATA MOVE 00h-35h
The READ for INTERNAL DATA MOVE (00h-35h) command is used in conjunction with
the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. First, 00h is written to
the command register, then the internal source address is written (5 cycles). After the
address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the
command register. This transfers a page from memory into the cache register.
All 5 ADDRESS cycles are required when a READ for INTERNAL DATA MOVE command
is issued.
After a READ for INTERNAL DATA MOVE (00h-35h) command is issued and R/B#
returns HIGH, signifying operation completion, the data transferred from the source
page into the cache register may be read out by toggling RE#. Data is output sequentially
from the column address originally specified with the READ FOR INTERNAL DATA
MOVE (00h-35h) command. RANDOM DATA READ (05h-E0h) commands can be issued
without limit after the READ FOR INTERNAL DATA MOVE command.
The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE
command. Please refer to the description of this command in the following section.
PROGRAM for INTERNAL DATA MOVE 85h-10h
After the READ for INTERNAL DATA MOVE (00h-35h) command has been issued and
R/B# goes HIGH, the PROGRAM for INTERNAL DATA MOVE (85h-10h) command can
be written to the command register. This command transfers the data from the cache register
to the data register and programming of the new destination page begins. The sequence:
85h, destination address (5 cycles), then 10h, is written to the device. After 10h is written,
R/B# goes LOW while the control logic automatically programs the new page. The READ
STATUS command can be used instead of the R/B# line to determine when the write is
complete. When status register bit 6 = 1, bit 0 of the status register indicates if the operation was successful.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for
INTERNAL DATA MOVE command sequence to modify one or more bytes of the original
data. First, data is copied into the cache register using the 00h-35h command sequence,
then the RANDOM DATA INPUT (85h) command is written along with the address of the
data to be modified next. New data is input on the external data pins. This copies the
new data into the cache register.
When 10h is written to the command register, the original data plus the modified data
are transferred to the data register, and programming of the new page is started. The
RANDOM DATA INPUT command can be issued as many times as necessary before
starting the programming sequence with 10h (see Figures 28 and 29 on page 39).
Because INTERNAL DATA MOVE operations do not use external memory, ECC cannot
be used to check for errors before programming the data to a new page. This can lead to
a data error if the source page contains a bit error due to charge loss or charge gain. In
the case that multiple INTERNAL DATA MOVE operations are performed, these bit
errors may accumulate without correction. For this reason, it is highly recommended
that systems using INTERNAL DATA MOVE operations also use a robust ECC scheme
that can correct 2 or more bits per sector.
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Figure 28:
INTERNAL DATA MOVE
tR
tPROG
R/B#
RE#
WE#
I/Ox
00h
Address (5 cycles)
Data output
35h
05h
Address
(2 cycles)
E0h
Data output
85h
Address (5 cycles)
10h
70h
Status
Unlimited number of repetitions
39
Figure 29:
INTERNAL DATA MOVE with Optional RANDOM DATA Output and RANDOM DATA Input
R/B#
RE#
WE#
I/Ox
00h
Address (5 cycles)
35h
Data output
Address Data
85h (5
cycles)
Address
85h (2
cycles)
Data
Unlimited number of repetitions
Optional
10h
70h
Status
2Gb x8, x16: NAND Flash Memory
Command Definitions
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tPROG
tR
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Optional
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Command Definitions
BLOCK ERASE Operation
BLOCK ERASE 60h-D0h
Erasing occurs at the block level. For example, the MT29F2G08ABD device has 2,048
erase blocks, organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes).
Each block is 132K bytes (128K + 4K bytes). The BLOCK ERASE command operates on
one block at a time (see Figure 30).
Three cycles of addresses BA[18:6] and PA[5:0] are required. Although page addresses
PA[5:0] are loaded, they are a “Don’t Care” and are ignored for BLOCK ERASE operations.
See Table 4 on page 16 for addressing details.
The actual command sequence is a two-step process. The ERASE SETUP (60h) command is first written to the command register. Then 3 cycles of addresses are written to
the device. Next, the ERASE CONFIRM (D0h) command is written to the command register. At the rising edge of WE#, R/B# goes LOW and the control logic automatically controls the timing and erase-verify operations. R/B# stays LOW for the entire tBERS erase
time.
The READ STATUS (70h) command can be used to check the status of the BLOCK ERASE
operation. When bit 6 = 1, the ERASE operation is complete. Bit 0 indicates a pass/fail
condition where 0 = pass (see Figure 30, and Table 12 on page 34).
Figure 30:
BLOCK ERASE Operation
CLE
CE#
WE#
ALE
tBERS
R/B#
RE#
I/Ox
60h
Address input (3 cycles)
D0h
70h
Status
I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error
Don’t Care
Notes: 1. I/O[15:8] is applicable only for x16 devices.
2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Block Lock Feature
The block lock feature of this NAND Flash device provides the ability to protect the
entire device or ranges of blocks from PROGRAM and ERASE operations. Using this
block lock feature offers increased functionality and flexibility over using just the WP#
pin to prevent PROGRAM and ERASE operations.
Block lock features are enabled and disabled at power-on through the use of the LOCK
pin. At power-on, if LOCK is LOW, all block lock commands are disabled. However, at
power-on, if LOCK is HIGH, the block lock commands are enabled and, by default, all of
the blocks on the device are protected, or locked, from PROGRAM and ERASE operations, even if WP# is HIGH.
Before the contents of the device can be modified, the device must first be unlocked.
Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE
operations complete successfully only in the block ranges that have been unlocked.
Blocks, once unlocked, can be locked again to protect them from further PROGRAM and
ERASE operations.
Blocks that are locked can be protected further, or locked tight. When locked tight, the
device’s blocks can no longer be locked or unlocked until the device is power cycled.
WP# and Block Lock
• Holding WP# LOW locks all blocks provided the blocks are not locked tight.
• If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command
must be issued to unlock blocks.
UNLOCK 23h-24h
By default at power-on if LOCK is HIGH, all of the blocks in the NAND Flash device are
locked, meaning that they are protected from PROGRAM and ERASE operations. The
UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no
protection and can be programmed or erased.
The UNLOCK command uses two registers, a lower boundary block address register and
an upper boundary block address register, and the invert area bit to determine what
range of blocks are unlocked. When the invert area bit = 0, the range of blocks within the
lower and upper boundary address registers are unlocked. When the invert area bit = 1,
the range of blocks outside the boundaries of the lower and upper boundary address
registers are unlocked. The lower boundary block address must be less than the upper
boundary block address. Figures 31 and 32 on page 42 show examples of how the lower
and upper boundary address registers work with the invert area bit.
To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate ADDRESS cycles that indicate the lower boundary block address. Then issue the
24h command followed by the appropriate ADDRESS cycles that indicate the upper
boundary block address. The least significant page address bit, PA0, should be set to “1”
if setting the invert area bit; otherwise, it should be “0.” The other page address bits
should be “0” (see Figure 33 on page 43).
Only one range of blocks can be specified in the lower and upper boundary block
address registers. If after unlocking a range of blocks the UNLOCK command is again
issued, the new block address range determines which blocks are unlocked. The previous unlocked block address range is not retained.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 31:
Flash Array Protected: Inverted Area Bit = 0
Block 2047
Block 2046
Block 2045
Block 2044
Block 2043
Block 2042
Block 2041
Block 2040
Block. 2039
..
..
..
..
..
..
.
Block 0002
Block 0001
Block 0000
Figure 32:
ALE Cycle
First
Second
Third
FFCh
Upper block boundary
FF8h
Lower block boundary
Unprotected
area
Protected
area
Flash Array Protected: Invert Area Bit = 1
Block 2047
Block 2046
Block 2045
Block 2044
Block 2043
Block 2042
Block 2041
Block 2040
Block. 2039
..
..
..
..
..
..
.
Block 0002
Block 0001
Block 0000
Table 13:
Protected
area
Unprotected
Area
FFCh
Upper block boundary
FF8h
Lower block boundary
Protected
area
Unprotected
area
Block Lock Address Cycle Assignments
I/O[15:8]1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
LOW
LOW
LOW
BA7
BA15
LOW
BA6
BA14
LOW
LOW
BA13
LOW
LOW
BA12
LOW
LOW
BA11
LOW
LOW
BA10
LOW
LOW
BA9
BA17
Invert area bit2
BA8
BA16
Notes: 1. I/O[15:8] is applicable only for x16 devices.
2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 33:
UNLOCK Operation
WP#
CLE
CE#
WE#
ALE
RE#
I/Ox
23h
Unlock
Block
Block
Block
add 1
add 2
add 3
Lower boundary
24h
Block
Block
Block
add 1
add 2
add 3
Upper boundary
R/B#
LOCK 2Ah
By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are
locked, meaning that they are protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked
again using the LOCK (2Ah) command. The LOCK command locks all of the blocks in the
device. Locked blocks are write-protected from PROGRAM and ERASE operations.
To lock all of the blocks in the device, issue the LOCK (2Ah) command.
When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for
LBSY. The PROGRAM or ERASE operation does not complete. Any READ STATUS command reports bit 7 as “0,” indicating that the block is protected.
t
The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is
locked tight (see “LOCK-TIGHT 2Ch” on page 44).
Figure 34:
LOCK Operation
CLE
CE#
WE#
I/Ox
2Ah
LOCK command
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2Gb x8, x16: NAND Flash Memory
Command Definitions
LOCK-TIGHT 2Ch
The LOCK-TIGHT (2Ch) command prevents locked blocks from being unlocked and
also prevents unlocked blocks from being locked. When this command is issued, the
UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional
level of protection against inadvertent PROGRAM and ERASE operations to locked
blocks.
To implement lock-tight in all of the locked blocks in the device, verify that WP# is HIGH
and then issue the LOCK-TIGHT (2Ch) command.
When a PROGRAM or ERASE operation is issued to a locked block that has also been
locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not
complete. The READ STATUS (70h) command reports bit 7 as “0,” indicating that the
block is protected. PROGRAM and ERASE operations complete successfully to blocks
that were not locked at the time the LOCK-TIGHT command was issued.
After the LOCK-TIGHT command is issued, the command cannot be disabled via a software command. The only ways to disable the lock-tight status is to power cycle the
device. When the lock-tight status is disabled, all of the blocks become locked, the same
as if the LOCK (2Ah) command had been issued.
The LOCK-TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.
Figure 35:
LOCK-TIGHT Operation
LOCK
WP#
CLE
CE#
WE#
I/Ox
2Ch
LOCK-TIGHT
command
R/B#
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Don’t Care
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 36:
PROGRAM/ERASE Issued to Locked Block
tLBSY
R/B#
I/Ox
PROGRAM or ERASE
Address/data input
CONFIRM
Locked block
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70h
60h
READ STATUS
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2Gb x8, x16: NAND Flash Memory
Command Definitions
BLOCK LOCK READ STATUS 7Ah
The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection
status of individual blocks. The ADDRESS cycles have the same format as shown in
Table 14; the invert area bit should be set LOW. On the falling edge of RE# the I/O pins
output the block lock status register which contains the information on the protection
status of the block. Table 14 shows how to interpret the block lock status register bits.
Table 14:
Block Lock Status Register Bit Definitions
Block Lock Status Register Definitions
Block is locked-tight
Block is locked
Block is unlocked, and device is locked-tight
Block is unlocked, and device is not locked-tight
Figure 37:
I/O[7:3]
I/O2 (Lock#)
I/O1 (LT#)
I/O0 (LT)
X
X
X
X
0
0
1
1
0
1
0
1
1
0
1
0
BLOCK LOCK READ STATUS
CLE
CE#
WE#
tWHR
ALE
RE#
I/Ox
7Ah
BLOCK LOCK
READ STATUS
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Add 1
Add 2
Add 3
Status
Block address
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 38:
BLOCK LOCK Flow Chart
Power-up
Power-up with
LOCK HIGH
Power-up with
LOCK LOW
(default)
Entire NAND Flash
array locked
BLOCK LOCK function
disabled
LOCK-TIGHT Cmd
with
LOCK HIGH
Entire NAND Flash
array locked tight
UNLOCK Cmd with
invert area bit = 1
UNLOCK Cmd with
invert area bit = 0
Locked range
Unlocked range
LOCK
Cmd
LOCK Cmd
Locked range
Unlocked range
UNLOCK Cmd with
invert area bit = 0
UNLOCK Cmd with invert area bit = 1
Unlocked range
UNLOCK Cmd
with invert area
bit = 1
UNLOCK Cmd with invert area bit = 0
LOCK-TIGHT Cmd
with LOCK HIGH
Locked range
LOCK-TIGHT Cmd
with LOCK HIGH
Unlocked range
Locked-tight range
Locked-tight range
Unlocked range
Unlocked range
Locked-tight range
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2Gb x8, x16: NAND Flash Memory
Command Definitions
One-Time Programmable (OTP) Area
This Micron NAND Flash device offers a protected, one-time programmable NAND
Flash memory area. Ten full pages (2,112 bytes per page) of OTP data is available on the
device, and the entire range is guaranteed to be good. The OTP area is accessible only
through the OTP commands. Customers can use the OTP area in any way they desire;
typical uses include programming serial numbers or other data for permanent storage.
In Micron NAND Flash devices, the OTP area leaves the factory in a non-written state (all
bits are “1s”). Programming or partial-page programming enables the user to program
only “0” bits in the OTP area. The OTP area cannot be erased, even if it is not protected.
Protecting the OTP area simply prevents further programming of the OTP area.
While the OTP area is referred to as “one-time programmable,” Micron provides a
unique way to program and verify data—before permanently protecting it and preventing future changes.
OTP programming and protection are accomplished in two discrete operations. First,
using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed
entirely in one operation, or in up to four partial-page programming sequences. Programming can occur on other pages within the OTP area in a similar manner. Second,
the OTP area is permanently protected from further programming using the OTP DATA
PROTECT (A5h-10h) command. The pages within the OTP area can always be read using
the OTP DATA READ (AFh-30h) command, whether or not it is protected.
To determine whether or not the device is busy during an OTP operation, either monitor
R/B# or use the READ STATUS (70h) command.
OTP DATA PROGRAM A0h-10h
The OTP DATA PROGRAM (A0h-10h) command is used to write data to the pages within
the OTP area. An entire page can be programmed at one time, or a page can be partially
programmed up to four times. There is no ERASE operation for the OTP pages.
The OTP DATA PROGRAM command allows programming into an offset of an OTP page,
using the 2 bytes of column address (CA[11:0] for x8 devices or CA[10:0] for x16 devices).
The OTP DATA PROGRAM command will not execute if the OTP area has been protected.
To use the OTP DATA PROGRAM command, issue the A0h command. Issue 5 ADDRESS
cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 3 cycles
select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Next, write from 1 to
2,112 bytes of data. After data input is complete, issue the 10h command. The internal
control logic automatically executes the proper programming algorithm and controls
the necessary timing for programming and verification. Program verification only
detects “1s” that are not successfully written to “0s.”
R/B# goes LOW during the duration of the array programming time (tPROG). The READ
STATUS (70h) command is the only command valid during the OTP DATA PROGRAM
operation. Bit 5 of the status register will reflect the state of R/B#. If bit 7 is “0,” then the
OTP area has been protected; otherwise, it will be a “1.”
When the device is ready, read bit 0 of the status register to determine if the operation
passed or failed (see Table 12 on page 34).
It is possible to program each OTP page a maximum of four times.
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Command Definitions
RANDOM DATA INPUT 85h
After the initial OTP data set is input, additional data can be written to a new column
address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT
command can be used any number of times in the same page prior to issuance of the
OTP PAGE WRITE (10h) command. See Figure 40 for the proper command sequence.
Figure 39:
OTP DATA PROGRAM
CLE
CE#
tWC
WE#
tWB
tPROG
ALE
RE#
I/Ox
A0h
Col
add 1
Col
add 2
OTP
page1
00h
00h
DIN
N
DIN
M
1 up to m bytes
serial input
OTP DATA INPUT
command
10h
70h
PROGRAM
command
READ STATUS
command
Status
R/B#
OTP data written
(following "good" status confirmation)
Don’t Care
Notes: 1. The OTP page must be within the 02h–0Bh range.
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Figure 40:
OTP PROGRAM with RANDOM DATA INPUT
CLE
CE#
tWC
WE#
tWB
tPROG
ALE
RE#
A0h
OTP DATA INPUT
command
R/B#
Col
add 1
Col
add 2
OTP
page1
00h
00h
Col
Col
DIN
DIN
85h
add 2
add 1
N
M
1 up to m bytes RANDOM New column address
serial input
DATA
in selected OTP page
INPUT
command
DIN
P
DIN
Q
10h
70h1
PROGRAM
command
READ STATUS
command
Status
50
OTP data written
(following
"good" status confirmation)
Don’t Care
2Gb x8, x16: NAND Flash Memory
Command Definitions
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I/Ox
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2Gb x8, x16: NAND Flash Memory
Command Definitions
OTP DATA PROTECT A5h-10h
The OTP DATA PROTECT (A5h-10h) command is used to protect all the data in the OTP
area. After the data is protected it cannot be programmed further. When the OTP area is
protected, the pages within the area are no longer programmable and cannot be unprotected.
To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the following 5 ADDRESS cycles: 00h-00h-01h-00h-00h. Finally, issue the 10h command.
R/B# goes LOW while the OTP area is being protected. The protect command duration is
similar to a normal page programming operation, tPROG. The READ STATUS (70h) command is the only command valid during the OTP DATA PROTECT operation. Bit 5 of the
status register will reflect the state of R/B#.
When the device is ready, read bit 0 of the status register to determine if the operation
passed or failed (see Table 12 on page 34).
Figure 41:
OTP DATA PROTECT
CLE
CE#
tWC
WE#
tWB
tPROG
ALE
RE#
I/Ox
Col
00h
A5h
Col
00h
01h
00h
00h
OTP DATA PROTECT
command
10h
70h
PROGRAM
command
READ STATUS
command
Status
R/B#
OTP data protected1
Don’t Care
Notes: 1. OTP data is protected following “good” status confirmation.
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Command Definitions
OTP DATA READ AFh-30h
The OTP DATA READ (AFh-30h) command is used to read data from a page within the
OTP area. An OTP page within the OTP area is available for reading data whether or not
the area is protected.
To use the OTP DATA READ command, issue the AFh command. Next, issue 5 ADDRESS
cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 3 cycles
select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Finally, issue the 30h
command.
R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The
READ STATUS (70h) command and the RESET (FFh) command are the only commands
valid during the OTP DATA READ operation. Bit 5 of the status register will reflect the
state of R/B#. For details, refer to Table 12 on page 34.
Normal READ operation timings apply to OTP read accesses (see Figure 42). Additional
pages within the OTP area can be selected by repeating the OTP DATA READ command.
The RANDOM DATA READ command enables the user to specify a new column address
within the OTP page so the data at single or multiple column addresses can be read. The
random read mode is enabled after a normal OTP DATA READ (AFh-30h) sequence.
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (2 cycles).
The RANDOM DATA READ command can be issued without limit within the OTP page.
Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially
(see Figure 43 on page 53).
Figure 42:
OTP DATA READ Operation
CLE
CE#
WE#
ALE
tR
RE#
I/Ox
AFh
Col
add 1
Col
add 2
OTP
page1
00h
00h
DOUT
N
30h
DOUT
N+1
DOUT
M
Busy
R/B#
Don’t Care
Notes: 1. The OTP page must be within the 02h–0Bh range.
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CLE
CE#
WE#
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tR
RE#
R/B#
2Gb x8, x16: NAND Flash Memory
Command Definitions
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Don’t Care
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Busy
53
Notes: 1. The OTP page must be within the range 02h–0Bh.
DOUT
H
DOUT
P
E0h
Col
add 2
Col
add 1
05h
DOUT
M
DOUT
N+1
DOUT
N
30h
00h
00h
OTP
page1
Col
add 2
Col
add 1
AFh
I/Ox
OTP DATA READ with RANDOM DATA READ
Figure 43:
ALE
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Command Definitions
Features Operations
The GET FEATURES (EEh) and SET FEATURES (EFh) commands are used to alter the
NAND Flash device behavior from the default power-on behavior. These commands use
a 1-byte feature address to determine which feature is to be read or modified. Each feature (in the range of 0 to 255) is defined in the features table (Table 15). The GET FEATURES (EEh) command (see “GET FEATURES EEh” on page 56) simply reads the
parameter in the features table (4 bytes). The SET FEATURES (EFh) command (see “SET
FEATURES EFh” on page 57) places parameters in the features table (4 bytes).
When a feature is set, by default it remains active until the device is power-cycled. It is
volatile. Unless otherwise specified in the features table, once a device is set it remains
set, even if a RESET (FFh) command is issued.
Table 15:
Features
Feature Address
00h
01h
02h–7Fh
80h
81h
82h-FFh
Table 16:
Description
N/A
Timing mode
Reserved
Vendor-specific parameter: Programmable I/O drive strength
Vendor-specific parameter: Programmable R/B# pull-down strength
Reserved
Feature Address 01h: Timing Mode
Subfeature
Parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
Reserved (0)
0
0
0
00h
1,2
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
01h
01h
01h
01h
01h
2
3
3
3
4
P1
Timing mode
Mode 0
(default)
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Notes: 1. The timing-mode feature address is used to change the default timing mode. The timing
mode should be selected to indicate the maximum speed at which the device will receive
commands, addresses, and data cycles. The five supported settings for the timing mode are
shown. The default timing mode is mode 0. The device returns to mode 0 when the device
is power cycled. Supported timing modes are reported in the parameter page.
2. Supported for both 1.8V and 3.3V.
3. Supported for 3.3V only.
4. Not supported.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Table 17:
Feature Address 80h: Programmable I/O Drive Strength
Subfeature
Parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
0
0
1
1
0
1
0
1
00h
01h
02h
03h
1
P1
I/O drive
strength
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Full (default)
Three-quarters
One-half
One-quarter
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Notes: 1. The PROGRAMMABLE DRIVE STRENGTH feature address is used to change the default I/O
drive strength. Drive strength should be selected based on expected loading of the memory bus. This table shows the four supported output drive-strength settings. The default
drive strength is full strength. The device returns to the default drive strength mode when
the device is power cycled. AC timing parameters may need to be relaxed if I/O drive
strength is not set to full.
Table 18:
Feature Address 81h: Programmable R/B# Pull-down Strength
Subfeature
Parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
0
0
1
1
0
1
0
1
00h
01h
02h
03h
1
P1
R/B# pull-down
strength
Full (default)
Three-quarters
One-half
One-quarter
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Notes: 1. The programmable R/B# pull-down strength feature address is used to change the default
R/B# pull-down strength. R/B# pull-down strength should be selected based on expected
loading of R/B#. The four supported pull-down strength settings are shown. The default
pull-down strength is full strength. The device returns to the default pull-down strength
when the device is power cycled.
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2Gb x8, x16: NAND Flash Memory
Command Definitions
GET FEATURES EEh
The GET FEATURES command is used to determine the current settings for the specified
feature address. This command returns the parameter settings, including modifications
made previously with the SET FEATURES function. Figure 44 defines GET FEATURES
behavior and timing.
Figure 44:
GET FEATURES (EEh)
CLE
CE#
WE#
ALE
RE#
I/Ox
EEh
P11
FA
Feature address,
1 cycle
P2
P3
P4
tFEAT
R/B#
Notes: 1. P1–P4 are the parameters for the specified feature address (FA).
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2Gb x8, x16: NAND Flash Memory
Command Definitions
SET FEATURES EFh
The SET FEATURES command is used to set the parameters at a specified feature
address. These parameters are stored in the device until power is cycled. They are
applied to all die on the CE# to which this command is issued.
Figure 45:
SET FEATURES (EFh)
CLE
CE#
WE#
ALE
RE#
I/Ox
EFh
P11
FA
P2
P3
Feature address,
1 cycle
P4
tFEAT
R/B#
Notes: 1. P1–P4 are the parameters for the specified feature address (FA).
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Command Definitions
RESET Operation
RESET FFh
The RESET command is used to put the memory device into a known condition and to
abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy
state. The contents of the memory location being programmed or the block being erased
are no longer valid. The data may be partially erased or programmed, and is invalid. The
command register is cleared and is ready for the next command. The data register and
cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the
command register (see Figure 46 and Table 19).
The RESET command must be issued to all CE#s as the first command after power-on.
The device will be busy for a maximum of 1ms.
Figure 46:
RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
I/Ox
FFh
RESET
command
Table 19:
Status Register Contents After RESET Operation
Condition
Status
WP# HIGH
WP# LOW
Ready
Ready and write protected
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hex
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
E0h
60h
58
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2Gb x8, x16: NAND Flash Memory
Command Definitions
WRITE PROTECT Operation
It is possible to enable and disable PROGRAM and ERASE commands using the WP# pin.
Figures 47 through 50 illustrate the setup time (tWW) required from WP# toggling until a
PROGRAM or ERASE command is latched into the command register. After command
cycle 1 is latched, the WP# pin must not be toggled until the command is complete and
the device is ready (status register bit 5 is “1”).
Figure 47:
ERASE Enable
WE#
tWW
I/Ox
60h
D0h
WP#
R/B#
Figure 48:
ERASE Disable
WE#
tWW
I/Ox
60h
D0h
WP#
R/B#
Figure 49:
PROGRAM Enable
WE#
tWW
I/Ox
80h
10h
(or 15h)
WP#
R/B#
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2Gb x8, x16: NAND Flash Memory
Command Definitions
Figure 50:
PROGRAM Disable
WE#
tWW
I/Ox
80h
10h
(or 15h)
WP#
R/B#
Figure 51:
PROGRAM for INTERNAL DATA MOVE Enable
WE#
tWW
I/Ox
85h
10h
WP#
R/B#
Figure 52:
PROGRAM for INTERNAL DATA MOVE Disable
WE#
tWW
I/Ox
85h
10h
WP#
R/B#
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2Gb x8, x16: NAND Flash Memory
Error Management
Error Management
This NAND Flash device is specified to have the minimum number of valid blocks (NVB)
of the total available blocks per die shown in Table 20. This means the devices may have
blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum
required ECC. Additional bad blocks may develop with use. However, the total number
of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide bad-block management and error-correction algorithms.
This ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad-block mark into every location
in the first page of each invalid block. It may not be possible to program every location in
an invalid block with the bad-block mark. However, the first spare area location in each
bad block is guaranteed to contain the bad-block mark. This method is compliant with
ONFI Factory Defect Mapping requirements. See Table 20 for the bad-block mark.
System software should initially check the first spare area location for non-FFh data on
the first page of each block prior to performing any program or erase operations on the
NAND Flash device. A bad-block table can then be created, enabling system software to
map around these areas. Factory testing is performed under worst-case conditions.
Because invalid blocks may be marginal, it may not be possible to recover the bad-block
marking if the block is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Check status after each PROGRAM and ERASE operation.
• Under typical conditions, use the minimum required ECC shown in Table 20.
• Use bad-block management and wear-leveling algorithms.
The first block (physical block address 00h) for each CE# is guaranteed to be valid with
ECC when shipped from the factory.
Table 20:
Error Management Details
Description
Requirement
Minimum number of valid blocks (NVB)
Total available blocks per die
Minimum required ECC
First spare area location
Bad-block mark
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2,008
2,048
1-bit ECC per 528 bytes of data
x8: byte 2,048
x16: word 1,024
x8: 00h
x16: 0000h
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Electrical Characteristics
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not guaranteed. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Table 21:
Absolute Maximum Ratings
Voltage on any pin relative to VSS
Parameter/Condition
Voltage Input
3.3V
Voltage input
1.8V
VCC supply voltage
3.3V
VCC supply voltage
1.8V
Storage temperature
Short circuit output current, I/Os
Table 22:
Symbol
Min
Max
Unit
VIN
VIN
VCC
VCC
TSTG
–0.6
–0.6
–0.6
–0.6
–65
–
+4.6
+2.4
+4.6
+2.4
+150
5
V
V
V
V
°C
mA
Recommended Operating Conditions
Parameter/Condition
Operating temperature
Extended temperature
VCC supply voltage
VCC supply voltage
Ground supply voltage
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Symbol
Min
Typ
Max
Unit
TA
0
–40
2.7
1.65
0
–
–
3.3
1.8
0
+70
+85
3.6
1.95
0
°C
°C
V
V
V
VCC
VCC
VSS
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
VCC Power Cycling
Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. (The WP# signal permits additional hardware protection during power transitions.) When VCC reaches 2.5V for a 3.3V device or 1.5V for a
1.8V device, a minimum of 100µs should be allowed for the Flash device to initialize
before any commands are executed (see Figures 53 for the states of signals during VCC
power cycling).
Both of the following conditions must be satisfied before R/B# will be valid:
• 50µs have elapsed since Vcc started its ramp.
• 10µs have elapsed since Vcc reached ≈ 2.5V for 3.3V or ≈ 1.5V for 1.8V
The RESET command must be issued to all CE#s as the first command after the NAND
Flash device is powered on. Each CE# will be busy for a maximum of 1ms after a RESET
command is issued.
Each NAND die will draw no more than IST prior to execution of the first RESET command after the device is powered on.
Figure 53:
AC Waveforms During Power Transitions
3V device: ≈ 2.5V
1.8V device: ≈ 1.5V
3V device: ≈ 2.5V
1.8V device: ≈ 1.5V
VCC
CLE
tCS
CE#
WP#
WE#
100μs
(MIN)
ALE
RE#
FFh
I/Ox
1ms
(MAX)
R/B#
10μs
(MAX)
50μs
Don’t Care
(MAX)
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 23:
DC and Operating Characteristics (3.3V)
Parameter
Sequential READ current
PROGRAM current
ERASE current
Standby current (TTL)
Standby current (CMOS)
Staggered power-up
current3
Input leakage current
Output leakage current
Input high voltage
Input low voltage,
all inputs
Output high voltage
Output low voltage
Output low current
Conditions
Symbol
Min
Typ
Max
Unit
RC = tRC (MIN); CE# = VIL;
IOUT = 0mA
–
–
CE# = VIH;
WP# = 0V/VCC
CE# = VCC - 0.2V;
WP# = 0V/VCC
Rise time = 1ms
Line capacitance = 0.1µF
VIN = 0V to VCC
VOUT = 0V to VCC
I/O[7:0], I/O[15:0],
CE#, CLE, ALE, WE#, RE#,
WP#, R/B#
–
ICC1
–
25
35
mA
ICC2
ICC3
ISB1
–
–
–
25
25
–
35
35
1
mA
mA
mA
ISB2
–
10
50
µA
IST
–
–
10 per die
mA
ILI
ILO
VIH
–
–
0.8 x VCC
–
–
–
±10
±10
VCC + 0.3
µA
µA
V
VIL
–0.3
–
0.2 x VCC
V
IOH = –400µA
IOL = 2.1mA
VOL = 0.4V
VOH
VOL
IOL (R/B#)
2.4
–
8
–
–
10
–
0.4
–
V
V
mA
t
Notes
3
1
1
2
Notes: 1. VOH and VOL may need to be relaxed if I/O drive strength is not set to “full.”
2. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to “full.”
3. Measurement is taken with 1ms averaging intervals and begins after Vcc reaches Vcc
(MIN).
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 24:
DC and Operating Characteristics (1.8V)
Parameter
Sequential READ current
PROGRAM current
ERASE current
Standby current (TTL)
Standby current (CMOS)
Staggered power-up
current3
Input leakage current
Output leakage current
Input high voltage
Input low voltage,
all inputs
Output high voltage
Output low voltage
Output low current
Conditions
Symbol
Min
Typ
Max
Unit
RC = RC (MIN); CE# = VIL;
IOUT = 0mA
–
–
CE# = VIH;
LOCK = WP# = 0V/VCC
CE# = VCC - 0.2V;
LOCK = WP# = 0V/VCC
Rise time = 1ms
Line capacitance = 0.1µF
VIN = 0V to VCC
VOUT = 0V to VCC
I/O[7:0], I/O[15:0],
CE#, CLE, ALE, WE#, RE#,
WP#, R/B#, LOCK
–
ICC1
–
10
20
mA
ICC2
ICC3
ISB1
–
–
–
10
10
–
20
20
1
mA
mA
mA
ISB2
–
10
50
µA
IST
–
–
10 per die
mA
ILI
ILO
VIH
–
–
0.8 x VCC
–
–
–
±10
±10
VCC + 0.3
µA
µA
V
VIL
–0.3
–
0.2 x VCC
V
IOH = –100µA
IOL = 100µA
VOL = 0.2V
VOH
VOL
IOL (R/B#)
VCC - 0.1
–
3
–
–
4
–
0.1
–
V
V
mA
t
t
Notes
3
1
1
2
Notes: 1. VOH and VOL may need to be relaxed if I/O drive strength is not set to “full.”
2. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to “full.”
3. Measurement is taken with 1ms averaging intervals and begins after Vcc reaches Vcc
(MIN).
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 25:
Valid Blocks
Parameter
Valid block number
Symbol
Device
Min
Max
Unit
Notes
NVB
MT29F2GxxAxD
2,008
2,048
blocks
1, 2
Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad
blocks upon shipment. Additional bad blocks may develop over time; however, the total
number of available blocks will not drop below NVB during the endurance life of the
device. Do not erase or program blocks marked invalid by the factory.
2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the factory.
Table 26:
Capacitance
Description
Input capacitance
Input/output capacitance (I/O)
Symbol
Max
Unit
Notes
CIN
CIO
10
10
pF
pF
1,2
1.2
Notes: 1. These parameters are verified in device characterization and are not 100 percent tested.
2. Test conditions: Tc = 25°C; f = 1 MHz; VIN = 0V.
Table 27:
Test Conditions
Parameter
Device
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
MT29F2GxxAxD
3.3V
1.8V
Value
Notes
0.0V to VCC
5ns
VCC/2
1 TTL GATE and CL = 50pF
1 TTL GATE and CL = 30pF
1
1
Notes: 1. Verified in device characterization, not 100 percent tested.
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 28:
AC Characteristics: Command, Data, and Address Input (3.3V)
Parameter
Symbol
ALE to data start
ALE hold time
ALE to setup time
CE# hold time
CLE hold time
CLE setup time
CE# setup time
DATA hold time
DATA setup time
WRITE cycle time
WE# pulse width HIGH
WE# pulse width
WP# setup time
tADL
t
ALH
t
ALS
tCH
t
CLH
t
CLS
t
CS
t
DH
tDS
t
WC
tWH
tWP
tWW
Min
Max
Unit
Notes
70
5
10
5
5
10
15
5
10
25
10
12
100
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Notes: 1. Timing for begins tADL begins in the ADDRESS cycle on the final rising edge of WE# and
ends with the first rising edge of WE# for data input.
Table 29:
AC Characteristics: Command, Data, and Address Input (1.8 V)
Parameter
Symbol
Min
Max
Unit
Notes
ALE to data start
ALE hold time
ALE setup time
CE# hold time
CLE hold time
CLE setup time
CE# setup time
Data hold time
Data setup time
WRITE cycle time
WE# pulse width HIGH
WE# pulse width
WP# setup time
tADL
100
4
15
4
5
15
24
4
15
35
15
17
100
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tALH
tALS
tCH
tCLH
tCLS
tCS
tDH
tDS
t
WC
WH
tWP
tWW
t
Notes: 1. Timing for begins tADL begins in the ADDRESS cycle on the final rising edge of WE# and
ends with the first rising edge of WE# for data input.
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 30:
AC Characteristics: Normal Operation (3.3V)
Parameter
Symbol
ALE to RE# delay
CE# access time
CE# HIGH to output High-Z
CLE to RE# delay
CE# HIGH to output hold
Cache busy in page read cache mode (first 31h)
Cache busy in page read cache mode (next 31h and 3Fh)
Output High-Z to RE# LOW
Data transfer from Flash array to data register
READ cycle time
RE# access time
RE# HIGH hold time
RE# HIGH to output hold
RE# HIGH to WE# LOW
RE# HIGH to output High-Z
RE# LOW to output hold
RE# pulse width
Ready to RE# LOW
Reset time (READ/PROGRAM/ERASE)
WE# HIGH to busy
WE# HIGH to RE# LOW
tAR
t
CEA
t
CHZ
tCLR
t
COH
t
DCBSYR1
t
DCBSYR2
t
IR
tR
t
RC
tREA
tREH
tRHOH
tRHW
tRHZ
tRLOH
tRP
tRR
tRST
tWB
tWHR
Min
Max
Unit
Notes
10
–
–
10
15
–
t
DCBSYR1
0
–
25
–
10
15
100
–
5
12
20
–
–
60
–
25
30
–
–
3
25
–
25
–
20
–
–
–
100
–
–
–
5/10/500
100
–
ns
ns
ns
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
1
1
1, 2
1
1
1
1
1
1
1
1
1
1
1
1, 2
1
1
1
1, 3
1, 4
1
Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to “full.”
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will go
busy for a maximum of 1ms. Thereafter, the device goes busy for maximum 5µs.
4. Do not issue a new command during tWB, even if R/B# is ready.
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 31:
AC Characteristics: Normal Operation (1.8V)
Parameter
Symbol
ALE to RE# delay
CE# access time
CE# HIGH to output High-Z
CLE to RE# delay
CE# HIGH to output hold
Cache busy in page read cache mode (first 31h)
Cache busy in page read cache mode (next 31h and 3Fh)
Output High-Z to RE# LOW
Data transfer from Flash array to data register
READ cycle time
RE# access time
RE# HIGH hold time
RE# HIGH to output hold
RE# HIGH to WE# LOW
RE# HIGH to output High-Z
RE# LOW to output hold
RE# pulse width
Ready to RE# LOW
Reset time (READ/PROGRAM/ERASE)
WE# HIGH to busy
WE# HIGH to RE# LOW
tAR
t
CEA
t
CHZ
tCLR
t
COH
t
DCBSYR1
t
DCBSYR2
t
IR
tR
t
RC
tREA
tREH
tRHOH
tRHW
tRHZ
tRLOH
tRP
tRR
tRST
tWB
tWHR
Min
Max
Unit
Notes
10
–
–
10
15
–
t
DCBSYR1
0
–
35
–
15
15
100
–
0
17
20
–
–
80
–
30
45
–
–
3
25
–
25
–
24
–
–
–
100
–
–
–
5/10/500
100
–
ns
ns
ns
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
1
1
1, 2
1
1
1
1
1
1
1
1
1
1
1
1, 2
1
1
1
1, 3
1, 4
1
Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to “full.”
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will go
busy for a maximum of 1ms. Thereafter, the device goes busy for maximum 5µs.
4. Do not issue a new command during tWB, even if R/B# is ready.
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2Gb x8, x16: NAND Flash Memory
Electrical Characteristics
Table 32:
PROGRAM/ERASE Characteristics
Symbol
Parameter
Typ
Max
Unit
Notes
NOP
BERS
t
CBSY
tCBSY
t
FEAT
t
FEAT
t
LBSY
t
LPROG
tOBSY
t
PROG
tPROG
Number of partial page programs
BLOCK ERASE operation time
Busy time for PROGRAM CACHE operation (3.3V)
Busy time for PROGRAM CACHE operation (1.8V)
Busy time for SET FEATURES and GET FEATURES operations (3.3V)
Busy time for SET FEATURES and GET FEATURES operations (1.8V)
Busy time for PROGRAM/ERASE on locked block
LAST PAGE PROGRAM operation time
Busy time for OTP DATA PROGRAM operation if OTP is protected
PAGE PROGRAM operation time (1.8V)
PAGE PROGRAM operation time (3.3V)
–
0.5
3
3
–
–
–
–
–
300
220
4
3
500
600
1
3
3
–
30
600
500
cycles
ms
µs
µs
µs
µs
µs
–
µs
µs
µs
1
t
Notes: 1.
2.
3.
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2
2
3
Four total partial-page programs to the same page.
MAX time depends on timing between internal program completion and data-in.
tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) address load time (last page) - data load time (last page).
tCBSY
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Timing Diagrams
Figure 54:
COMMAND LATCH Cycle
CLE
tCLS
tCS
tCLH
tCH
CE#
tWP
WE#
tALS
tALH
tDS
tDH
ALE
I/Ox
COMMAND
Don’t Care
Note:
Figure 55:
x16: I/O[15:8] must be set to “0.”
ADDRESS LATCH Cycle
CLE
tCLS
tCS
CE#
tWC
tWP
tWH
WE#
tALS
tALH
ALE
tDS tDH
I/Ox
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Don’t Care
Note:
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Row
add 3
Undefined
x16: I/O[15:8] must be set to “0.”
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 56:
INPUT DATA LATCH Cycle
CLE
tCLH
CE#
tALS
tCH
ALE
tWC
tWP
tWP
tWP
WE#
tWH
tDS tDH
tDS tDH
tDS tDH
DIN 1
DIN Final1
DIN 0
I/Ox
Don’t Care
Notes: 1. DIN Final = 2,111 (x8).
Figure 57:
SERIAL ACCESS Cycle After READ
tCEA
CE#
tREA
tREA
tRP
tCHZ
tREA
tREH
tCOH
RE#
tRHZ
tRHZ
tRHOH
DOUT
I/Ox
tRR
DOUT
DOUT
tRC
R/B#
Don’t Care
Note:
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Use this timing diagram for tRC ≥ 30ns.
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 58:
Serial Access Cycle After READ (EDO Mode)
CE#
tRC
tRP
tCHZ
tREH
tCOH
RE#
tRHZ
tREA
tREA
tRLOH
tCEA
tRHOH
DOUT
I/Ox
DOUT
DOUT
tRR
R/B#
Don’t Care
Figure 59:
READ STATUS Operation
tCLR
CLE
tCLS tCLH
tCS
CE#
tWP
tCH
WE#
tCEA
tWHR
tRP
RE#
tRHZ
tRHOH
tDS tDH
I/Ox
tCHZ
tCOH
tIR
tREA
Status
output
70h
Don’t Care
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 60:
PAGE READ Operation
CLE
tCLR
CE#
tWC
WE#
tWB
tAR
ALE
tR
tRC
tRHZ
RE#
tRR
I/Ox
00h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
tRP
DOUT
N
30h
DOUT
N+1
DOUT
M
Busy
R/B#
Don’t Care
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READ Operation with CE# “Don’t Care”
CLE
CE#
RE#
ALE
tR
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Figure 61:
R/B#
WE#
tCEA
CE#
Don’t Care
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Micron Confidential and Proprietary
75
Out
I/Ox
tCHZ
tREA
tCOH
RE#
Data output
30h
Address (5 cycles)
00h
I/Ox
RANDOM DATA READ Operation
CLE
tCLR
CE#
WE#
R/B#
Busy
76
Don’t Care
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
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Column address M
Column address N
DOUT
M+1
DOUT
M
E0h
Col
add 2
Col
add 1
05h
DOUT
N+1
DOUT
N
30h
Row
add 3
Row
add 2
Row
add 1
Col
add 2
Col
add 1
00h
I/Ox
tREA
tRC
tR
tWHR
tRHW
tAR
tWB
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Figure 62:
ALE
RE#
tRR
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Figure 63:
PAGE READ CACHE MODE Operation, Part 1 of 2
CLE
tCLS tCLH
tCS
tCH
CE#
tWC
WE#
tCEA
tRHW
ALE
tRC
tWB
tR
tREA
tDS tDH
I/Ox
00h
tRR
Col
add 1
Col
add 2
Column address
00h
Row
add 1
Row
add 2
Row
add 3
Page address
M
30h
DOUT
0
31h
tDCBSYR1
DOUT
1
DOUT
0
31h
DOUT
Page address
M
tDCBSYR2
Page address
M+1
77
R/B#
Column Address 0
Column address 0
1
Don’t Care
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
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Continued to 1
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RE#
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Figure 64:
PAGE READ CACHE MODE Operation, Part 2 of 2
CLE
tCLS
tCLH
tCS
tCH
CE#
WE#
tRHW
tCEA
tRHW
ALE
tRC
tWB
tDS tDH
I/Ox
tRR
DOUT
0
31h
DOUT
tREA
tDCBSYR2
DOUT
1
Page address
M+1
DOUT
DOUT
0
31h
tDCBSYR2
DOUT
1
Page address
M+2
DOUT
DOUT
0
3Fh
tDCBSYR2
DOUT
1
DOUT
Page address
M+x
78
R/B#
Column address 0
1
Column address 0
Column address 0
Don’t Care
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
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RE#
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2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 65:
PAGE READ CACHE MODE Operation Without R/B#, Part 1 of 2
CLH
CH
tWC
tRHW
tCEA
tRC
tREA
DH
h
Col
add 1
Col
add 2
Column address
00h
Row
add 1
Row
add 2
Row
add 3
Page address
M
30h
70h
Status
I/O 5 = 0, Busy
= 1, Ready
31h
70h
Status
00h
I/O 6 = 0, Cache busy
= 1, Cache ready
DOUT
0
DOUT
1
DOUT
31h
Page address
M
70h
Status
00
I/O 6 = 0, Cache busy
= 1, Cache read
Column address 0
Colu
1
Continued to 1
of next page
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Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 66:
CLS
tCLH
CS
tCH
PAGE READ CACHE MODE Operation Without R/B#, Part 2 of 2
tRHW
tCEA
tRC
tDS tDH
31h
tREA
70h
Status
00h DOUT
0
DOUT
1
DOUT
Page address
M+1
I/O 6 = 0, Cache busy
= 1, Cache ready
31h
70h
Status
00h
DOUT
0
DOUT
Page address
M+2
I/O 6 = 0, Cache busy
= 1, Cache ready
Column address 0
DOUT
1
3Fh
70h
Status
00h DOUT
0
I/O 6 = 0, Cache busy
= 1, Cache ready
Column address 0
DO
1
Page
M
Column address 0
om 1
page
Figure 67:
READ ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tWHR
I/Ox
90h
00h
tREA
Byte 1
Byte 0
Byte 2
Byte 3
Byte 4
(or 20h)
Address, 1 cycle
Note:
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
See Table 9 on page 30 for actual values.
80
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©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 68:
PROGRAM PAGE Operation
CLE
CE#
tWC
tADL
WE#
tWB
tPROG
tWHR
ALE
RE#
I/Ox
80h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
SERIAL DATA
INPUT command
Row
add 3
DIN
N
DIN
M
1 up to m Byte
serial input
10h
70h
PROGRAM
command
READ STATUS
command
Status
R/B#
Don’t Care
Figure 69:
Program Operation with CE# “Don’t Care”
CLE
CE#
WE#
ALE
I/Ox
80h
Address (5 cycles)
Data
input
tCS
Data
input
10h
tCH
CE#
tWP
WE#
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
Don’t Care
81
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NDA_2gb_nand_m59a__2.fmRev. A 8/08 EN
Figure 70:
PROGRAM PAGE Operation with RANDOM DATA INPUT
CLE
CE#
tWC
tADL
tADL
WE#
tWB
tPROG
tWHR
ALE
RE#
80h
SERIAL DATA
INPUT command
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
DIN
N
DIN
N+1
85h
Col
add 1
Col
add 2
RANDOM DATA Column address
Serial input INPUT command
DIN
N
DIN
N+1
Serial input
Status
10h
70h
PROGRAM
command
READ STATUS
command
R/B#
Don’t Care
82
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
I/Ox
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 71:
INTERNAL DATA MOVE Operation
CLE
CE#
tADL
tWC
WE#
tWB tPROG
tWB
tWHR
ALE
RE#
I/Ox
tR
00h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
35h
85h
Col
Col
Row Row Row
add 1 add 2 add 1 add 2 add 3
Data
1
Data
N
Busy
10h
Status
70h
Busy
READ
STATUS
R/B#
INTERNAL
DATA MOVE
Don’t Care
Figure 72:
PROGRAM PAGE CACHE MODE Operation
CLE
CE#
tADL
tWC
WE#
tWB tLPROG
tWBtCBSY
tWHR
ALE
RE#
I/Ox
80h
Col
Col
Row Row Row
add 1 add 2 add 1 add 2 add 3
SERIAL DATA
INPUT
DIN
DIN
15h
N
M
Serial input PROGRAM
80h
Col
Col
Row Row Row
add 1 add 2 add 1 add 2 add 3
DIN
N
DIN 10h
M
PROGRAM
70h
Status
R/B#
Last page - 1
Last page
Don’t Care
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
83
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 73:
PROGRAM PAGE CACHE MODE Operation Ending on 15h
tADL
tADL
tWHR
Row Row Row
Col
Col
dd 1 add 2 add 1 add 2 add 3
DIN 15h 70h
DIN
N
M
Serial input PROGRAM
Status
80h
Col Row Row Row
Col
add 1 add 2 add 1 add 2 add 3
DIN
N
DIN
M
15h
Status
70h
PROGRAM
Last page – 1
Last page
Poll status until:
I/O6 = 1, Ready
Figure 74:
70h
tW
To verify successful completio
I/O5 =
1, Ready
I/O0 =
0, Last page PRO
I/O1 =
0, Last page – 1 P
BLOCK ERASE Operation
CLE
CE#
tWC
WE#
tWB
tWHR
ALE
RE#
tBERS
I/Ox
60h
Row
add 1
Row
add 2
Row
add 3
Row address
D0h
70h
ERASE
command
READ STATUS
command
Status
Busy
R/B#
I/O0 = 0, Pass
I/O0 = 1, Fail
AUTO BLOCK ERASE
SETUP command
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
84
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Timing Diagrams
Figure 75:
RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
I/Ox
FFh
RESET
command
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Package Dimensions
Package Dimensions
Figure 76:
48-Pin TSOP Package
0.25 for
reference only
0.50 for
reference only
20.00 ±0.25
18.40 ±0.08
48
1
Mold compound:
Epoxy novolac
Plated lead finish:
100% Sn
Package width and length do
not include mold protrusion.
Allowable protrusion is
0.25 per side.
12.00 ±0.08
0.27 MAX
0.17 MIN
24
25
0.10
0.15
+0.03
-0.02
See detail A
0.25
1.20 MAX
Gage
plane
0.10
+0.10
-0.05
0.50 ±0.1
0.80
Detail A
Note:
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
All dimensions are in millimeters.
86
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Package Dimensions
Figure 77:
63-Ball VFBGA Package
0.65 ±0.05
Seating
plane
Solder ball material:
96.5% Sn, 3%Ag, 0.5% Cu
A
0.10 A
Substrate material: Plastic laminate
Mold compound: Epoxy novolac
7.20
63X Ø0.45
Dimensions
apply to solder
balls post reflow.
Pre-reflow ball
is Ø0.42 on a Ø0.4
SMD ball pad.
0.80 TYP
Ball A1 ID
Ball A1 ID
Ball A1
Ball A10
0.80 TYP
CL
8.80
13.00 ±0.10
4.40
6.50 ±0.05
CL
3.60
1.00 MAX
5.25 ±0.05
10.50 ±0.10
Note:
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
All dimensions are in millimeters.
87
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb x8, x16: NAND Flash Memory
Revision History
Revision History
Rev. A, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08
• Initial release.
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NDA_2gb_nand_m59a__2.fm - Rev. A 8/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.