Preliminary‡ MT9V135: SOC VGA Digital Image Sensor Features 1/4-Inch System-On-A-Chip (SOC) VGA NTSC/PAL CMOS Digital Image Sensor MT9V135C12STC (Pb-Free CLCC) Features Table 1: Micron® DigitalClarity® CMOS imaging technology • • System-On-a-Chip (SOC)—Completely integrated camera system • NTSC/PAL (true two field) analog composite video output • ITU-R BT.656 parallel output (8-bit, interlaced) • Simultaneous composite and digital video outputs (simplifies focus and setup of network cameras • Serial LVDS data output • Low power, interlaced scan CMOS image sensor • Supports use of external devices for addition of custom overlay graphics • Superior low-light performance • On-chip image flow processor (IFP) performs sophisticated processing • Color recovery and correction, sharpening, gamma, lens shading correction, and on-the-fly defect correction • Automatic features: – Auto exposure – Auto white balance (AWB) – Auto black reference (ABR) – Auto flicker avoidance – Auto color saturation – Auto defect identification and correction • Simple two-wire serial programming interface Parameter 1/4-inch (4:3) 3.63mm(H) x 2.78mm(V) 4.57mm diagonal Active pixels 640H x 480V NTSC output 720H x 486V PAL output 720H x 576V Pixel size 5.6µm x 5.6µm Color filter array RGB Paired Bayer pattern Shutter type Electronic rolling shutter (ERS) Maximum data rate 13.5 Mp/s master clock 27 MHz Frame rate (VGA 640H x 30 fps at 27 MHz (NTSC) 480V) 25 fps at 27 MHz (PAL) Integration time 16µs–33ms (NTSC) (composite video output) 16µs–40ms (PAL) ADC resolution 10-bit, on-chip Responsivity 5 V/lux-sec (550nm) Pixel dynamic range 70dB 39dB SNRMAX Supply I/O digital 2.5–3.1V (2.8V nominal) voltage Core digital 2.5–3.1V (2.8V nominal) Analog 2.5–3.1V (2.8V nominal) Power consumption 320 mW @ 2.8V, 25°C Operating temperature1 –30°C to +70°C Packaging 48-pin CLCC Note: 1. Customers requiring a similar part with greater temperature range should consider using the Micron MT9V125. Security cameras 900 MHz and 2.4 GHz wireless cameras Composite video and digital video cameras CCTV security cameras Smart cameras Evidence quality cameras Cameras using active or passive overlay 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_1.fm - Rev. B 3/07 EN Typical Value Optical format Active imager size Applications • • • • • • • Key Performance Parameters Table 2: Ordering Information Part Number MT9V135C12STC ES MT9V135C12STCD MT9V135C12STCH 1 Description 48-pin CLCC ES, Pb-Free Demo kit Demo kit headboard Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. Preliminary MT9V135: SOC VGA Digital Image Sensor General Description General Description The MT9V135 is a VGA CMOS image sensor featuring Micron’s breakthrough DigitalClarity technology—a low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low power, and integration advantages of CMOS. The MT9V135 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correction, auto white balance (AWB), and on-the-fly defect identification and correction. The MT9V135 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and PAL video formats. The MT9V135 includes digital video output that can be switched to the NTSC/PAL encoder. This can be used in conjunction with an external DSP to provide an overlay (such as a logo or a menu screen) on top of the live video. The image data can be output on any one of three output ports: • Composite analog video (support for both single-ended and differential) • Low-voltage differential signalling (LVDS) • CCIR 656 interlaced digital video in parallel 8-bit format Table 3: Figure 1: MT9V135 Detailed Performance Parameters Parameter Value Output Gain Read Noise Dark Current 28 e-/LSB 5.3 e-RMS at 16X 1600 e-/pix/s at 70°C MT9V135 Quantum Efficiency vs. Wavelength 60 Quantum Efficiency [%] 50 40 30 20 10 0 350 450 550 650 750 850 950 1050 Wavelength [nm] PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Functional Overview Functional Overview The MT9V135 is a fully-automatic, single-chip camera, requiring only a single power supply, lens, and clock source for basic operation. Output video is streamed via the chosen output port. The MT9V135 internal registers are configured using a two-wire serial interface. The device can be put into a low-power sleep mode by asserting STANDBY and shutting down the clock. Output signals can be tri-stated. Both tri-stating output signals and entry into standby mode can be achieved via two-wire serial interface register writes. The MT9V135 requires an input clock of 27 MHz to support correct NTSC or PAL timing. Internal Architecture Internally, the MT9V135 consists of a sensor core and an image flow processor (IFP). The IFP is divided in two sections: the colorpipe, and the camera controller. The sensor core captures raw images that are then input into the IFP. The colorpipe section processes the incoming stream to create interpolated, color-corrected output, and the camera controller section controls the sensor core to maintain the desired exposure and color balance. The IFP scales the image and an integrated video encoder generates either NTSC or PAL analog composite output. The MT9V135 supports three different output ports; analog composite video out, LVDS serial out and CCIR 656 interlaced digital video in parallel 8bit format. Figure 2 shows the major functional blocks of the MT9V135. The built-in NTSC/PAL encoder and the LVDS Formatter allow simultaneous outputs of composite and digital video signals. This is especially useful during installation of network cameras and allows the installer to adjust the camera view and focus using analog monitoring equipment while the digital viedo is compressed and formatted for IP network delivery. Figure 2: Functional Block Diagram Sensor Core SCLK SDATA Pixel Data . 640H x 480V . 1/4-inch optical format . True interlaced readout . Auto black compensation . Programmable analog gain . Programmable exposure . 10-bit ADC EXTCLK STANDBY SRAM Line Buffers LVDS_OUT_POS LVDS Formatter and Driver LVDS_OUT_NEG NTSC/PAL Encoder and DAC DAC_OUT_NEG Control Bus Control Bus + Sensor control (gains, shutter, etc.) DIN[7:0] DAC_OUT_POS DIN_CLK Image Flow Processor Camera Control VDD/DGND VAA /AGND VAAPIX PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN Control Bus Auto exposure Auto white balance Flicker detect/avoid Image Data 3 Image Flow Processor Colorpipe Lens shading correction Color interpolation Defect correction Color correction Horizontal Interpolator Gamma correction Color conversion + formatting DOUT0[7:0] PIXCLK FRAME_VALID LINE_ VALID Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Functional Overview Figure 3 shows a typical application using a DSP to produce a video overlay (such as a logo or menu text). The parallel digital video output is sent to the DSP, which adds the overlay. The digital video with the overlay is then looped back into the MT9V135 to the NTSC/PAL encoder and LVDS formatter to provide simultaneous composite analog and digital LVDS outputs. Figure 3: Typical Usage Configuration with Overlay NTSC/PAL composite analog output with overlay DIN_CLK PIXCLK MT9V135 DOUT[7:0] DIN[7:0] Parallel digital (CCIR 656) 27MHz Oscillator PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 4 DSP Parallel digital signal with overlay (CCIR 656) Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Typical Connections Typical Connections Figure 4 shows a detailed MT9V135 device configuration. For low-noise operation, the MT9V135 requires separate analog and digital power supplies. Incoming digital and analog ground conductors can be tied together next to the die. Power supply voltages VAA (the primary analog voltage) and VAAPIX (the main voltage to the pixel array) must be tied together to avoid current loss. Both power supply rails should be decoupled from ground using capacitors. The MT9V135 requires a single external voltage supply level. Typical Configuration (without use of overlay) VAA AND VAAPIX5 Power VDD VDD_DAC VDD_PLL VAA 1.5KΩ2 SADDR STANDBY from Controller or Digital GND 2.8KΩ CLKIN Two-Wire Serial Interface SDATA SCLK LVDS_POS LVDS_NEG LVDS_ENABLE 1KΩ DIN_CLK DIN[7:0] HORIZ_FLIP NTSC_PAL_SELECT DOUT[7:0] DOUT_LSB[1:0] PIXCLK LINE_VALID FRAME_VALID PEDESTAL RSVD RESET# 10µF 0.1µF DGND AGND DGND AGND VAAPIX VDD 1µF VAA 1µF 0.1µF AGND DGND PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 75Ω Terminated Receiver DAC_REF STANDBY1 Master Clock Notes: VAAPIX DAC_POS DAC_NEG 75Ω 1.5KΩ2 VDD VDD_DAC VDD_PLL Power Power Power 75Ω Figure 4: 1µF 0.1µF AGND 1. MT9V135 STANDBY can be connected to customer’s ASIC controller directly or to Digital GND, depending on the controller’s capability. 2. A 1.5KΩ resistor value is recommended, but may be greater for slower (for example, 100Kb) two-wire speed. 3. LVDS_ENABLE should be tied HIGH if LVDS is to be used. 4. Pull down DAC_REF with a 2.8K ohm resistor for 1.0V peak-to-peak video output. For a 1.4V peak-to-peak video output, change the video resistor to 2.4K ohms. 5. VAA and VAAPIX must be tied to the same potential for proper operation. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Typical Connections DIN[7] DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[3] DOUT[2] DOUT[1] DOUT[0] DOUT_LSB1 DOUT_LSB0 PIXCLK 48-pin CLCC Assignment 6 5 4 3 2 1 48 47 46 45 44 43 9 40 VDDPLL DIN[3] 10 39 LVDS_POS DIN[2] 11 38 LVDS_NEG DIN[1] 12 37 DGND DIN[0] 13 36 VDD DIN_CLK 14 35 DAC_POS DGND 15 34 VDDDAC VDD 16 33 DAC_NEG CLK_IN 17 32 DGND STANDBY 18 31 DAC_REF Table 4: 21 22 23 24 25 26 27 28 29 30 VAAPIX 20 SDATA 19 AGND DIN[4] VAA LV PEDESTAL 41 LVDS_ENABLE 8 NTSC_PAL_SELECT DIN[5] HORIZ_FLIP FV RSVD 42 SADDR 7 SCLK DIN[6] RESET_BAR Figure 5: Pin Descriptions Pin Assignment Name Type 17 19 22 23 21 18 EXTCLK RESET_BAR SADDR RSVD SCLK STANDBY Input Input Input Input Input Input 24 HORIZ_FLIP Input 25 NTSC_PAL_SELECT Input PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN Description Master clock in sensor. Active LOW: asynchronous reset. Two-wire serial interface device ID selection 1:0xBA, 0:0x90. Must be attached to DGND. Two-wire serial interface clock. Multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). If “0” at reset: Default horizontal setting. If “1” at reset: Flips the image readout format in the horizontal direction. If “0” at reset: Default NTSC mode. If “1” at reset: Default PAL mode. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Typical Connections Table 4: Pin Descriptions (continued) Pin Assignment Name Type Description 27 PEDESTAL Input 26 LVDS_ENABLE Input 6, 7, 8, 9, 10, 11, 12, 13 14 20 5, 4, 3, 2, 1, 48, 47, 46 44 DIN[7:0] Input If “0” at reset: Does not add pedestal to composite video output. If “1” at reset: Adds pedestal to composite video output. Valid for NTSC only, pull low for PAL operation. Active HIGH: Enables the LVDS output port. Must be HIGH if LVDS is to be used. External data input port selectable at video encoder input. DIN_CLK SDATA DOUT[7:0] Input Output Output DOUT_LSB0 Output 45 DOUT_LSB1 Output 42 41 43 35 FRAME_VALID LINE_VALID PIXCLK DAC_POS Output Output Output Output 33 31 39 38 29 15, 32, 37 28 30 16, 36 34 40 DAC_NEG DAC_REF LVDS_POS LVDS_NEG AGND DGND VAA VAAPIX VDD VDDDAC VDDPLL Output Output Output Output Supply Supply Supply Supply Supply Supply Supply Notes: PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN DIN capture clock. (This clock must be synchronous to CLK_IN.) Two-wire serial interface data I/O. Pixel data output DOUT7 (most significant bit (MSB)), DOUT0 (least significant bit (LSB)). Data output [9:2] in sensor stand-alone mode. Sensor stand-alone mode output 0—typically left unconnected for normal SOC operation. Sensor stand-alone mode output 1—typically left unconnected for normal SOC operation. Active HIGH: FRAME_VALID; indicates active frame. Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. Pixel clock output. Positive video DAC output in differential mode. Video DAC output in single-ended mode. Negative video DAC output in differential mode. External reference resistor for video DAC. LVDS positive output. LVDS negative output. Analog ground. Digital ground. Analog power: 2.5V–3.1V (2.8V nominal). Pixel array analog power supply: 2.5V–3.1V (2.8V nominal). Digital power: 2.5V-3.1V (2.8V nominal). DAC power: 2.5V-3.1V (2.8V nominal). LVDS PLL power: 2.5V-3.1V (2.8V nominal). 1. ALL power pins (VDD/VDDDAC/VDDPLL/VAA/VAAPIX) must be connected to 2.8V (nominal). Power pins cannot be floated. 2. ALL ground pins (AGND/DGND) must be connected to ground. Ground pins cannot be floated. 3. Inputs are not tolerant to signal voltages above 3.1V. 4. All unused inputs must be tied to GND or VDD. 5. VAA and VAAPIX must be tied to the same potential for proper operation. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Detailed Architecture Overview Sensor Core The sensor consists of a pixel array of 695 x 512, an analog readout chain, 10-bit ADC with programmable gain and black offset, and timing and control, as illustrated in Figure 6. Figure 6: Sensor Core Block Diagram Active Pixel Sensor (APS) Array Control Register Communication Bus to IFP Timing and Control Clock Sync Signals ADC Analog Processing 10-Bit Data to IFP There are 649 columns by 498 rows of optically-active pixels that include a pixel boundary around the VGA (640 x 480) image to avoid boundary effects during color interpolation and correction. The one additional active column and two additional active rows are used to enable horizontally and vertically mirrored readout to start on the same color pixel. Figure 7 on page 9 illustrates the process of capturing the image. The original scene is flipped and mirrored by the sensor optics. Sensor readout starts at the lower right hand corner. The image is presented in true orientation by the output display. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Figure 7: Image Capture Example SCENE (Front view) fI so es oc Pr e ag m in er th Ga OPTICS g d an (Rear view) e IMAGE CAPTURE ag Im IMAGE SENSOR isp D Row by Row y la Start Rasterization Start Readout IMAGE RENDERING DISPLAY (Front view) The sensor core uses a paired RGB Bayer color pattern, as shown in Figure 9 on page 11. Row pairs consist of the following: rows 0, 1, rows 2, 3, rows 4, 5, and so on. The evennumbered row pairs (0/1, 4/5, and so on) in the active array contain green and red pixels. The odd-numbered row pairs (2/3, 6/7, and so on) contain blue and green pixels. The odd-numbered columns contain green and blue pixels; even-numbered columns contain red and green pixels. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Figure 8: Pixel Color Pattern Detail (top right corner) Column Readout Direction .. . Row Readout Direction ... Black Pixels G R G R G R G G R G R G R G B G B G B G B B G B G B G B G R G R G R G G R G R G R G First Active Border Pixel (42, 13) Output Data Format The sensor core image data is read out in an interlaced scan order. Progressive readout— which is not supported by the color pipe—is an option, but is intended only for raw data output. Valid image data is surrounded by horizontal and vertical blanking, shown in Figure 9 on page 11. For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of the image field. For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical size is 288 pixels per field; 240 image pixels with 24 dark pixels at the top of the image and 24 dark pixels at the bottom of the image field. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Figure 9: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P2,0 P2,1 P2,2.....................................P2,n-1 P2,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE ODD FIELD HORIZONTAL BLANKING Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL EVEN BLANKING VERTICAL/HORIZONTAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 P1,0 P1,1 P1,2.....................................P1,n-1 P1,n P3,0 P3,1 P3,2.....................................P3,n-1 P3,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE EVEN FIELD HORIZONTAL BLANKING Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n 00 00 00 .................. 00 00 00 PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL ODD BLANKING VERTICAL/HORIZONTAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Image Flow Processor The MT9V135 IFP consists of a color processing pipeline, and a measurement and control logic block (the camera controller). The stream of raw data from the sensor enters the pipeline and undergoes several transformations. Image stream processing starts with conditioning the black level and applying a digital gain. The lens shading block compensates for signal loss caused by the lens. Next, the data is interpolated to recover missing color components for each pixel. The resulting interpolated RGB data passes through the current color correction matrix (CCM), gamma, and saturation corrections, and is formatted for final output. The measurement and control logic continuously accumulate image brightness and color statistics. Based on these measurements, the IFP calculates updated values for exposure time and sensor analog gains that are sent to the sensor core through the control bus. Black Level Conditioning The sensor core black level calibration works to maintain black pixel values at a constant level, independent of analog gain, reference current, voltage settings, and temperature conditions. If this black level is above zero, it must be reduced before color processing can begin. The black level subtraction block in the IFP re-maps the black level of the sensor to zero prior to lens shading correction. Following lens shading correction, the black level addition block provides capability for another black level adjustment. However, for good contrast, this level should be set to zero. Digital Gain Controlled by auto exposure logic, the input digital gain stage amplifies the raw image in low-light conditions. (Range: x1–x8). Test Pattern A built-in test pattern generator produces a test image stream that can be multiplexed with the gain stage. The test pattern can be selected through register settings. Lens Shading Correction Inexpensive lenses tend to attenuate image intensity near the edges of pixel arrays. Other factors also cause signal and coloration differences across the image. The net result of all these factors is known as lens shading. Lens shading correction (LC) compensates for these differences. Typically, the profile of lens shading induced anomalies across the frame is different for each color component. Lens shading correction is independently calibrated for the color channels. Interpolation and Aperture Correction A demosaic engine converts the single color per pixel Bayer data from the sensor into RGB (10-bit per color channel). The demosaic algorithm analyzes neighboring pixels to generate a best guess for the missing color components. Edge sharpness is preserved as much as possible. Aperture correction sharpens the image by an adjustable amount. Sharpening can be programmed to phase out as light levels drop to avoid amplifying noise. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Defect Correction This device supports 2D defect correction. In 2D defect detection/correction, pixels with values different from their neighbors by greater than a defined threshold are considered defects unless near the image boundary. The approach is termed 2D, as pixels on neighboring lines as well as neighboring pixels on the same line are considered in both detection and correction. Color Correction To obtain good color rendition and saturation, it is necessary to compensate for the differences between the spectral characteristics of the imager color filter array and the spectral response of the human eye. This compensation, also known as color separation, is achieved through linear transformation of the image with a 3 x 3 element color correction matrix. The optimal values for the color correction coefficients depend on the spectra of the incident illumination and can be programmed by the user. Color Saturation Control Both color saturation and sharpness enhancement can be set by the user, or adjusted automatically by tracking the magnitude of the gains used by the auto exposure algorithm. Automatic White Balance The MT9V135 has a built-in AWB algorithm designed to compensate for the effects of changing scene illumination on the quality of the color rendition. This sophisticated algorithm consists of two major submodules: • A measurement engine (ME) performing statistical analysis of the image. • A module selecting the optimal color correction matrix and analog color channel gains in the sensor core. While the default algorithm settings are adequate in most situations, the user can reprogram base color correction matrices and limit color channel gains. The AWB does not attempt to locate the brightest or grayest elements in the image; it performs in-depth image analysis to differentiate between changes in predominant spectra of illumination and changes in predominant scene colors. Factory defaults are suitable for most applications; however, a wide range of algorithm parameters can be overwritten by the user through the serial interface. Auto Exposure The auto exposure algorithm performs automatic adjustments to image brightness by controlling exposure time and analog gains in the sensor core, as well as digital gain applied to the image. The algorithm relies on the auto exposure measurement engine that tracks speed and amplitude changes in the overall luminance of selected windows in the image. Back light compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. Other algorithm features include fast-fluctuating illumination rejection (time averaging), response-speed control, and controlled sensitivity to small changes. While the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters as described above. The auto exposure algorithm enables compensation for a broad range of illumination intensities. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_2.fm - Rev. B 3/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Electrical Specifications Electrical Specifications Table 5: Electrical Characteristics and Operating Conditions TA = 25°C Parameter1 I/O and core digital voltage (VDD) LVDS PLL voltage Video DAC voltage Analog voltage (VAA) Pixel supply voltage (VAAPIX) Leakage current Imager operating temperature2 Storage temperature Notes: Table 6: Condition Min Typ Max Unit N/A N/A N/A N/A N/A STANDBY, no clocks N/A N/A 2.5 2.5 2.5 2.5 2.5 2.8 2.8 2.8 2.8 2.8 3.1 3.1 3.1 3.1 3.1 10 +70 +125 V V V V V µA °C °C –30 –30 1. VDD, VAA, and VAAPIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. 2. Customers requiring a similar part with greater temperature range should consider using the Micron MT9V125. Video DAC Electrical Characteristics TA = 25°C; All table values are estimates until the block is tested and characterized Parameter Resolution DNL INL Output local oad Output voltage Output current DNL INL Output local load Output voltage Output voltage Differential output mid level Supply current Condition Min Single-ended mode Single-ended mode Single-ended mode, output pad (DAC_POS) Single-ended mode, unused output (DAC_NEG) Single-ended mode, code 000h Single-ended mode, code 3FFh Single-ended mode, code 000h Single-ended mode, code 3FFh Differential mode Differential mode Differential mode per pad (DAC_POS and DAC_NEG) Differential mode, code 000h, pad dacp Differential mode, code 000h, pad dacn Differential mode, code 3FFh, pad dacp Differential mode, code 3FFH, pad dacn Differential mode, code 000h, pad dacp Differential mode, code 000h, pad dacn Differential mode, code 3FFh, pad dacp Differential mode, code 3FFH, pad dacn Differential mode PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_3.fm - Rev. B 3/07 EN Estimate Typ 10 0.8 5.7 75 0 0.02 1.42 0.6 37.9 0.7 1.4 37.5 Max 1.1 8.1 1 3 0.37 1.07 1.07 0.37 0.6 37.9 37.9 0.6 0.72 bits bits bits Ohm Ohm V V mA mA bits bits Ohm V V V V mA mA mA mA V 55 14 Unit mA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Electrical Specifications Table 7: Signal Digital I/O Parameters Parameter Definition All Outputs All Inputs EXTCLK Condition Load capacitance Output signal slew Output high voltage Output low voltage Output high current Output low current Input high voltage Input low voltage Input leakage current Input signal capacitance Master clock frequency VOH VOL IOH IOL VIH VIL IIN Signal CAP freq Min Typ 1 2.8V, 30pF load 2.8V, 5pF load VDD = 2.8V, VOH = 2.4V VDD = 2.8V, VOL = 0.4V VDD = 2.8V VDD = 2.8V 0.72 1.25 2.8 2.5 –0.3 16 15.9 1.48 Max Unit 30 pF V/ns V/ns V V mA mA V V µA pF MHz MHz 3.1 0.3 26.5 21.3 1.43 2 –2 3.5 Absolute minimum VGA at 30 fps 2 27 Power Consumption Table 8: Power Consumption TA = Ambient = 25°C; All supplies at 2.8V Mode Sensor (mW) Image-Flow Proc (mW) I/Os (mW)1 DAC (mW) LVDS (mW) Total (mW) 60 100 10 150 80 400 0.56 Active mode 2 Standby Notes: PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_3.fm - Rev. B 3/07 EN 1. 10pF nominal. 2. (NTSC or PAL) and LVDS should not be operated at the same time. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Package Diagram Package Diagram Figure 10: 48-Pin CLCC Package Outline Drawing 2.3 ±0.2 D 1.7 Seating plane Substrate material: alumina ceramic 0.7 thickness Wall material: alumina ceramic A Lid material: borosilicate glass 0.55 thickness 8.8 47X 1.0 ±0.2 0.8 TYP 4.4 48 48X 0.40 ±0.05 48X R 0.15 H CTR 1.75 Ø0.20 A B C 1 First clear pixel 5.215 4.84 4.4 Ø0.20 A B C 5.715 0.8 TYP 4X 10.9 ±0.1 CTR V CTR 11.43 8.8 Image sensor die: 0.675 thickness 0.2 5.215 5.715 11.43 Lead finish: Au plating, 0.50 microns minimum thickness over Ni plating, 1.27 microns minimum thickness Notes: C Optical area A B 0.05 0.10 A 1.400 ±0.125 0.90 for reference only 0.35 for reference only 10.9 ±0.1 CTR Optical center1 Optical area: Maximum rotation of optical area relative to package edges: 1º Maximum tilt of optical area relative to seating plane A : 50 microns Maximum tilt of optical area relative to top of cover glass D : 100 microns 1. Optical center = package center. 2. All dimensions are in millimeters. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and DigitalClarity are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_3.fm - Rev. B 3/07 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: SOC VGA Digital Image Sensor Revision History Revision History Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/28/2007 • Updated package drawing. PDF: 09005aef82c99cd/Source:09005aef824c99db MT9V135_LDS_3.fm - Rev. B 3/07 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved.