HFC0300 Variable Off Time Controller The Future of Analog IC Technology DESCRIPTION HFC0300 is a variable off-time controller that uses a fixed-peak–current technique to decrease its frequency as the load lightens. As a result, it offers excellent efficiency at light-load while optimizing the efficiency under other load conditions. When the frequency decreases to threshold, the peak current decreases with the decreasing load to prevent mechanical resonance in the transformer. The controller enters burst mode when the output power falls below a given level. The HFC0300 features various protections such as thermal shutdown, VCC under-voltage lockout, overload protection, short-circuit protection, and over-voltage protection. The HFC0300 is available in SOIC-7 package. FEATURES Variable Off-Time, Current Mode Control Universal Main Supply Operation (85VAC to 265VAC) Frequency Foldback as Load Lightens Peak-Current Compression to Reduce Transformer Noise Active-Burst Mode for Low Standby Power Consumption Internal High-Voltage Current Source Internal 200ns Leading Edge Blanking Thermal Shutdown (Auto Restart with Hysteresis) VCC Under-Voltage Lockout with Hysteresis Over-Voltage Protection on VCC Pin Timer-Based Overload Protection Short-Circuit Protection Natural Spectrum Shaping for Improved EMI Performance APPLICATIONS Battery Charger for Portable Electronics Standby Power Supply Switched-Mode Power Supplies For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 1 HFC0300– VARIABLE OFF TIME CONTROLLER TYPICAL APPLICAION T1 Output * * Input 85Vac - 265Vac * HV 8 1 2 VCC FSET 6 3 5 4 DRV CS GND COMP HFC0300 HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 2 HFC0300– VARIABLE OFF TIME CONTROLLER ORDERING INFORMATION Part Number* HFC0300HS Package SOIC-7 Top Marking Free Air Temperature (TA) HFC0300 -40°C to +125°C For Tape & Reel, add suffix –Z (e.g. HFC0300HS–Z); For RoHS compliant packaging, add suffix –LF (e.g. HFC0300HS–LF–Z) PACKAGE REFERENCE TOP VIEW DRV 1 8 HV CS 2 GND 3 6 VCC COPM 4 5 FSET SOIC-7 (4) ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance HV Breakdown Voltage .............. -0.7V to +700V VCC, DRV to GND ........................-0.3V to +30V DRV to GND .................................-0.3V to +18V FSET, COMP, CS to GND ..............-0.3V to +7V (2) Continuous Power Dissipation (TA = +25°C) SOIC-7……………………………………....1.3W Junction Temperature ...............................150°C Thermal Shut Down ..................................150°C Thermal Shut Down Hysteresis ..................25°C Lead Temperature ....................................260°C Storage Temperature .............. -60°C to +150°C ESD Capability Human Body Model (All Pins except Drain) ........................................... 2.0kV ESD Capability Machine Model ................. 200V Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. θJA θJC SOIC-7 .................................... 96 ...... 45 ... °C/W Recommended Operation Conditions (3) Maximum Junction Temp. (TJ) ............... +125°C Operating Vcc range ........................ 8.2V to 20V HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 3 HFC0300– VARIABLE OFF TIME CONTROLLER ELECTRICAL CHARACTERISTICS VCC=12V, TA=25°C, unless otherwise noted. Parameter Symbol Conditions Supply Current from Pin HV IHV VHV=400V, Vcc=6V Break-Down Voltage VBR Min Typ Max Unit Start-up Current Source (Pin HV) Off-State HV Leakage Current Supply Voltage Management (Pin VCC) VCC Increasing Level where the Current Source Turns Off VCC Decreasing Level where the Current Source Turns On Vcc Re-Charge Level where Protections Occurs ILeak mA 700 VHV=400V, Vcc=10V V 10 17 μA VCCOFF 10.7 11.7 12.7 V VCCON 7.6 8.2 8.8 V VCCR 5.0 5.5 6.0 V VCC Decreasing Level where Latch-Off Phase Ends VCClatch Internal IC Consumption ,1nF Load on DRV Pin Icc Internal IC Consumption, Latch off Phase Rising Voltage Threshold on VCC where Controller Latches Off (OVP) Integration Time Constraint on the OVP Comparator Timing Capacitor(Pin FSET) Minimum Voltage on FSET Capacitor Maximum Voltage on FSET Capacitor Source Current FSET Capacitor Discharge Time (Active at Drive Turn-On) Feedback Management (Pin COMP) Icclatch fs=65kHz, Vcc=12V Vcc=6V VOVP 22.5 tINT 0.82 23 tDISCH VOLP Over Load Protection Delay Time tOLP 3.0 V 1.3 mA 500 μA 24 25.5 20 VFSETmin VFSETmax IFSET Over Load Protection Set Point COMP Decreasing Level where the Controller Enters the Burst Mode COMP Increasing Level where the Controller Leaves the Burst Mode 2 0.88 3.2 28 μs 0.94 33 0.6 0.80 CFSET=330pF 0.85 V V V μA μs 0.90 74 V ms VBURH 3.0 3.2 3.4 V VBURL 2.9 3.1 3.3 V Current Sampling Management (Pin CS) Short-Circuit Comparator Leading-Edge Blanking Current-Sense Comparator Leading-Edge Blanking Maximum Current-Sense Comparator Limit Short-Circuit Protection Point HFC0300 Rev. 1.0 9/23/2011 tLEB1 150 ns tLEB2 200 ns VLimit VSCP VCOMP=1V VSCP 0.45 0.5 1.0 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved -0.55 V V 4 HFC0300– VARIABLE OFF TIME CONTROLLER ELECTRICAL CHARACTERISTICS (continued) VCC=12V, TA=25°C, unless otherwise noted. Parameter Symbol Driving Signal (Pin DRV) Sourcing Resistor Sinking Resistor VDRIVE Clamp Conditions RH RL VDRIVE Vcc=18V Min Typ 10 3 13.7 Max Unit Ω Ω V PIN FUNCTIONS SOIC-7 Pin # Name Description 1 2 3 DRV CS GND 4 COMP 5 FSET 6 VCC 8 HV Drive. Output of the drive signal. Current Sense Input. Ground. Switching Frequency Set. A feedback voltage of 0.85V will trigger overload protection, and a feedback voltage of 3.1V will trigger a burst mode operation. Frequency Set. Maximum switching frequency set by a capacitor. IC Supply. Connected to an external bulk capacitor. If an auxiliary winding brings this pin above 24V, the controller latches off. High-Voltage Source. Input for the start-up high voltage current source. HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved 5 HFC0300– VARIABLE OFF TIME CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS 2.7 12 8.5 11.75 8.25 V CCH (V) 2.3 2.1 1.9 0 8 7.75 11 -40 -20 0 20 40 60 80 100 120 7.5 -40 -20 0 20 40 60 80 100 120 20 40 60 80 100 120 78 24.5 0.86 76 24.3 0.84 74 24.1 0.82 0.8 VOVP(V) 0.88 TOCP(ms) VOLP(V) 11.5 11.25 1.7 1.5 -40 -20 V CCL(V) 2.5 72 23.7 70 0.78 -40 -20 0 20 40 60 80 100 120 68 -40 -20 0.88 30 0.875 29 0.87 28 0.865 27 23.9 23.5 -40 -20 0 0 20 40 60 80 100 120 20 40 60 80 100 120 0.51 0.5 IPEAK(V) FSETMIN(V) 0.505 0.495 0.49 0.485 0.86 -40 -20 HFC0300 Rev. 1.0 9/23/2011 0 20 40 60 80 100 120 26 -40 -20 0 20 40 60 80 100 120 0.48 -40 -20 0 20 40 60 80 100 120 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved 6 HFC0300– VARIABLE OFF TIME CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continued) SCP Point vs. Temperature Comp Increasing Level Comp Decreasing Level at which the Controller Enters at which the Controller Leaves the Burst Mode vs. Temperature the Burst Mode vs. Temperature 0.95 0.93 3.25 3.16 3.23 3.14 0.89 3.21 0 HFC0300 Rev. 1.0 9/23/2011 20 40 60 80 100 120 3.17 -40 -20 0 20 3.12 3.1 3.19 0.87 0.85 -40 -20 VBURL(V) VBURH(V) IPEAK(V) 0.91 40 60 80 100 120 3.08 -40 -20 0 20 40 60 80 100 120 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved 7 HFC0300– VARIABLE OFF TIME CONTROLLER BLOCK DIAGRAM Power Management VCC(6) OTP OVP GND(3) OLP COMP(4) Fault Management Burst Mode Control Peak Current Compression FSET(5) Frequency Control Start Up Unit HV(8) Internal Power Supply Driving Signal Management DRV(1) Current Comparator CS(2) Figure 1: Functional Block Diagram HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved 8 HFC0300– VARIABLE OFF TIME CONTROLLER OPERATION The HFC0300 incorporates all the necessary features to build a reliable Switched-Mode Power Supply (SMPS). Its high level of integration requires few external components. Based on a fixed peak current technique, the controller decreases its frequency with the decreasing load to minimize switching loss. When the output power falls below a given level, the controller enters burst mode. It also has better EMI performance because the switching frequency varies with the natural bulk ripple voltage. Frequency Foldback A capacitor connected to the FSET pin sets the frequency at the end of charging. This capacitor charges from a constant current source and its voltage is compared with an internal threshold fixed by COMP voltage (see Figure 2). When this capacitor voltage reaches threshold, the capacitor discharges rapidly down to 0V, and a new period starts after a 0.6μs delay (see Figure 3). Start-up and Under Voltage Lock-out Initially, the internal high voltage current source drawn from the high-voltage (HV) pin powers the IC. The IC starts switching and the internal highvoltage current source turns off as soon as the voltage on VCC reaches 11.7V. Then the auxiliary winding of the transformer supplies the IC before the VCC voltage falls back below 8.2V. Otherwise, the switching pulse stops and the high-voltage current source turns on again. Figure 4 shows the typical waveform with VCC under-voltage lockout (UVLO). The auxiliary winding takes over VCC VCCH=11.7V VCCL=8.2V ON Internal Current Source OFF FSET Driving Signal 0.6µs pulse 28µA VCC S VOFFSET 0.88V R Q _ Q Drive COMP 3.3V Figure 2: Voltage-Controlled Oscillation Vfset Controlled by the COMP Voltage Minimum Frequency Pout Decrease IFSET=28µA Pout Increase Maximum Frequency Figure 3: COMP-Voltage–Adjusted Switching Frequency HFC0300 Rev. 1.0 9/23/2011 Figure 4: VCC Under-Voltage Lockout The lower threshold of VCC UVLO goes from 8.2V to 5.5V when fault conditions happen, such as over-load protection (OLP), over-voltage protection (OVP), and over-temperature protection (OTP). Over-Voltage Protection By monitoring the VCC pin with a 20µs timeconstant filter, the HFC0300 goes into latched fault condition whenever an over-voltage condition occurs—if VCC goes above 24V, typically. The controller stays fully latched in this position until the VCC is cycled down to 3.0V, e.g. when the user unplugs the power supply from the main input and re-plugs it. Over-Load Protection In a flyback converter, the maximum output power is limited by the maximum switching frequency and primary peak current. As the primary peak current is constant, the maximum power is limited by maximum frequency. When the switching frequency reaches the maximum, www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 9 HFC0300– VARIABLE OFF TIME CONTROLLER the output voltage decreases if the load continues to increase. COMP then drops below the over-load protection (OLP) point because feedback is equivalent to an open circuit. By continuously monitoring the COMP, when the COMP voltage drops below 0.85V—which is considered an error—the timer starts counting. If the error flag is removed, the timer resets. If the timer reaches completion at the delay time determined by the FSET capacitor (for example, 74ms at CFSET=330pF), OLP takes place. This timer avoids triggering OLP when the power supply is at start-up or load transition phase. Therefore the power supply should start-up in less than over load protection delay time, as determined by the following equation: t delay 74ms CFSET 330pF Short Circuit Protection The HFC0300 shuts down when the CS voltage rises higher than 1V using short-circuit protection (SCP). As soon as the fault disappears, the power supply resumes operation. During SCP, the VCC UVLO lower threshold goes from 8.2V to 5.5V. Thermal Shutdown The HFC0300 shuts down switching when the inner temperature exceeds 150°C to prevent damaging high temperatures. As soon as the inner temperature drops below 125°C, the power supply resumes operation. During the thermal shutdown (TSD), the VCC UVLO lower threshold goes from 8.2V to 5.5V. Peak current compression As the load becomes lighter, the frequency decreases and may enter the audible range. To avoid exciting mechanical resonances in the transformer and generating acoustic noise, the HFC0300 reduces the peak current as power goes down and thus reduces noise issues. Peak Current(V) Peak Current Compression Constant Peak Current Burst Mode 0.5 0.167 2.1 0.9 3.1 3.2 COMP(V) Figure 5: Peak Current vs. COMP Burst Operation The HFC0300 enters burst-mode operation to minimize power dissipation in no load or light load conditions. As the load decreases, the COMP voltage increases; The IC stops switching when the COMP voltage increases over the threshold, VBRUH = 3.2V. The output voltage then drops, which causes the COMP voltage to decrease further. Once the COMP voltage falls below the threshold VBRUL = 3.1V, switching resumes and the COMP voltage then oscilates. The burst mode operation alternately enables and disables switching cycle of the MOSFET. Leading-Edge Blanking In order to avoid the premature termination of the switching pulse due to the parasitic capacitance, an internal leading-edge blanking (LEB) unit is employed between the CS pin and the current comparator input. During the blanking time, the current comparator is disabled and can not turn off the external MOSFET. Figure 6 shows the leading-edge blanking. VLimit TLEB=200nS Figure 5 shows the curve of peak current versus COMP. t Figure 6: Leading-Edge Blanking HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 10 HFC0300– VARIABLE OFF TIME CONTROLLER Start Y Internal High Voltage Current Source ON Shut Down Internal High Voltage Current Source Y Vcc>11.7V N Vcc Decrease to 5.5V Shut off the Switching Pulse Y Vcc<8.2V Y OTP or SCP Logic High? N Latch off the Switching Pulse N Y Y VCC>24V Soft Start N Vcc<3V? N OTP or SCP Monitor Monitor Vcc Monitor VCOMP Y VCOMP>3.2V 0.85V<VCOMP<3.1V VCOMP<0.85V T>TOLP and OLP=Logic High Y N Continuous Fault Monitor Switch Off N VCOMP<3.1V Off Time Operation Y OLP=Logic High UVLO, OTP, SCP & OLP is auto restart, OVP is latch Release from the latch condition, need to unplug from the main input. Figure 7: Control Flow Chart HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 11 HFC0300– VARIABLE OFF TIME CONTROLLER Vcc Start up Regulation Occurs Here Over Voltage Occurs Here Unplug from main input Normal operation Normal operation Normal operation 11.7V 8.2V 5.5V Driver Pluses Driver High voltage current source On Off Fault Flag OLP delay Normal operation OVP Fault Occurs Here Normal operation OLP Fault Occurs Here Normal operation OTP Fault Occurs Here Normal operation Figure 8: Signal Changes in the Presence of Different Faults HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 12 HFC0300– VARIABLE OFF TIME CONTROLLER APPLICATION INFORMATION Design Keys of HFC0300 Current Sense Resistor Section The peak current level is internally set to 0.5V, so the current-sense resistor sets the primary-side peak current, which determines the operation mode of the converter—such as CCM, BCM or DCM. If power supply is designed to operate at BCM at low-line input, it will operate at DCM at the high line and the same load condition. The magnetizing inductor current (reflected on the primary side) and the drain-source voltage (VDS) of the primary MOSFET is shown in Figure 9. Inductor Current (A) The time duration of the secondary current can be determined by equation (1): t sec Isecondary/N 0.5V/Rsense VDS Tsecond Low line N Vo (1) Where Lm is the primary magnetizing inductance, Ipeak is the primary peak current, and N is the turn ratio of the transformer. Ipeak remains the same at under different inputs and with the same output, so the time duration of secondary current is the same. The switching period can be calculated by: N Ipeak t sec (2) 2 Io From equation (2), the switching period remains the same at different inputs with the same output condition. Since the primary-side switch ON time decreases with the increasing input voltage, then the higher the input line voltage, the deeper discontinuous current mode (DCM) it will enter. Usually, the parameters are designed for the minimum input condition to guarantee that the converter can deliver the required maximum output power. t Iprimary Lm Ipeak Since N is pre-determined, if the power supply is designed to operate at boundary current mode (BCM) at the low line, the peak current can be calculated as: Inductor Current (A) Iprimary Ipeak _ BCM Isecondary/N D Tsecond High line T Figure 9: Inductor Current and Voltage of Primary MOSFET HFC0300 Rev. 1.0 9/23/2011 (3) Where D is the duty ratio of the switching. Then: 0.5V/Rsense VDS 2 Io N (1 D) (Vo VF ) N Vin (Vo VF ) N (4) If the peak current set by the current-sense resistor is larger than Ipeak_BCM, the power supply will enter DCM. On the other hand, if the peak current set by current sense resistor is less than Ipeak_BCM, the power supply will enter CCM, as shown as Figure 10. Here, we define Kdepth as the depth of CCM. Ivalley K depth (5) Ipeak www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 13 HFC0300– VARIABLE OFF TIME CONTROLLER regulated by the feedback loop like a voltagecontrolled oscillation (VCO). IMOSFET Ipeak 28uA ( 0.6us) fmax 0.88V CFSET Figure 10: Primary Current at CCM So the peak current can be determined as: Ipeak _ CCM 2 Io (1 D) (1 K depth ) N FSET 0.6µs pulse The converter operation mode must be determined with each power supply specification given; i.e. determine the Kdepth. Ipeak and Ivalley as calculated by equations (3) through (6). Select the current sense resistor using equation (7). Vpeak Rsense (7) Ipeak Where Vpeak is the peak voltage threshold of the current resistor; a constant 0.5V for HFC0300. Chose the current resistor with the proper power rating based on the power loss given in equation (8) Ipeak Ivalley 2 )2 1 (Ipeak Ivalley )2 ] D Rsense 12 28µA (6) Usually, BCM is preferable at power levels below 40W, and CCM is preferable at power levels higher than 40W: The higher the power delivered, the deeper the CCM adopted for higher efficiency and better thermal performance at full load. For example, for a 90W power supply, Kdepth should be around 0.5. (8) Design of CFSET and OLP Function The capacitor CFSET sets the maximum frequency as shown in equation (9). This capacitor is charged by a constant-current source shortly after the primary side switch turns on (about 0.6µs delay), and its voltage is compared with the COMP voltage from feedback loop (see Figure 11). When the capacitor voltage reaches threshold, the capacitor rapidly discharges down to 0V, and a new period starts. An internal delay of about 0.6µs delay before CFSET charges again fully discharges the voltage at the FSET pin, (see Figure 12). Thus the switching frequency is HFC0300 Rev. 1.0 9/23/2011 (9) Where fmax is the maximum frequency set by the capacitor connected to FSET pin. Ivalley Psense [( 1 VCC VOFFSET 0.88V S Q R _ Q Drive COMP 3.3V Figure 11: Schematic for Voltage-Controlled Oscillation Vfset Controlled by the COMP Voltage Minimum Frequency Pout Decrease IFSET=28µA Pout Increase Maximum Frequency Figure 12: Switching Frequency as Adjusted by COMP Voltage As described in the section above, the switching frequency reaches its maximum at low line and full load. This frequency, defined as fs (65kHz in this case). Set the maximum frequency (fmax) at 110% fs. The frequency increases with the increasing output power. When the frequency reaches its maximum—set by CFSET—the overpower limit drops the output voltage, saturating COMP, and drops the OLP threshold (0.85V). The OLP uses a unique digital timer method: When COMP is less than 0.85V and raises an error flag, the timer starts counting. If the error flag is removed, the timer resets. If the timer overflows after reaching 6000, OLP triggers. This timer duration avoids triggering the OLP when www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 14 HFC0300– VARIABLE OFF TIME CONTROLLER the power supply is at start-up or load transition phase. Therefore, set the output voltage in less than 6000 switching cycles during start-up. Equation (11) estimates the compensation rate of the above circuit : k Ramp Compensation Circuit R3 * C1 Select to be larger than the switching period so that the ramp is approximately linear. Design Summary (10) Figure 14 shows a detailed reference design of the off-time controlled flyback converter using the HFC0300. The input voltage is 90VAC to 265VAC and the output is 24V/1.5A. Where: is the coefficient which is usually 0.5 to 1.0 Rsense is the value of primary sense resistor The transformer used in this design has a turn ratio of 84:14:8 (Np: Ns: Naux) with a primary inductance of 818μH. The core is EE25. Figure 15, Figure 16, and Table 1 Winding Ordershow wiring schematics. For applications using the HFC0300, use the ramp compensation circuit shown in Figure 13 . HV 8 FSET 510K 1K R1 HFC0300 VCC VCC 1 DRV 2 CS 6 3 GND 5 4 (11) Where VDRV is the drive voltage If the power supply operates in CCM and the duty cycle is larger than 0.5, add a ramp compensation circuit to avoid harmonics in peak current mode control. Usually, the ramp compensation rate is selected as per equation (10) V N Rsense k O Lm VDRV R1 * R2 R3 33pF C1 COMP R2 30K CS Figure 13: Ramp Compensation Circuit HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 15 HFC0300– VARIABLE OFF TIME CONTROLLER 2.2nF CY3 R11A 20 C9 3.3nF T1 R11B 20 1 R2A 150k R2B 150k C2 4.7nF 3 Np 9/10 3 F1 2 1A BD1 GBU406 R3 3.3 C1 LX1 CX1 CN1 Ns C3 FR107 C11 C10 1 C12 CN2 5 6/7 AGND Np-Aux D2 2.2M L1 2 1 1 D3 B1100 R4 D1 V40120C 4 2 PGND EE25 R13 R15 1k 97.6k R5 RT1 2.2M 5 RF R2 NC PGND 51k U2 PC817A R12 U1 R6 Q1 AP2761I-A 10 R8 1 1k R7 2 C5 3 20k HV Drv CS NC GND VCC 4.02k 8 7 6 C7 R1 10k R3C R3B R3A 1 1 1 1nF 4 COMP Fset HFC0300 R14 5 1 C13 C8 C6 U3 TL431K PGND PGND R16 R17 11.3k NC AGND Figure 14: Schematic of Off-Time Flyback Converter with HFC0300 PRI. SEC. 1 2 3 5 N4 10 9 N1 N3 N2 7 6 4 TEFLON TUBE Figure 15: Connection Diagram HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 16 HFC0300– VARIABLE OFF TIME CONTROLLER Pri. Side Sec. Side 2mm 2mm Tape: 3T N4 3T N3 3T N2 1T N1 1T Figure 16: Winding Diagram Table 1 Winding Order Tape(T) Winding Edge Tape (Pri.) Terminal (start-end) Edge Tape (Sec.) Wire size (φ) Turns (T) N1 2mm 3->2 2mm 0.3mm*1 42 N2 2mm 5->4 2mm 0.2mm*1 8 N3 2mm 9,10->6,7 2mm 0.3mm*5 14 N4 2mm 2->1 2mm 0.3mm*1 42 1 1 3 3 3 Experimental Verification A physical prototype based on Figure 13 was used to verify both the design procedure presented in this application note, and the performance. The input ranged between 90VAC and 265VAC, and the output was at 24V/1.5A. The converter operates in BCM at 90VAC input and full load. Figure 17 and Figure 18 the current and drain voltage waveforms of the primary MOSFET. Figure 19 shows the burst mode function of the controller at light load. To minimize power dissipation at no load or light load, the HFC0300 enters burst-mode operation. As the load decreases, the COMP voltage increases. The HF0300 skips switching cycles when the COMP voltage increases over the threshold VBURH = 3.2V. The output voltage drops, causing the COMP voltage to decrease again. HFC0300 Rev. 1.0 9/23/2011 Once the COMP voltage falls below the threshold VBURL = 3.1V, switching resumes. The COMP voltage then rings. The burst mode operation alternately enables and disables switching cycles of the MOSFET thereby reducing switching loss in the no load or light load conditions. Figure 20 shows over-load protection. When COMP is low, the controller stops switching after 6000 switching cycles (about 100ms for this application) Figure 21 shows the measured efficiency. From the efficiency curve, the efficiency is still high at light load condition due to decreased switching frequency. Also the power consumption at no load is given in Table 2. In burst mode, the power loss with no load is very small, even with high line input. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 17 HFC0300– VARIABLE OFF TIME CONTROLLER VDS CS Figure 17: Drain Current and Voltage of MOSFET at Low-Line Input (90VAC); CH2 - CS, CH3, VDS VDS CS Figure 18: Drain Current and Voltage of MOSFET at High-Line Input (230VAC); CS2 - CS, CH3 - VDS HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 18 HFC0300– VARIABLE OFF TIME CONTROLLER Figure 19: Burst Mode; CH2 - COMP, CH3 - DRV Vout DRV Iout COMP Figure 20: Overload Protection; CH1 - VOUT, CH2 - DRV, CH4 IOUT HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved 19 HFC0300– VARIABLE OFF TIME CONTROLLER 90.00% 88.00% Efficiency(%) 86.00% 84.00% 82.00% 80.00% 78.00% 76.00% 74.00% 72.00% 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Output Current Io(A) Vin=115VAC Vin=230VAC Figure 21: Measured Efficiency Table 2: No-Load Loss at Different Line Voltages Input voltage (VAC, RMS) Power loss (mW) HFC0300 Rev. 1.0 9/23/2011 90 115 230 265 74.4 77.2 110.1 121.9 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 20 HFC0300– VARIABLE OFF TIME CONTROLLER PACKAGE INFORMATION SOIC-7 0.189(4.80) 0.197(5.00) 8 0.050(1.27) 0.024(0.61) 5 0.063(1.60) 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.213(5.40) 4 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.013(0.33) 0.020(0.51) 0.050(1.27) BSC 0.0075(0.19) 0.0098(0.25) SEE DETAIL "A" SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH , PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) JEDEC REFERENCE IS MS-012. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. HFC0300 Rev. 1.0 9/23/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 21