MPS MP1720DQ-6

MP1720
The Future of Analog IC Technology
2.7W Mono Class D
Low-EMI High-Efficiency Audio Amplifier
DESCRIPTION
FEATURES
The MP1720 is a high efficiency Class-D audio
amplifier. It utilizes a full bridge output structure
capable of delivering 2.7W into 4Ω speaker.
This device exhibits the high fidelity of a class
AB amplifier with an efficiency of 90% which
dramatically reduces solution size by integrating
the following:















250mΩ power MOSFETs (VIN =3.3V)
Startup / Shutdown pop elimination
Short circuit /Thermal overload Protection
The MP1720 features a pin-selectable 1MHz or
1.3MHz frequency control or can be
synchronized to an external clock source. The
flexible switching frequency and internal EMIreduction scheme eliminates the need for an
output LC filter and passes emission standards
without filter & with considerable cable.
Passes FCC-Radiated Emissions Standards
with 24inch of Cable without output filter
2.7W Into 4Ω with 5V VIN @ 10% THD+N
Up to 90% Efficiency
Flexible Switching Frequency setting
Low Noise (53μV Typical) with 3.3V VIN
15ms Start-up time Eliminates pop
Low Quiescent Current (4mA @3.3V)
Low Shutdown Current (0.1μA)
Full Bridge Output Drive
Fully Differential Input
Short circuit Protection
Thermal Shutdown
APPLICATIONS




The MP1720 has five fixed gain options.
MP1720-3: 3dB; MP1720-6: 6dB; MP1720-9:
9dB; MP1720-12: 12dB; MP1720-216: 21.6dB.
Cellular Phones
PDAs
MP3 Players
Portable Audio
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
The MP1720 is available in 10-pin MSOP-EP
and 10-pin QFN packages.
TYPICAL APPLICATION
IN-
CIN
Enable
Cs
VIN
INP
INN
PVIN
OUTN
MP1720
OUTP
DGND
PGND
SHDN
CLK
OUT OUT+
AMPLITUDE (dBuV/m)
IN+
CIN
50
Cs
Power Supply
40
FCC EMI LIMIT
30
20
10
0
-10
30
100
300
FREQUENCY (MHz)
MP1720 Rev. 1.01
8/9/2012
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© 2012 MPS. All Rights Reserved.
1
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
ORDERING INFORMATION
Part Number*
Package
MP1720DQ-3
MP1720DQ-6
MP1720DQ-9
MP1720DQ-12
MP1720DQ-216
MP1720DH-3
MP1720DH-6
MP1720DH-9
MP1720DH-12
MP1720DH-216
QFN10 (3mm x 3mm)
MSOP10EP
Top Marking
Free Air Temperature (TA)
6J
7J
8J
9J
2K
1720K
1720L
1720M
1720N
1720P
-40C to +85C
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
VIN
1
10
PVIN
VIN
1
10
PVIN
INP
2
9
OUTN
INP
2
9
OUTN
INN
3
8
OUTP
DGND
4
7
PGND
SHDN
5
6
CLK
INN
3
8
OUTP
DGND
4
7
PGND
SHDN
5
6
CLK
EXPOSED PAD
ON BACKSIDE
CONNECT TO GND
EXPOSED PAD
ON BACKSIDE
CONNECT TO GND
QFN10
MSOP10EP
ABSOLUTE MAXIMUM RATINGS (1)
VIN to DGND...............................................6.0V
PVIN to PGND ............................................6.0V
DGND to PGND ..........................-0.3V to +0.3V
PVIN to VIN .................................-0.3V to +0.3V
All Other Pins to DGND….-0.3V to (VIN + 0.3V)
Continuous Power Dissipation (TA = +25°C) (2)
QFN10 ....................................................... 2.5W
MSOP10-EP .............................................. 1.2W
Junction Temperature.............................+140°C
Storage Temperature Range ...-65°C to +150°C
Lead Temperature (soldering, 10s) ........+260°C
Recommended Operating Conditions
(3)
Supply Voltage VIN.........................2.5V to 5.5V
Operating Junct. Temp. (TJ)..... -40C to +125C
MP1720 Rev. 1.01
8/9/2012
Thermal Resistance
(4)
θJA
θJC
3x3 QFN10..............................50 ...... 12 ... C/W
MSOP10-EP ..........................105 ..... 19 ... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operation conditions.
4) Measured on JESD51-7, 4-layer PCB.
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© 2012 MPS. All Rights Reserved.
2
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
ELECTRICAL CHARACTERISTICS
VIN = PVIN = SHDN =3.3V, DGND = PGND = 0V, CLK = DGND (fCLK=1.0MHz), RLoad = ∞, RLoad
connected between OUT+ and OUT-, TA = +25C, unless otherwise noted.
Parameter
Symbol
Output Offset Voltage
|VOS|
Power Supply Rejection Ratio
PSRR
Common Mode Rejection Ratio
CMRR
Quiescent Current
IQ
Shut Down Current
Ids
Turn-On Time
tON
Input Equivalent Resistance
RINE
Input Bias Voltage
VBIAS
Voltage Gain
AV
Output Slew Rate
SR
Rise/Fall Time
tRISE,tFALL
Oscillator Frequency
fOSC
CLK Frequency Lock Range
UVLO
FCLK
CLK Input Thresholds
SHDN Input Thresholds
SHDN Input Leakage Current
CLK Input Current (5)
Conditions
Vs=0V, Av=4V/V,
VIN=2.5V to 5.5V
Min
VIN=2.5V to 5.5V
VIN=3.3V, VID=0.05V,
ΔVIC=0.6V
VIN=5.5V, no load,
switching
VIN=3.3V, no load,
switching
VIN=2.5V, no load,
switching
Max
Unit
±6
± 80
mV
-70
dB
-66
dB
7
4
8
mA
4
μA
3.5
SHDN =0, VIN=2.5V to
5.5V
MP1720-3
MP1720-6
Either
MP1720-9
input
MP1720-12
MP1720-216
MP1720-3
MP1720-6
MP1720-9
MP1720-12
MP1720-216
Typ
0.1
15
ms
12
21
kΩ
950
900
820
745
410
1.3
1.9
2.7
3.8
11.4
995
940
860
784
465
1.4
2.0
2.85
4.0
12.0
1035
980
900
825
530
1.5
2.1
3.0
4.2
12.6
ILkg_SHND
ILkg_CLK
V/V
VIN=3.3V
200
V/μs
10% to 90%
CLK = GND
CLK = FLOAT
VIN=2.5V to 5.5V
12
1000
1300
ns
500
kHz
1400
2.25
VCLKH
VCLKL
VSDH
VSDL
mV
VIN=2.5V to 5.5V
VIN=2.5V to 5.5V
SHDN =6.3V
Vclk = 0V
2.5
1
1.6
0.1
-1.25
0.45
±1
±10
kHz
V
V
V
μA
μA
Notes:
5) CLK has an internal 1MΩ resistor to VREF.
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
3
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
OPERATION CHARACTERISTICS
TEST SET-UP GRAPH, VIN = PVIN = SHDN =3.3V, DGND = PGND = 0V, CLK = DGND
(fCLK=1.0MHz), RLoad = 4Ω, Gain=12dB, TA = +25C, unless otherwise noted (6).
Parameter
Symbol
Conditions
THD+N=1%,
RLoad=4Ω
Output Power
POUT
THD+N=10%,
RLoad=4Ω
THD+N=1%,
RLoad=8Ω
THD+N=10%,
RLoad=8Ω
Total Distortion Pulse
Noise
THD+N
Supply Ripple
Rejection Ratio(7)
KSVR
Signal to Noise Ratio
SNR
Output Noise
Vn
Common Mode
Rejection Ratio(8)
MP1720 Rev. 1.01
8/9/2012
CMRR
POUT=2W,
POUT=0.8W
POUT=0.4W
fS=217Hz,
VRipple=300mVPP,
input AC-ground
VOUT=2 VRMS
A-weighted
VIN=3.3V, fs=20Hz
to 20kHz, input ACgrounded
VicRIPPLE=300mVPP,
fs=1kHz
Min
Typ
Max
Unit
VIN =5.0V
VIN =3.3V
VIN =2.5V
VIN =5.0V
VIN =3.3V
VIN =2.5V
VIN =5.0V
VIN =3.3V
VIN =2.5V
VIN =5.0V
VIN =3.3V
VIN =2.5V
VIN =5.0V
VIN=3.3V
VIN=2.5V
2.14
0.87
0.48
2.78
1.18
0.64
1.19
0.55
0.31
1.56
0.71
0.40
0.15%
0.13%
0.13%
VIN=3.3V
-60
dB
VIN=3.3V
91.3
dB
No weighting
72
A weighting
53
VIN=3.3V
-62
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© 2012 MPS. All Rights Reserved.
W
W
μVRMS
dB
4
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
PIN FUNCTIONS
Pin #
Name
Description
1
2
3
4
VIN
INP
INN
DGND
Analog Power Supply
Positive differential input
Negative differential input
Analog Ground
5
SHDN
Shutdown input (drive high to enable the MP1720)
6
CLK
7
8
9
10
PGND
OUTP
OUTN
PVIN
Thermal Pad
MP1720 Rev. 1.01
8/9/2012
Frequency select and external clock input;
CLK=GND: Operate frequency fCLK=1.0MHz
CLK=FLOAT: Operate frequency fCLK=1.3MHz
CLK=Clocked: Operate frequency fCLK=external clock frequency
Power Ground
Positive BTL output
Negative BTL output
Power Supply
Must be soldered to a ground on PCB
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© 2012 MPS. All Rights Reserved.
5
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
FUNCTIONAL BLOCK DIAGRAM
Power Supply
1
10
VIN
5
SHDN
Control Logic
6
CLK
PVIN
UVLO
OSC
FREQUENCY
PLL
SELECT
PVIN
-R3
2
3
INP
U2
+
R1
+
PGND
-+
--
8
OUTN
9
LOGIC
U1
INN
OUTP
PVIN
R2
+
U3
R4
--
PGND
MP1720
START UP
OTP
OCP
PGND
DGND
7
4
Figure 1—MP1720 Functional Block Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
TEST SET-UP GRAPH
10uF
0.1uF
Measurement +
Output
-
1uF
1uF
VIN
PVIN
INP
OUTN
INN
MP1720
OUTP
DGND
PGND
SHDN
CLK
68nF
0.1uF
33nF
15uH
22ohm
load
0.15uF
15uH
33nF
+
Measurement
Input
22ohm
68nF
Notes:
6) The 70kHz low-pass filter is required even if the analyzer has a low-pass filter.
7) For PSRR test, Please remove the 10uF decoupling capacitor and just keep the small decoupling capacitors for recovery switching
currents.
8) CIN was shorted for any Common-Mode input voltage measurement.
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
6
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES
VIN = PVIN = SHDN =3.3V, DGND = PGND = 0V, CLK = DGND (fCLK=1.0MHz), signal frequency
fs=1kHz, Gain=12dB, TA = +25C, unless otherwise noted (6,7,8).
20
20
20
10
10
10
5
5
5
2
2
1
1
0.5
0.5
0.5
0.2
0.2
2
1
VIN=2.5V
0.1
0.1
0.1
VIN=5V
0.05
VIN=5V
0.05
VIN=3.3V
0.01
60m 80m100m
200m 300m 500m 700m 1
2
3
4
0.01
60m 80m100m
200m 300m
POUT (W)
20
500m 700m
1
2
0.01
2
1
2
1
0.5
0.5
0.2
5
2
0.1
0.05
0 . 02
0 . 01
0 . 005
0.02
0 . 002
POUT=100mW
50 100 200
500 1k
2k
5k 10k 20k
0 . 001
500m 700m
1
2
5
POUT=400mW
1
0.5
0.1
0 . 05
POUT=800mW
20
200m 300m
20
10
0.01
60m 70m 100m
CLK=EXT
(500kHz)
POUT (W)
20
10
5
0.2
CLK=GND
(1.0MHz)
0.02
POUT (W)
10
THD+N (%)
0.05
VIN=3.3V
0.02
0.02
CLK=Float
(1.3MHz)
CLK=EXT
(1.4MHz)
VIN=2.5V
0.2
CLK=Float
(1.3MHz)
0.2
POUT=50mW
CLK=GND
(1.0MHz)
0.1
0.05
CLK=EXT
(500kHz)
0.02
20
50 100 200
FREQUENCY (Hz)
500 1k
2k
5k 10k 20k
0.01
20
CLK=EXT
(1.4MHz)
50 100 200
500 1k
2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Frequency Response
VIN=3.3V, POUT=100mW
+0
+0
20
-10
40
-20
+4
+2
+0
-2
60
-4
80
-30
-40
-50
-6
100
-60
-8
120
-10
10 20
50 100 200 500 1k 2k
5k 10k 20k 40k
FREQUENCY (Hz)
MP1720 Rev. 1.01
8/9/2012
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k
FREQUENCY (Hz)
-70
20
50 100 200
500 1k
2k
5k 10k 20k
FREQUENCY (Hz)
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7
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
VIN = PVIN = SHDN =3.3V, DGND = PGND = 0V, CLK = DGND (fCLK=1.0MHz), signal frequency
fs=1kHz, Gain=12dB, TA = +25C, unless otherwise noted (6,7,8).
Efficiency vs. POUT
Efficiency vs. POUT
VIN=3.3V
100
100
-10
90
90
80
80
70
70
EFFICIENCY(%)
-30
-40
-50
-60
60
50
40
30
20
-70
10
-80
0
20
50 100 200
500 1k
2k
5k 10k 20k
EFFICIENCY(%)
+0
-20
50
40
30
20
0
0.4
0.8
0
1.2
0
VIN=3.3V, THD+N=1%
90
1.8
80
80
1.6
70
1.4
60
1.2
70
60
50
40
30
20
10
900 1100 1300
P OUT (W)
2
90
EFFICIENCY(%)
100
50
40
1
0.6
20
0.4
10
0.2
0
500
700
900
1100
3.5
CLK FREQUENCY(kHz)
1.2
SHDN
2V/div
1.5
ILOAD
100mA/div
THD+N=1%
0.5
THD+N (%)
2.5
THD+N=10%
4.5
5.5
VIN(V)
1.4
0
2.5
THD+N=1%
0
2.5
1300
3
1
THD+N=10%
0.8
30
CLK FREQUENCY(kHz)
2
2.4 2.8
P OUT(W)
100
700
2
Efficiency vs. CLK Frequency
VIN=5V, THD+N=1%
0
500
0.4 0.8 1.2 1.6
P OUT(W)
Efficiency vs. CLK Frequency
EFFICIENCY(%)
60
10
FREQUENCY (Hz)
P OUT (W)
VIN=5V
1
0.8
0.6
0.4
0.2
0
3.5
4.5
VIN(V)
MP1720 Rev. 1.01
8/9/2012
5.5
0
0.5
1
1.5
2
2.5
COMMON MODE VOLTAGE (V)
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© 2012 MPS. All Rights Reserved.
8
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
OPERATION
The MP1720 is a high efficiency Class D audio
power amplifier, low cost which can operate well
without output LC filter, low EMI which can pass
FCC-Radiated Emissions Standards with 24inch
unshielded twisted-pair-speaker Cable without
output filter. It has fully differential input and
output. And this device can still be used with a
single-ended input; but for some noisy
environment the MP1720 should be used with
differential inputs to ensure maximum noise
rejection.
MP1720 Functional Block Diagram is shown as
Figure 1. The amplifier detects the input signal
and gets the input differential voltage, which
would be combined with the DC bias voltage to
generate the complementary voltage. The
complementary voltage is compared with the
sawtooth waveform. The output of the
comparators (U2, U3) would trip when the input
magnitude of the sawtooth exceeds the
complementary voltage. When no signal is
inputted, the output of both comparators are the
pulse with a fixed turn on time, and zero output is
got from the difference of two channel output
(VOUTP-VOUTN). As the larger positive signal is
inputted, the output duty of one comparator
would be larger while another remains the fixed
turn on time or less time, so larger output is got
from the difference of two channel output (VOUTPVOUTN). And there is opposite duty adjustment
when the larger negative signal is inputted.
CLK Operating Modes
The MP1720 offers two kinds of operate
frequency solution: internal fixed clock setting or
be synchronized to an external clock. Allowing
the switching frequency to be flexibly adjusted
can avoid the frequency or harmonics fall in
sensitive frequency bands.
1) Internal clock Mode
The MP1720 have two kinds of internal clock
selection. Setting CLK = DGND, the switching
frequency is 1.0MHz. Setting CLK = FLOAT, the
switching frequency is 1.3MHz.
MP1720 Rev. 1.01
8/9/2012
2) External Clock Mode
The MP1720 CLK input allows the amplifier to be
synchronized to an external TTL clock, which can
push the spectral components of the switching
harmonics off sensitive frequency bands. This
external TTL clock frequency range is very wide
and frequency from 0.5MHz to 1.4MHz is
recommended.
Table 1—CLK Operating Modes
CLK=GND
fCLK=1.0MHz
CLK=FLOAT
fCLK=1.3MHz
CLK=Clocked
fCLK=external clock frequency
Input configuration
The MP1720 is a mono BTL Class-D amplifier
with differential inputs and outputs, and this
device can still be used with a single-ended input
1) Differential Input
For some noisy environment, the MP1720 should
be used with differential inputs. The fully
differential amplifier allows the inputs to be
biased at voltage other than mid-supply. The
input coupling capacitors are not required if the
design uses a differential source that is biased
from 0.2 V to 1.9V (please see TPC: THD+N vs.
Common mode voltage). Although the input
coupling capacitor is saved, the low frequency
noise would be amplified to the speaker.
If the input signal is not biased within the
recommended common-mode input range, the
input coupling capacitors are needed to pass
only the AC audio signal to the input of the
amplifier as a high pass filter.
2) Single-Ended Input
The MP1720 also can be configured as a singleended input amplifier. Input coupling capacitor is
needed to create a high-pass filter with the input
resistor and get the low frequency rejection.
Note: The voltage at each input pin (INP or INN)
should be not lower than -0.5V, so the input
signal voltage and the maximum output power
would be limited, especially for the low gain part.
For the high output power applications, the
higher gain versions or the differential input is
recommended.
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© 2012 MPS. All Rights Reserved.
9
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
The peak-to-peak range of limited input voltage
on each input pin VLIMIT(PP) can be calculated by
the DC bias voltage VBIAS as the following formula.
VLIMIT (PP) = 2* (VBIAS+0.5)
(1)
Take the application with input coupling capacitor
as an example, the input DC bias voltage VBIAS
on each input pin is set internally (detailed value
please see Input Bias Voltage in the EC table).
For different gain options, the calculated
maximum input signal and the tested maximum
output power, with SE input or differential input,
are shown in the Table 2.
Table 2—Maximum Input voltage and
Maximum Output Power
Test condition:VIN=PVIN=5V; 4Ω load.
Part
MP1720-3
SE input
VIN_max POUT_max
(W)
(VPP)
2.99
0.52
MP1720-6
2.88
0.93
MP1720-9
2.72
1.74
2.568
2.62
1.93
2.7 @ 10%
THD+N
MP172012
MP1720216
Differential input
POUT_max
VIN_max
(W)
(VPP)
5.98
1.9
2.7 @ 10%
5.76
THD+N
2.7 @ 10%
5.44
THD+N
2.7 @ 10%
5.136
THD+N
2.7 @ 10%
3.86
THD+N
Thermal Shutdown/ Short Circuit Protection
The MP1720 provides internal over thermal
protection and short-circuit protection. The
amplifier would be disabled to prevent damage to
the IC if the junction temperature surpasses
+125°C. The junction temperature must fall below
+112°C before normal operation resumes. The
currents of both the high-side and low-side
MOSFETs are measured. If the current exceeds
an internally preset value, all MOSFETs will be
turned off. After the over thermal or short circuit
fault is monitored, the MP1720 remains disabled
status for a minimum of 50μs until normal
operation resumes.
Pop Suppression
After driving SHDN pin high, there is a 15ms
Start-up time to eliminate the startup pop. During
this period, an internal circuitry would charges
the bias voltages of the device to a certain level
to prevent the startup click or pop. And after
driving SHDN pin low, the all outputs will be set
to high impedance immediately
Shutdown Function
The MP1720 SHDN input is a low-active control.
To shutdown MP1720, drive SHDN low-level
voltage. To enable MP1720, drive SHDN highlevel voltage. Shutdown function can place the
MP1720 in a low-power (0.1μA) shutdown mode
and reduce power consumption and extend
battery life.
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
10
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
APPLICATION INFORMATION
COMPONENT SELECTION
The MP1720 uses a minimum number of external
components to complete a fully bridged Class D
audio amplifier. Use the following sections to
customize the amplifier for your particular
application.
1) Input Coupling Capacitors (CIN)
The MP1720 is a mono BTL Class-D amplifier
with differential outputs and inputs. If the input
signal is not biased within the recommended
common-mode input range or if using a singleended source, the input coupling capacitors are
used to pass only the AC audio signal to the
input of the amplifier as a high pass filter. Choose
an input coupling capacitor such that the corner
frequency fIN is less than the desired pass-band
frequency. The formula for the corner frequency
is:
fIN 
1
2RINCIN
2) Power Supply Decoupling Capacitor (CS)
The class-D audio amplifier requires adequate
power supply decoupling to ensure the efficiency
is high and total harmonic distortion (THD+N) is
low. To carry the higher frequency transient
current, spikes, or digital hash on the line, a good
low
ESR ceramic capacitor is necessary. Place a 1μF
decoupling capacitor as close as possible to the
device VCC lead. It is very important for the
efficiency of the class-D amplifier, because any
resistance or inductance in the trace between the
capacitor and the device may cause a loss. A
10μF or greater capacitor placed near the audio
power amplifier would also help for filtering lowerfrequency noise
(2)
RIN is 15kΩ for MP1720. Speakers in wireless
handsets usually can’t respond well to low
frequencies, so for this application the corner
frequency can be set to block the low frequencies.
The input coupling capacitance is calculated as:
CIN 
1
2RINfIN
(3)
If the corner frequency is within the audible band,
the capacitors should have a tolerance of ±10%
or better, because any mismatch in capacitance
causes an impedance mismatch at the corner
frequency and below.
Tantalum or aluminum electrolytic capacitor with
low-voltage coefficients is recommended, or the
largest package ceramics capacitor to minimize
voltage coefficient effects, for example X7R
dielectrics is better than Y5V or Z5U.
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
11
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
TYPICAL APPLICATION CIRCUIT
Cs
10
0.1
Cs
Differential IN+
Input
IN-
VIN
PVIN
INP
OUTN
MP1720
INN
Enable
OUT-
OUTP
DGND
PGND
SHDN
CLK
OUT+
1.0MHz
100pF
1.3MHz
Ext-clock 0.5~1.4MHz
Figure 2—MP1720 Application Schematic with Differential Input
(Input DC-biased voltage is within the recommended common-mode voltage range)
CIN 1
Differential IN+
Input
IN-
Cs
10
0.1
Cs
CIN 1
VIN
PVIN
INP
OUTN
MP1720
INN
Enable
OUT-
OUTP
DGND
PGND
SHDN
CLK
OUT+
1.0MHz
100pF
1.3MHz
50
Ext-clock 0.5~1.4MHz
Figure 3—MP1720 Application Schematic with Differential Input
(Input DC-biased voltage is out of the recommended common-mode voltage range)
CIN 1
SE Input
CIN 1
Enable
0.1
Cs
Cs
10
VIN
PVIN
INP
OUTN
INN
MP1720
OUT-
OUTP
DGND
PGND
SHDN
CLK
OUT+
1.0MHz
50
Ext-clock 0.5~1.4MHz
100pF
1.3MHz
Figure 4—MP1720 Application Schematic with Single Ended Input
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
12
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
PACKAGE INFORMATION
3mm x 3mm QFN10
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.18
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
10
1
2.25
2.55
0.50
BSC
5
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
1.70
0.25
2.50
0.50
RECOMMENDED LAND PATTERN
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
13
MP1720 – 2.7W LOW EMI HIGH EFFICIENCY MONO CLASS-D AUDIO AMPLIFIER
MSOP-EP
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP1720 Rev. 1.01
8/9/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
14