MP2562 1A, 4MHz, 50V Step-Down Converter The Future of Analog IC Technology DESCRIPTION FEATURES The MP2562 is a high frequency step-down switching regulator with an integrated internal high-side high voltage power MOSFET. It provides 1A output with current mode control for fast loop response and easy compensation. • • • • The wide 4.5V to 50V input range accommodates a variety of step-down applications, including those in an automotive input environment. A 12µA shutdown mode quiescent current allows use in battery-powered applications. • • • • • • High power conversion efficiency over a wide load range is achieved by scaling down the switching frequency at light load condition to reduce the switching and gate driving losses. 120μA Quiescent Current(12uA Shutdown) Wide 4.5V to 50V Operating Input Range 460mΩ Internal Power MOSFET Up to 4MHz Programmable Switching Frequency Stable with Ceramic Capacitor Internal Soft-Start Internally Set Current Limit without external Current Sensing Resistor Up to 95% Efficiency Output Adjustable from 0.8V to 47V Available in 3x3 QFN10 and SOIC8 Packages APPLICATIONS The frequency foldback helps prevent inductor current runaway during startup and thermal shutdown provides reliable, fault tolerant operation. • • • • • By switching at 4MHz, the MP2562 is able to prevent EMI (Electromagnetic Interference) noise problems, such as those found in AM radio and ADSL applications. High Voltage Power Conversion Automotive Systems Industrial Power Systems Distributed Power Systems Battery Powered Systems “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. The MP2562 is available in small 3mm x 3mm QFN10 and SOIC8 packages. TYPICAL APPLICATION C4 100nF 90 10 8,9 C1 100V VIN BST SW 1,2 C2 D1 R5 3 EN EN MP2562 R6 7 6 6.3V R1 R2 COMP FREQ GND R4 FB 5 4 C3 220pF R3 C6 NS VOUT 3.3V 80 EFFICIENCY (%) VIN VIN=8V L1 70 VIN=24V VIN=50V 60 50 VIN=12V 40 10 VIN=36V 100 1000 OUTPUT CURRENT (mA) MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 1 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER ORDERING INFORMATION Part Number Package Top Marking Free Air Temperature (TA) MP2562DQ* 3x3 QFN10 9F –40°C to +85°C MP2562DS** SOIC8 MP2562DS –40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP2562DQ–Z). For RoHS Compliant Packaging, add suffix –LF (e.g. MP2562DQ–LF–Z) ** For Tape & Reel, add suffix –Z (e.g. MP2562DS–Z). For RoHS Compliant Packaging, add suffix –LF (e.g. MP2562DS–LF–Z) PACKAGE REFERENCE TOP VIEW SW 1 10 BST SW 2 9 VIN EN 3 8 VIN COMP 4 7 FREQ FB 5 6 GND TOP VIEW EXPOSED PAD ON BACKSIDE CONNECT TO GND QFN10 Supply Voltage (VIN).....................–0.3V to +55V Switch Voltage (VSW)........................................... ................-0.3V (-5V for <10ns) to VIN +0.3V BST to SW .....................................–0.3V to +6V All Other Pins .................................–0.3V to +6V Continuous Power Dissipation . ….(TA=+25°C) (2) 3x3 QFN10……………………………….….2.5W SOIC8………………………….……………..1.3W Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature................. –65°C to +150° (3) Supply Voltage VIN ...........................4.5V to 50V Output Voltage VOUT .........................0.8V to 47V Operating Junct. Temp. .......... –40°C to +125°C MP2562 Rev. 0.91 4/5/2010 1 8 BST EN 2 7 VIN COMP 3 6 FREQ FB 4 5 GND SOIC8 ABSOLUTE MAXIMUM RATINGS (1) Recommended Operating Conditions SW Thermal Resistance (4) θJA θJC 3x3 QFN10 ............................. 50 ...... 12... °C/W SOIC8..................................... 96 ...... 45... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage.. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 2 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, VEN = 2.5V, VCOMP = 1.4V, TA= +25°C, unless otherwise noted. Parameter Symbol Condition Feedback Voltage Upper Switch On Resistance Upper Switch Leakage Current Limit Error Amp Voltage Gain Error Amp Transconductance Error Amp Min Source current Error Amp Min Sink current VIN UVLO Threshold VIN UVLO Hysteresis Soft-Start Time Oscillator Frequency Shutdown Supply Current Quiescent Supply Current VFB RDS(ON) 4.5V < VIN < 50V VBST – VSW = 5V VEN = 0V, VSW = 0V, VIN = 50V Duty Cycle = 50% ICOMP = ±3µA VFB = 0.7V VFB = 0.9V Min Typ Max Units 0.776 0.8 460 1 1.8 200 60 5 –5 3.0 0.4 1.3(5) 2 4 12 120 0.824 V mΩ μA A V/V µA/V µA µA V V ms MHz MHz µA µA 40 2.7 10%< VOUT <90% RFREQ = 45kΩ RFREQ = 18kΩ VEN = 0V No load, VFB = 0.9V 1.6 3.2 Thermal Shutdown Thermal Shutdown Hysteresis (6) Minimum Off Time Minimum On Time (6) EN Up Threshold EN Threshold Hysteresis 1.3 80 3.3 2.4 4.8 20 145 150 °C 15 °C ns ns V mV 100 100 1.5 300 1.7 Note: 5) The Soft-Start Time is measured based on VOUT from 10% to 90% and multiplied by 1.25 to get 0% to 100% Soft-Start Time. 6) Guaranteed by design. MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 3 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER PIN FUNCTIONS QFN Pin # SOIC8 Pin # 1, 2 1 3 2 4 3 5 4 6 5 7 6 8, 9 7 10 8 Name Description Switch Node. This is the output from the high-side switch. A low forward drop Schottky diode to ground is required. The diode must be close to the SW pins to reduce switching spikes. Enable Input. Pulling this pin below the specified threshold shuts the chip down. EN Pulling it up above the specified threshold or leaving it floating enables the chip. Compensation. This node is the output of the error amplifier. Control loop frequency COMP compensation is applied to this pin. Feedback. This is the input to the error amplifier. The output voltage is set by a FB resistive divider connected between the output and GND which scales down VOUT equal to the internal +0.8V reference. GND, Ground. It should be connected as close as possible to the output capacitor to Exposed shorten the high current switch paths. Connect exposed pad (QFN Package Only) to Pad* ground plane. Switching Frequency Program Input. Connect a resistor from this pin to ground to set FREQ the switching frequency. Input Supply. This supplies power to all the internal control circuitry, both BST VIN regulators and the high-side switch. A decoupling capacitor to ground must be placed close to this pin to minimize switching spikes. Bootstrap. This is the positive power supply for the internal floating high-side BST MOSFET driver. Connect a bypass capacitor between this pin and SW pin. SW * Note: exposed pad applies to QFN package only. MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 4 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT=5V, C1 = 10µF, C2 = 22µF, L1 = 10µH and TA = +25°C, unless otherwise noted. 100 Efficiency @VOUT=5V 100 VIN=5V 90 EFFICIENCY (%) EFFICIENCY (%) 90 VIN=8V 80 70 VIN=24V 60 VIN=12V 50 80 VIN=12V 70 60 VIN=24V 50 f s =500kHz 40 10 100 1000 f s =500kHz 40 10 OUTPUT CURRENT (mA) 100 Steady State IOUT = 0.1A IOUT = 1A VOUT AC Coupled 10mV/div. VOUT AC Coupled 20mV/div. VSW 10V/div. VSW 10V/div. 3500 3000 2500 2000 1500 1000 500 0 10 100 Rfreq ( 1000 ) IL 1A/div. 1 MP2562 Rev. 0.91 4/5/2010 4000 Oscillating Frequency vs Rfreq OUTPUT CURRENT (mA) Steady State IL 1A/div. 1000 OSCILLATIONG EFFICIENCY (KHz) Efficiency @VOUT=2.5V 2 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 5 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT=5V, C1 = 10µF, C2 = 22µF, L1 = 10µH and TA = +25°C, unless otherwise noted. Startup Shutdown Startup IOUT = 0.1A IOUT = 0.1A IOUT = 1A VEN 5V/div. VEN 5V/div. VEN 5V/div. VOUT 2V/div. VSW 10V/div. VOUT 2V/div. VOUT 2V/div. VSW 10V/div. VSW 10V/div. IL 1A/div. IL 1A/div. IL 1A/div. 1ms/div. 1ms/div. Shutdown IOUT = 1A VEN 5V/div. 1ms/div. Short Circuit Entry Short Circuit Recovery IOUT = 0.1A to Short IOUT = Short to 0.1A VOUT 2V/div. VOUT 2V/div. IL 1A/div. IL 1A/div. VOUT 2V/div. VSW 10V/div. IL 1A/div. 200μ s/div. MP2562 Rev. 0.91 4/5/2010 200μ s/div. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 200μ s/div. 6 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER BLOCK DIAGRAM VIN VIN EN REFERENCE UVLO/ THERMAL SHUTDOWN 5V + -2.6V INTERNAL REGULATORS + -BST SW SS time VOUT SS -- ISW + ISW Level Shift FB SW Gm Error Amp SS 0V8 -- COMP + OSCILLATOR CLK VOUT COMP GND FREQ Figure 1—Functional Block Diagram OPERATION The MP2562 is a variable frequency, non-synchronous, step-down switching regulator with an integrated high-side high voltage power MOSFET. It provides a single highly efficient solution with current mode control for fast loop response and easy compensation. It features a wide input voltage range, internal soft-start control and precision current limiting. Its very low operational quiescent current makes it suitable for battery powered applications. MP2562 Rev. 0.91 4/5/2010 PWM Control At moderate to high output current, the MP2562 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off for at least 100ns before the next cycle starts. If, in one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET remains on, saving a turn-off operation. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 7 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER Error Amplifier The error amplifier compares the FB pin voltage with the internal reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge the external compensation network to form the COMP voltage, which is used to control the power MOSFET current. During operation, the minimum COMP voltage is clamped to 0.9V and its maximum is clamped to 2.0V. COMP is internally pulled down to GND in shutdown mode. COMP should not be pulled up beyond 2.6V. Internal Regulator Most of the internal circuitries are powered from the 2.6V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 3.0V, the output of the regulator is in full regulation. When VIN is lower than 3.0V, the output decreases. Enable Control The MP2562 has a dedicated enable control pin (EN). With high enough input voltage, the chip can be enabled and disabled by EN which has positive logic. Its falling threshold is a precision 1.2V, and its rising threshold is 1.5V (300mV higher). When floating, EN is pulled up to about 3.0V by an internal 1µA current source so it is enabled. To pull it down, 1µA current capability is needed. When EN is pulled down below 1.2V, the chip is put into the lowest shutdown current mode. When EN is higher than zero but lower than its rising threshold, the chip is still in shutdown mode but the shutdown current increases slightly. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The UVLO rising threshold is about 3.0V while its falling threshold is a consistent 2.6V. MP2562 Rev. 0.91 4/5/2010 Internal Soft-Start The soft-start is implemented to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V to 2.6V. When it is lower than the internal reference (REF), SS overrides REF so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than its upper threshold, it shuts down the whole chip. When the temperature is lower than its lower threshold, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor is charged and regulated to about 5V by the dedicated internal bootstrap regulator. When the voltage between the BST and SW nodes is lower than its regulation, a PMOS pass transistor connected from VIN to BST is turned on. The charging current path is from VIN, BST and then to SW. External circuit should provide enough voltage headroom to facilitate the charging. As long as VIN is sufficiently higher than SW, the bootstrap capacitor can be charged. When the power MOSFET is ON, VIN is about equal to SW so the bootstrap capacitor cannot be charged. When the external diode is on, the difference between VIN and SW is largest, thus making it the best period to charge. When there is no current in the inductor, SW equals the output voltage VOUT so the difference between VIN and VOUT can be used to charge the bootstrap capacitor. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 8 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER At higher duty cycle operation condition, the time period available to the bootstrap charging is less so the bootstrap capacitor may not be sufficiently charged. In case the internal circuit does not have sufficient voltage and the bootstrap capacitor is not charged, extra external circuitry can be used to ensure the bootstrap voltage is in the normal operational region. Refer to External Bootstrap Diode in Application section. The DC quiescent current of the floating driver is about 20µA. Make sure the bleeding current at the SW node is higher than this value, such that: IO + VO > 20μA (R1 + R2) Current Comparator and Current Limit The power MOSFET current is accurately sensed via a current sense MOSFET. It is then fed to the high speed current comparator for the current mode control purpose. The current comparator takes this sensed current as one of its inputs. When the power MOSFET is turned on, the comparator is first blanked till the end of the turn-on transition to avoid noise issues. The comparator then compares the power switch current with the COMP voltage. When the sensed current is higher than the COMP voltage, the comparator output is low, turning off the power MOSFET. The cycle-by-cycle maximum current of the internal power MOSFET is internally limited. MP2562 Rev. 0.91 4/5/2010 Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. While the internal supply rail is up, an internal timer holds the power MOSFET OFF for about 50µs to blank the startup glitches. When the internal soft-start block is enabled, it first holds its SS output low to ensure the remaining circuitries are ready and then slowly ramps up. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, power MOSFET is turned off first to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. Programmable Oscillator The MP2562 oscillating frequency is set by an external resistor, Rfreq from the FREQ pin to ground. The value of Rfreq can be calculated from: R freq (KΩ) = 180000 fs (KHz)1.1 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 9 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER APPLICATION INFORMATION COMPONENT SELECTION Setting the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin. The voltage divider divides the output voltage down to the feedback voltage by the ratio: VFB = VOUT R2 R1 + R2 Thus the output voltage is: VOUT = VFB (R1 + R2) R2 About 20µA current from high side BS circuitry can be seen at the output when the MP2562 is at no load. In order to absorb this small amount of current, keep R2 under 40KΩ. A typical value for R2 can be 40.2kΩ. With this value, R1 can be determined by: R1 = 50.25 × ( VOUT − 0.8)(kΩ) For example, for a 3.3V output voltage, R2 is 40.2kΩ, and R1 is 127kΩ. Inductor The inductor is required to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. MP2562 Rev. 0.91 4/5/2010 A good rule for determining the inductance to use is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum switch current limit. The inductance value can be calculated by: L1 = ⎛ ⎞ VOUT V × ⎜1 − OUT ⎟⎟ fS × ΔIL ⎜⎝ VIN ⎠ Where VOUT is the output voltage, VIN is the input voltage, fS is the switching frequency, and ΔIL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated by: ILP = ILOAD + ⎛ ⎞ VOUT V × ⎜⎜1 − OUT ⎟⎟ 2 × fS × L1 ⎝ VIN ⎠ Where ILOAD is the load current. Table 1 lists a number of suitable inductors from various manufacturers. The choice of which style inductor to use mainly depends on the price vs. size requirements and any EMI requirement. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 10 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER Table 1—Inductor Selection Guide Inductance (µH) Max DCR (Ω) Current Rating (A) Dimensions L x W x H (mm3) 7447789002 2.2 0.019 4 7.3x7.3x3.2 7447789003 3.3 0.024 3.42 7.3x7.3x3.2 7447789004 4.7 0.033 2.9 7.3x7.3x3.2 744066100 10 0.035 3.6 10x10x3.8 744771115 15 0.025 3.75 12x12x6 744771122 22 0.031 3.37 12x12x6 RLF7030T-2R2 2.2 0.012 5.4 7.3x6.8x3.2 RLF7030T-3R3 3.3 0.02 4.1 7.3x6.8x3.2 RLF7030T-4R7 4.7 0.031 3.4 7.3x6.8x3.2 Part Number Wurth Electronics TDK SLF10145T-100 10 0.0364 3 10.1x10.1x4.5 SLF12565T-150M4R2 15 0.0237 4.2 12.5x12.5x6.5 SLF12565T-220M3R5 22 0.0316 3.5 12.5x12.5x6.5 FDV0630-2R2M 2.2 0.021 5.3 7.7x7x3 FDV0630-3R3M 3.3 0.031 4.3 7.7x7x3 FDV0630-4R7M 4.7 0.049 3.3 7.7x7x3 919AS-100M 10 0.0265 4.3 10.3x10.3x4.5 919AS-160M 16 0.0492 3.3 10.3x10.3x4.5 919AS-220M 22 0.0776 3 10.3x10.3x4.5 Toko Output Rectifier Diode The output rectifier diode supplies the current to the inductor when the high-side switch is off. To reduce losses due to the diode forward voltage and recovery times, use a Schottky diode. Choose a diode whose maximum reverse voltage rating is greater than the maximum input voltage, and whose current rating is greater than the maximum load current. Table 2 lists example Schottky diodes and manufacturers. Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. For simplification, choose the input capacitor with RMS current rating greater than half of the maximum load current. Table 2—Diode Selection Guide Diodes B280-13-F B290 CMSH2100M MP2562 Rev. 0.91 4/5/2010 Voltage/ Current Rating 80V, 2A 90V, 2A 100V, 2A Manufacturer Diodes Inc. Diodes Inc. Central Semi www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 11 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER The input capacitor (C1) can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ΔVIN = ⎛ ILOAD V V × OUT × ⎜1 − OUT fS × C1 VIN ⎜⎝ VIN ⎞ ⎟⎟ ⎠ Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: ΔVOUT = VOUT ⎛ V × ⎜⎜1 − OUT fS × L ⎝ VIN ⎞ ⎞ ⎛ 1 ⎟ ⎟⎟ × ⎜ R ESR + ⎜ 8 × f S × C2 ⎟⎠ ⎠ ⎝ Where L is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT = ⎛ ⎞ V × ⎜⎜1 − OUT ⎟⎟ VIN ⎠ × L × C2 ⎝ VOUT 8 × fS 2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT = VOUT ⎛ V × ⎜1 − OUT f S × L ⎜⎝ VIN ⎞ ⎟⎟ × R ESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP2562 can be optimized for a wide range of capacitance and ESR values. MP2562 Rev. 0.91 4/5/2010 Compensation Components MP2562 employs current mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP pin is the output of the internal error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC gain of the voltage feedback loop is given by: A VDC = R LOAD × G CS × A VEA × VFB VOUT Where AVEA is the error amplifier voltage gain, 200V/V; GCS is the current sense transconductance, 3.4A/V; RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3), the output resistor of error amplifier. The other is due to the output capacitor and the load resistor. These poles are located at: fP1 = GEA 2π × C3 × A VEA fP2 = 1 2π × C2 × R LOAD Where, GEA is the transconductance, 60μA/V. error amplifier The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: f Z1 = 1 2π × C3 × R3 The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: fESR = 1 2π × C2 × R ESR www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 12 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER In this case (as shown in TYPICAL APPLICATION), a third pole set by the compensation capacitor (C6) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: f P3 = 1 2π × C6 × R3 1. Choose the compensation resistor (R3) to set the desired crossover frequency. Determine the R3 value by the following equation: R3 = 2π × C2 × f C VOUT × G EA × G CS VFB Where fC is the desired crossover frequency. The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback loop has the unity gain is important. Lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies could cause system unstable. A good rule of thumb is to set the crossover frequency to approximately onetenth of the switching frequency. The Table 3 lists the typical values of compensation components for some standard output voltages with various output capacitors and inductors. The values of the compensation components have been optimized for fast transient responses and good stability at given conditions. Table 3—Compensation Values for Typical Output Voltage/Capacitor Combinations VOUT (V) L (µH) C2 (µF) R3 (kΩ) C3 (pF) C6 (pF) 1.8 4.7 22 120 100 None 2.5 4.7 - 6.8 22 82 330 None 3.3 6.8 -10 22 120 220 None 5 15 - 22 22 158 150 None 12 22 - 33 22 287 150 None 2. Choose the compensation capacitor (C3) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero, fZ1, below one forth of the crossover frequency provides sufficient phase margin. Determine the C3 value by the following equation: C3 > 4 2π × R3 × f C 3. Determine if the second compensation capacitor (C6) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: f 1 < S 2π × C2 × R ESR 2 If this is the case, then add the second compensation capacitor (C6) to set the pole fP3 at the location of the ESR zero. Determine the C6 value by the equation: C6 = C2 × R ESR R3 To optimize the compensation components for conditions not listed in Table 3, the following procedure can be used. MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 13 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER High Frequency Operation The switching frequency of MP2562 can be programmed up to 4MHz by an external resistor. Please pay attention to the following if the switching frequency is above 2MHz. The minimum on time of MP2562 is about 100ns (typ). Pulse skipping operation can be seen more easily at higher switching frequency due to the minimum on time. Recommended operating voltage is 12V or below, and 24V or below at 2MHz. Refer to Figure 2 below for detailed information. 30 Recommended VIN (max) vs Switching Frequency VIN (MAX) (V) 25 20 15 VOUT=3.3V 10 VOUT=2.5V 5 1500 2000 2500 3000 3500 4000 fs (KHz) Figure 2—Recommend Max VIN vs. fS Since the internal bootstrap circuitry has higher impedance, which may not be adequate to charge the bootstrap capacitor during each (1D)×Ts charging period, an external bootstrap charging diode is strongly recommended if the switching frequency is above 2MHz (see External Bootstrap Diode section for detailed implementation information). With higher switching frequencies, the inductive reactance (XL) of capacitor comes to dominate, so that the ESL of input/output capacitor determines the input/output ripple voltage at higher switching frequency. As a result of that, high frequency ceramic capacitor is strongly recommended as input decoupling capacitor and output filtering capacitor for such high frequency operation. Layout becomes more important when the device switches at higher frequency. It is essential to place the input decoupling capacitor, catch diode and the MP2562 (Vin pin, SW pin and PGND) as close as possible, with traces that are very short and fairly wide. This can help to greatly reduce the voltage spike on SW node, and lower the EMI noise level as well. Try to run the feedback trace as far from the inductor and noisy power traces as possible. It is often a good idea to run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two. The compensation components should be placed closed to the MP2562. Do not place the compensation components close to or under high dv/dt SW node, or inside the high di/dt power loop. If you have to do so, the proper ground plane must be in place to isolate those. Switching loss is expected to be increased at high switching frequency. To help to improve the thermal conduction, a grid of thermal vias can be created right under the exposed pad. It is recommended that they be small (15mil barrel diameter) so that the hole is essentially filled up during the plating process, thus aiding conduction to the other side. Too large a hole can cause ‘solder wicking’ problems during the reflow soldering process. The pitch (distance between the centers) of several such thermal vias in an area is typically 40mil. Please refer to the PCB layout guide and example on EV2562 datasheet. External Bootstrap Diode It is recommended that an external bootstrap diode be added when the input voltage is no greater than 5V or the 5V rail is available in the system. This helps improve the efficiency of the regulator. The bootstrap diode can be a low cost one such as IN4148 or LL4148. 5V BST MP2562 SW Figure 3—External Bootstrap Diode MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 14 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER This diode is also recommended for high duty cycle operation (when VOUT/VIN >65%) or low VIN (<5Vin) applications. At no load or light load, the converter may operate in pulse skipping mode in order to maintain the output voltage in regulation. Thus there is less time to refresh the BS voltage. In order to have enough gate voltage under such operating conditions, the difference of (VIN – VOUT) should be greater than 3V. For example, if the VOUT is set to 3.3V, the VIN needs to be higher than 3.3V+3V=6.3V to maintain enough BS voltage at no load or light load. To meet this requirement, EN pin can be used to program the input UVLO voltage to Vout+3V. MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 15 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS C4 100nF 10 8,9 VIN C1 100V VIN BST L1 SW 1,2 C2 D1 R5 3 EN EN R6 7 MP2562 FB R1 4 C3 100pF GND R4 6.3V 5 R2 COMP FREQ VOUT 1.8V 6 R3 C6 NS Figure 4—1.8V Output Typical Application Schematic C4 100nF 10 8,9 VIN C1 100V VIN BST L1 SW 1,2 C2 D1 R5 3 EN EN R6 7 MP2562 6 6.3V 5 R1 R2 COMP FREQ GND R4 FB VOUT 5V 4 C3 150pF R3 C6 NS Figure 5—5V Output Typical Application Schematic MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 16 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER PCB LAYOUT GUIDE PCB layout is very important to achieve stable operation. It is highly recommended to duplicate EVB layout for optimum performance. 1) If change is necessary, please follow these guidelines and take Figure 6 for reference. 2) Keep the path of switching current short and minimize the loop area formed by Input cap, high-side MOSFET and external switching diode. 3) Bypass ceramic capacitors are suggested to be put close to the VIN Pin. 4) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 5) Route SW away from sensitive analog areas such as FB. 6) Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. MP2562 MP2562 Typical Application Circuit TOP Layer Bottom Layer MP2562DS Layout Guide MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 17 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER GND R5 C3 R4 3 SW 1 EN SW 2 FB 5 COMP 4 R1 R2 R3 L1 SW C4 8 9 Vin Vin 10 BST 7 FREQ 6 GND D1 R6 C2 C1 Vin GND GND Vo TOP Layer Bottom Layer MP2562DQ Layout Guide Figure 6―MP2562 Typical Application Circuit and PCB Layout Guide MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 18 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER PACKAGE INFORMATION 3mm x 3mm QFN10 2.90 3.10 0.30 0.50 PIN 1 ID MARKING 0.18 0.30 2.90 3.10 PIN 1 ID INDEX AREA 1.45 1.75 PIN 1 ID SEE DETAIL A 10 1 2.25 2.55 0.50 BSC 5 6 TOP VIEW BOTTOM VIEW PIN 1 ID OPTION A R0.20 TYP. PIN 1 ID OPTION B R0.20 TYP. 0.80 1.00 0.20 REF 0.00 0.05 SIDE VIEW DETAIL A NOTE: 2.90 0.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5. 5) DRAWING IS NOT TO SCALE. 1.70 0.25 2.50 0.50 RECOMMENDED LAND PATTERN MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 19 MP2562 – 1A, 4MHz, 50V STEP-DOWN CONVERTER SOIC8 0.189(4.80) 0.197(5.00) 0.050(1.27) 0.024(0.61) 8 5 0.063(1.60) 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.213(5.40) 4 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.013(0.33) 0.020(0.51) 0.0075(0.19) 0.0098(0.25) SEE DETAIL "A" 0.050(1.27) BSC SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2562 Rev. 0.91 4/5/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 20