MP4470/4470A High-Efficiency, Fast-Transient, 5A, 36V Synchronous, Step-Down Converter The Future of Analog IC Technology DESCRIPTION FEATURES The MP4470/4470A is a fully-integrated, highfrequency, synchronous, rectified, step-down, switch-mode converter. It offers a very compact solution to achieve a 5A, continuous-output current over a wide input-supply range with excellent load and line regulation. It also provides fast transient response and good stability for wide input-supply and load range. The MP4470/4470A operates at high efficiency over a wide output current load range. • • • MP4470 has full protection features include SCP, OCP, OVP latch, UVP, and thermal shutdown. MP4470A has the same protection features to MP4470 except has no OVP latch function. The MP4470/4470A requires a minimal number of readily-available, standard, external components, and is available in a space-saving 3mm×4mm, 20-pin, QFN package. • • • • • • • • Wide 4.5V-to-36V Operating Input Range Guaranteed 5A, Continuous Output Current Internal 40mΩ High-Side, 20mΩ Low-Side Power MOSFETs Proprietary Switching-Loss-Reduction Technology 1% Reference Voltage Programmable Soft-Start Time Low Drop-out Mode 200kHz-to-1MHz Switching Frequency SCP, OCP, OVP Latch(MP4470 only), UVP, and Thermal Shutdown Output Adjustable from 0.8V to 0.9×VIN Available in a 3×4mm 20-pin QFN Package APPLICATIONS • • • • • • Notebook Systems and I/O Power Automotive Systems Networking Systems Industrial Supplies Optical Communications Systems Distributed Power and POL Systems All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1 OUTPUT CURRENT (A) MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 1 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER ORDERING INFORMATION Part Number* Package Top Marking MP4470GL MP4470AGL QFN20 (3×4mm) QFN20 (3×4mm) 4470 4470A * For Tape & Reel, add suffix –Z (e.g. MP4470/4470AGL–Z) PACKAGE REFERENCE 20 1 19 18 17 16 21 IN 2 24 SW 3 22 IN 4 25 SW 5 23 IN 6 7 15 14 13 12 11 8 9 10 QFN20 (3×4mm) ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VIN ....................................... 40V VSW ........................................-0.3V to VIN + 0.3V VBST ...................................................... VSW + 6V VPGOOD ....................................-0.3V to VCC+0.6V All Other Pins ..................................-0.3V to +6V (2) Continuous Power Dissipation (TA = +25°C) ………………………………… …………….2.6W Operating Junction Temperature ..............150°C Lead Temperature ....................................260°C Storage Temperature............... -65°C to +150°C Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC QFN20 (3×4mm) .....................48 ...... 10 ... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. Supply Voltage VIN ...........................4.5V to 36V Output Voltage VOUT ................... 0.8V to 0.9×VIN Operating Junction Temp. (TJ). -40°C to +125°C MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 24V, VEN = 2V, TA = +25°C, unless otherwise noted. Parameters Supply Current (Shutdown) Supply Current (Quiescent) HS Switch On Resistance LS Switch On Resistance (5) Switch Leakage Symbol IIN IIN HSRDS-ON LSRDS-ON SWLKG Current Limit tON Minimum Off Time(5) tOFF (5) tFB Foldback Off Time(5) tFB OCP Hold-Off Time(5) Feedback Voltage Feedback Current Soft-Start Charging Current Power-Good Rising Threshold Power-Good Falling Threshold Power-Good Threshold Hysteresis Power-Good Rising Delay EN Rising Threshold EN Falling Threshold EN Threshold Hysteresis EN Input Current VIN Under-Voltage Lockout Threshold Rising VIN Under-Voltage Lockout Threshold Hysteresis VCC Regulator VCC Load Regulation Vo Over-Voltage Protection Threshold (6) Thermal Shutdown(5) Thermal Shutdown Hysteresis(5) tOC VFB IFB ISS PGVth-Hi PGVth-Lo PGVth-Hys tPG ENVth-Hi ENVth-Lo ENVth-Hys IEN Min VEN = 0V VSW = 0V or 36V ILIMIT One-Shot On Time Foldback Off Time Condition VEN = 0V VFB = 0.95V VIN=12V, RFREQ=30kΩ 10 200 nA 230 280 6 0.87 0.82 500 1.1 0.8 VEN = 2V 3.7 A 330 ICC=0 ICC=10mA 4.5 ns 100 ns 4.8 μs 16.8 μs 100 815 10 8.5 0.9 0.85 0.05 700 1.25 0.86 390 1.5 4.0 2 μs mV nA μA VFB VFB VFB μs V V mV μA 4.3 V 823 50 11 0.93 0.88 900 1.4 0.92 880 INUVHYS VCC Units nA μA mΩ mΩ 8 807 INUVVth Max 200 600 55 6 ILIM=1(HIGH), VFB>50%VREF ILIM=1(HIGH), VFB<50%VREF ILIM=1(HIGH) VFB = 815mV VSS=0V Typ 10 500 40 20 4.85 1 mV 5.2 V % VOVP 1.25 VFB TSD 175 45 °C °C TSD-HYS Note: 5) Derived from bench characterization, not tested in production. 6) For MP4470 only. MP4470A has no OVP function. MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 24V, VOUT = 3.3V, L = 10µH, TA = +25°C, unless otherwise noted. Efficiency vs. Load Current 800 550 100 90 700 80 70 600 60 500 500 50 40 400 30 20 300 10 0 0.01 0.1 1 10 450 Case Temperature Rise vs. Output Current 40 0 5 10 15 20 25 30 35 40 VIN (V) Line Regulation 3 3.5 4 4.5 5 1.00 1.00 30 0.50 0.50 25 20 0.00 15 0.00 -0.50 10 -0.50 -1.00 5 0 2 2.5 Load Regulation 1.50 35 200 1 1.5 0 1 2 3 4 5 -1.50 0 10 20 30 40 -1.00 0 1 2 MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 4 5 4 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) VIN = 24V, VOUT = 3.3V, L = 10µH, TA = +25°C, unless otherwise noted. VO(AC) 10mV/div. SW 10V/div. IL 500mA/div. VO(AC) 10mV/div. VIN 10V/div. VO 2V/div. IL 200mA/div. SW 20V/div. IL 1A/div. SW 10V/div. VIN 10V/div. VO 2V/div. VIN 10V/div. VIN 10V/div. VO 2V/div. VO 2V/div. IL 2A/div. IL 2A/div. IL 5A/div. SW 10V/div. SW 20V/div. SW 20V/div. EN 2V/div. EN 2V/div. EN 2V/div. VO 2V/div. VO 2V/div. IL 500mA/div. IL 5A/div. SW 20V/div. SW 20V/div. VO 2V/div. IL 2A/div. SW 20V/div. MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) VIN = 24V, VOUT = 3.3V, L = 10µH, TA = +25°C, unless otherwise noted. MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER PIN FUNCTIONS Pin # Name Description 1 AGND Analog Ground. 2 FREQ Frequency Set (for CCM). The input voltage and the frequency-set resistor connected to GND determine the ON period. Decouple with a 1nF capacitor. 3 FB Feedback. The tap of external resistor divider from the output to GND sets the output voltage. 4 SS Soft-Start. Connect an external capacitor to program the soft-start time for the switch-mode regulator. When the EN pin goes HIGH, an internal current source (8.5µA) charges up the capacitor and the SS voltage slowly and smoothly ramps up from 0 to VFB. When the EN pin goes LOW, the internal current source discharges the capacitor and the SS voltage slowly ramps down. 5 EN Enable. EN=1 to enable the MP4470/4470A. For automatic start-up, connect EN pin to IN with a 100kΩ resistor. It includes an internal 1MΩ pull-down resistor. 6 7 8, 19, Exposed pads 21, 22, 23 9, 10, 17, 18, Exposed pads 24, 25 PGOOD Power Good Output. The output of this pin is an open drain and goes HIGH if the output voltage exceeds 90% of the nominal voltage. There is delay of ~700µs from FB ≥ 90% to PGOOD HIGH. BST Bootstrap. Requires a 0.1µF-to-1µF capacitor connected between SW and BS pins to form a floating supply across the high-side switch driver. IN Supply Voltage. The MP4470/4470A operates from a 4.5V-to-36V input rail. Requires CIN to decouple the input rail. Connect using wide PCB traces and multiple vias. SW Switch Output. Connect using wide PCB traces and multiple vias. 11-16 PGND System Ground. This pin is the reference ground of the regulated output voltage. For this reason care must be taken in PCB layout. 20 VCC Internal Bias Supply. Decouple with a 1µF capacitor as close to the pin as possible. MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER BLOCK DIAGRAM Figure 1—Functional Block Diagram MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER goes to zero. In CCM, the switching frequency (fSW) is fairly constant. OPERATION PWM Operation The MP4470/4470A is a fully-integrated, synchronous, rectified, step-down, switch-mode converter. At the beginning of each cycle, the high-side MOSFET (HS-FET) turns ON when the feedback voltage (VFB) drops below the reference voltage (VREF), which indicates an insufficient output voltage. The ON period is determined by the input voltage and the frequency-set resistor as: t ON ( ns ) = 96 × RFREQ ( kΩ ) VIN + tDELAY (ns) (1) After the ON period elapses, the HS-FET turns OFF. It is turned ON again when VFB drops below VREF. By repeating this operation, the converter regulates the output voltage. The integrated lowside MOSFET (LS-FET) turns ON when the HSFET is OFF to minimize conduction loss. A dead short occurs between input and GND if both the HS-FET and the LS-FET turn on at the same time (shoot-through). An internal dead-time (DT) generated between HS-FET OFF and LS-FET ON, or LS-FET OFF and HS-FET ON prevents shoot-through. Heavy-Load Operation tON Light-Load Operation At light-load or no-load conditions, the output drops very slowly and the MP4470/4470A reduces the switching frequency automatically to maintain high efficiency. Figure 3 shows the lightload operation. VFB does not reach VREF as the inductor current approaches zero. The LS-FET driver enters a tri-state (high Z) whenever the inductor current reaches zero. A current modulator takes control of the LS-FET and limits the inductor current to less than -1mA. Hence, the output capacitors discharge slowly to GND through the LS-FET to greatly improve the lightload efficiency. At light loads, the HS-FET does not turn ON as frequently as at heavy loads. This is called skip mode. tON Figure 3: Light-Load Operation As the output current increases from light-load condition, the current modulator’s regulatory time period becomes shorter. The HS-FET turns ON more frequently, thus increasing the switching frequency increases. The output current reaches its critical level when the current modulator time is zero. The critical output current level is: IOUT = (VIN − VOUT ) × VOUT 2 × L × FSW × VIN (2) It enters PWM mode once the output current exceeds the critical level. After that, the switching frequency stays fairly constant over the output current range. Figure 2: Heavy-Load Operation In continuous-conduction mode (CCM), when the output current is HIGH, the HS-FET and LS-FET repeatedly turn ON/OFF as shown in MPS. All Rights Reserved. The inductor current never Switching Frequency The input voltage is feed-forwarded to the ontime one-shot timer through the resistor, RFREQ. The duty ratio remains at VOUT/VIN. Hence, the switching frequency is fairly constant over the input voltage range. The switching frequency can be set as: MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER FSW (kHz) = 106 96 × RFREQ (kΩ) V + tDELAY (ns)] × IN [ VIN VOUT (3) IR4 Where tDELAY is the comparator delay (~20ns). The MP4470/4470A is optimized for 200kHz-to1MHz applications to operate at high switching frequencies with high efficiency. The highswitching frequency allows for smaller LC-filter components to reduce PCB space requirements. Ramp Compensation Figure 4 and Figure 5 show jitter occurring in both PWM mode and skip mode. Noise on VFB’s downward slope causes the HS-FET ON time to deviate from its intended position and produces jitter. There is a relationship between system stability and the steepness of the VFB ripple: The slope steepness of the VFB ripple dominates noise immunity. The magnitude of the VFB ripple doesn’t affect the noise immunity directly. IC4 IFB Figure 6: Simplified Circuit in PWM Mode with External Ramp Compensation In PWM mode has an equivalent circuit with HSFET OFF and uses a external ramp compensation circuit (R4, C4), shown as a simplified circuit in Figure 6. Derive the external ramp from the inductor-ripple current. Choose C4, R1, and R2 to meet the following condition: 1 1 ⎛ R × R2 ⎞ < ×⎜ 1 ⎟ 2π × FSW × C4 5 ⎝ R1 + R 2 ⎠ (4) Then: IR4 = IC4 + IFB ≈ IC4 (5) The VFB downward slope ripple is then estimated as: VSLOPE1 = Figure 4: Jitter in PWM Mode − VOUT R 4 × C4 (6) From equation 6, reduce R4 or C4 to reduce instability in PWM mode. If C4 cannot be reduced further due to equation 4’s limitations, then only reduce R4. Based on bench experiments, VSLOPE1 is around 20V/ms-40V/ms. In the case of POSCAP or other types of capacitors with higher ESR, an external ramp is not necessary. Figure 3: Jitter in Skip Mode Ceramic output capacitors lack enough ESR ripple to stabilize the system, and requires an external compensation ramp. Figure 7: Simplified Circuit in PWM Mode without External Ramp Compensation MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER Figure 7 shows an equivalent circuit in PWM mode with the HS-FET OFF and without an external ramp circuit. The ESR ripple dominates the output ripple. The VFB downward slope is: VSLOPE1 = −ESR × VREF L (7) From equation 7, the VFB downward slope is proportional to ESR/L. Therefore, it’s necessary to know the minimum ESR value of the output capacitors without an external ramp. There is also an inductance limit: A smaller inductance leads to more stability. Based on bench experiments, keep VSLOPE1 around 15V/ms to 30V/ms. In skip mode, the external ramp does not affect the downward slope, and VFB ripple’s downward slope is the same with or without the external ramp. Figure 8 shows an equivalent circuit with the HS-FET off and the current modulator regulating the LS-FET. ramps up with VSS. Once VSS reaches the same level as VREF, it continues ramping up while VREF takes over the PWM comparator. At this point, soft-start finishes and the MP4470/4470A enters steady-state. CSS is then: CSS ( nF ) = t SS ( ms ) × ISS ( μA ) VREF ( V ) (9) If the output capacitors have large capacitance values, avoid setting a short SS or risk hitting the current limit during SS. Select a minimum value of 4.7nF if the output capacitance value exceeds 330μF. Power Good (PGOOD) The MP4470/4470A has power-good (PGOOD) output. The PGOOD pin is the open drain of a MOSFET. It should connect to VCC or some other voltage source through a resistor (e.g. 100kΩ). In the presence of an input voltage, the MOSFET turns ON so that the PGOOD pin is pulled to GND before SS is ready. After VFB reaches 90%×VREF, the PGOOD pin is pulled HIGH after a delay; typically 700μs. When the FB voltage drops to 85%×VREF, the PGOOD pin is pulled LOW. Over-Current Protection (OCP) and ShortCircuit Protection (SCP) IMOD Figure 8: Simplified Circuit in Skip Mode The VFB ripple’s downward slope is: VSLOPE2 = − VREF (R1 + R2 ) × COUT (8) The MP4470/4470A has cycle-by-cycle overcurrent limit control. The inductor current is monitored during the ON state. Once the inductor current exceeds the current limit, the HS-FET turns OFF. At the same time, the OCP timer starts. The OCP timer is set at 100μs. Hitting the current limit during each cycle during this 100μs time frame will trigger hiccup SCP. To keep the system stable during light loads, avoid large VFB resistors. Also, keep the VSLOPE2 value around 0.4V/ms to 0.8mV/ms. Note that IMOD is excluded from the equation because it does not impact the system’s light-load stability. If a short circuit occurs, the MP4470/4470A will immediately hit its current limit and VFB will drop below 50%×VREF (0.815V). The device considers this an output dead short and will trigger hiccup SCP immediately. Soft-Start The MP4470/4470A employs soft start (SS) to ensure a smooth output during power-up. When the EN pin goes HIGH, an internal current source (8.5μA) charges up the SS capacitor (CSS). The CSS voltage takes over the REF voltage to the PWM comparator. The output voltage smoothly Over/Under-Voltage Protection (OVP/UVP) The MP4470 monitors the output voltage through the tap of a resistor divider to the FB pin to detect output over-voltage conditions. A VFB that exceeds 125%×VREF (0.815V) triggers OVP latchoff. Once OVP triggers, the LS-FET turns on to MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER discharge VO until the inductor current drops to zero while the HS-FET remains off. The MP4470 needs to power cycle to restart. Note that MP4470A has no this OVP function. The MP4470/4470A also monitors FB pin voltage to detect output under-voltage condition. A VFB drop below 50% ×VREF triggers UVP as well as a current-limit that triggers SCP. UVLO Protection The MP4470/4470A has under-voltage lock-out protection (UVLO). When the input voltage is higher than the UVLO rising threshold voltage, the MP4470/4470A will be powered up. It shuts off when the input voltage is lower than the UVLO falling threshold voltage. This is non-latch protection. Floating Driver and Bootstrap Charging An external bootstrap capacitor power the floating-power-MOSFET driver. A dedicated internal regulator charges and regulates the bootstrap capacitor voltage to ~5V. When the voltage between the BST and SW nodes drops below regulation, a PMOS pass transistor connected from VIN to BST turns on. The charging current path is from VIN, BST and then to SW. The external circuit should provide enough voltage headroom to facilitate charging. At higher duty cycles, the bootstrap-charging time is shorter so the bootstrap capacitor may not charge sufficiently. In case the internal circuit has insufficient voltage and time to charge the bootstrap capacitor, the bootstrap capacitor voltage will drop low. When VBST−VSW drops below 2.3V, the HS-FET turns OFF. A UVLO circuit allows the LS-FET to conduct and refresh the charge on the bootstrap capacitor. Once bootstrap capacitor voltage is charged, the HSFET can turn on again and the part resumes normal switching. With this bootstrap refreshing function, MP4470/4470A is able to work on the low drop-out mode. Thermal Shutdown The MP4470/4470A uses thermal shutdown. The junction temperature of the IC is internally monitored. If the junction temperature exceeds the threshold value (typically 175°C), the converter shuts off. This is a non-latched protection. There is about 45°C hysteresis. Once the junction temperature drops to about 130°C, it initiates a SS. As long as VIN is significantly higher than SW, the bootstrap capacitor remains charged. When the HS-FET is ON, VIN≈VSW so the bootstrap capacitor cannot charge. When the LS-FET is ON, VIN−VSW reaches its maximum for fast charging. When there is no inductor current, VSW=VOUT so the difference between VIN and VOUT can charge the bootstrap capacitor. MP4470/4470A Rev.0.8 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. Preliminary Specifications Subject to Change © 2013 MPS. All Rights Reserved. 12 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER APPLICATION INFORMATION Setting the Output Voltage A resistor divider from the output voltage to the FB pin set VOUT. Without an external ramp employed, the feedback resistors (R1 and R2) set the output voltage. To determine the values for the resistors, first, choose R2 (typically 5kΩ-40kΩ). Then R1 is: R1 = (10) VOUT − VREF × R2 VREF When using a low-ESR ceramic capacitor on the output, add an external voltage ramp to the FB pin through R4 and C4. The ramp voltage (VRAMP) affects output voltage. Calculate VRAMP as per equation 19. Choose R2 between 5kΩ and 40kΩ. Determine R1 as: 1 ⎛ VREF + VRAMP ⎜ 1 2 R1 = ⎜ − 1 R4 ⎜ ⎜ R 2 × ( VOUT − VREF − VRAMP ) 2 ⎝ −1 ⎞ ⎟ ⎟ (11) ⎟ ⎟ ⎠ Input Capacitor The input current to the step-down converter is discontinuous, and Therefore requires a capacitor to supply the AC current to the stepdown converter while maintaining the DC input voltage. Ceramic capacitors are recommended for best performance. Be sure to place the input capacitors as close to the IN pin as possible. The capacitance varies significantly with temperature. Capacitors with X5R and X7R ceramic dielectrics are are fairly stable over temperature fluctuations. The capacitors must also have a ripple-current rating greater than the converter’s maximum input-ripple current. The input ripple current can be estimated as follows: ICIN = IOUT × VOUT V × (1 − OUT ) VIN VIN (12) The worst-case condition occurs at VIN = 2VOUT, where: ICIN = IOUT 2 (13) Using equation 11 to calculate the output voltage can be complicated. Furthermore, as VRAMP changes due to changes in VOUT and VIN, VFB also varies. To improve the output voltage accuracy and simplify the R2 calculation from equation 11, add a DC-blocking capacitor (CDC). Figure 9 shows a simplified circuit with external ramp compensation and a DC-blocking capacitor. Equation 10 can then estimate R1) For simplification, choose an input capacitor whose RMS current rating is greater than half of the maximum load current.The input capacitance value determines the input voltage ripple of the converter. If there is an input-voltage-ripple requirement in the system design, choose an input capacitor that meets the specification Select a CDC value between 1µF and 4.7μF to improve DC-blocking performance. The input voltage ripple can be estimated as follows: ΔVIN = Cdc IOUT V V × OUT × (1 − OUT ) FSW × CIN VIN VIN (14) The worst-case condition occurs at VIN = 2VOUT, where: ΔVIN = I 1 × OUT 4 FSW × CIN (15) Figure 9: Simplified Circuit with External Ramp Compensation and DC Blocking Capacitor MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic or POSCAP capacitors. The output voltage ripple can be estimated as: V V 1 ΔVOUT = OUT × (1 − OUT ) × (RESR + ) (16) FSW × L 8 × FSW × COUT VIN Where RESR is the equivalent series resistance of the output capacitor. For ceramic capacitors, capacitance dominates the impedance at the switching frequency, can is the primary cause of the output-voltage ripple. For simplification, estimate the output voltage ripple as: ΔVOUT = VOUT V × (1 − OUT ) 2 8 × FSW × L × COUT VIN (17) The output voltage ripple caused by ESR is very small and therefore requires an external ramp to stabilize the system. The voltage ramp is ~30mV. The external ramp can be generated through R4 and C4 using the following equation: VRAMP = (VIN − VOUT ) × TON R4 × C4 (18) 2π × FSW × C4 < 1 R1× R2 ×( ) 5 R1 + R2 Where ΔIL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated as: ILP = IOUT + Select C4 to meet the following condition: 1 Inductor The inductor is required to supply constant current to the output load while being driven by the switching input voltage. A larger inductance will result in less ripple current and a lower output ripple voltage. However, a larger inductance resultsin a larger inductor, which will physically larger, and have a higher series resistance and/or lower saturation current. A good rule for determining the inductor value is to allow the peak-to-peak ripple current in the inductor to be approximately 30% to 40% of the maximum switch current limit. Ensure that the peak inductor current is below the maximum switch current limit. The inductance value can be calculated as: VOUT V (21) L= × (1 − OUT ) FSW × ΔIL VIN VOUT V × (1 − OUT ) 2FSW × L VIN (22) (19) For POSCAP capacitors, the ESR dominates the impedance at the switching frequency. The ramp voltage generated from the ESR is high enough to stabilize the system. Therefore, an external ramp is not needed. A minimum ESR value of 12mΩ is required to ensure stable operation of the converter. For simplification, the output ripple can be approximated as: ΔVOUT = VOUT V × (1 − OUT ) × RESR (20) FSW × L VIN MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER Typical Design Parameter Tables Table 3—700kHz, 24VIN The following tables include recommended component values for typical output voltages (3.3V, 5V) and switching frequencies (300kHz, 500kHz, and 700kHz). Refer to Tables 1 through 3 for design cases without external ramp compensation, and Tables 4 through 6 for design cases with external ramp compensation. An external ramp is not needed when using highESR capacitors, such as electrolytic or POSCAPs. An external ramp is needed when using low-ESR capacitors, such as ceramic capacitors. For cases not listed in this datasheet, an Excel spreadsheet available through your local sales representative can calculate approximate component values. Table 1—300kHz, 24VIN VOUT (V) 3.3 5 L (μH) 10 10 VOUT (V) 3.3 5 L (μH) 10 10 R1 (kΩ) 30.1 51.1 R2 (kΩ) 10 10 RFREQ (kΩ) 110 169 VOUT (V) 3.3 5 L (μH) 10 10 R1 (kΩ) 30.1 51.1 R2 (kΩ) 10 10 RFREQ (kΩ) 44.2 69.8 Table 4—300kHz, 24VIN VOUT (V) 3.3 5 L (μH) 10 10 R1 (kΩ) 30.9 53.6 R2 (kΩ) 10 10 R4 (kΩ) 953 845 C4 (pF) 390 560 RFREQ (kΩ) 110 169 Table 5—500kHz, 24VIN VOUT (V) 3.3 5 L (μH) 10 10 R1 (kΩ) 31.6 53.6 R2 (kΩ) 10 10 R4 (kΩ) 620 845 C4 (pF) 390 390 RFREQ (kΩ) 63.4 100 Table 6—700kHz, 24VIN VOUT (V) 3.3 5 L (μH) 10 10 R1 (kΩ) 31.6 54.9 R2 (kΩ) 10 10 R4 (kΩ) 560 620 C4 (pF) 390 390 RFREQ (kΩ) 44.2 69.8 Table 2—500kHz, 24VIN R1 (kΩ) 30.1 51.1 R2 (kΩ) 10 10 RFREQ (kΩ) 63.4 100 MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER LAYOUT RECOMMENDATION 1. Place high-current paths (GND, IN, and SW) very close to the device with short, direct, and wide traces. 2. Place input capacitors on both VIN sides (PIN8 and PIN19) and as close to the IN and GND pins as possible. 3. Place the decoupling capacitor as close to the VCC and GND pins as possible. 4. Keep the switching node SW short and away from the feedback network. 5. Place the external feedback resistors next to the FB pin. Do not place vias on the FB trace. 6. Keep the BST voltage path (BST, C3, and SW) as short as possible. 7. Connect the bottom IN and SW pads to a large copper area to achieve better thermal performance. 8. A Four-layer layout is strongly recommended to achieve better thermal performance. Inner1 Layer C1A C1B C1C Inner2 Layer C2A C2B Top Layer Bottom Layer Figure 10: PCB Layout MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS Figure 11: Typical Application Circuit, 3.3V-Output MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER PACKAGE INFORMATION 3mm × 4mm QFN20 NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP4470/4470A Rev. 1.1 www.MonolithicPower.com 8/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 18