NEC UPA1764

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1764
SWITCHING
DUAL N-CHANNEL POWER MOS FET
INDUSTRIAL USE
PACKAGE DRAWING (Unit : mm)
DESCRIPTION
The µPA1764 is N-channel MOS Field Effect
Transistor designed for high current switching
applications.
8
5
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
FEATURES
1.44
6.0 ±0.3
4
4.4
0.8
0.15
+0.10
–0.05
5.37 MAX.
0.05 MIN.
★
1
1.8 MAX.
★
★
★
• Dual chip type
• Low On-state Resistance
RDS(on)1 = 27 mΩ (TYP.) (VGS = 10 V, ID = 3.5 A)
RDS(on)2 = 32 mΩ (TYP.) (VGS = 4.5 V, ID = 3.5 A)
RDS(on)3 = 34 mΩ (TYP.) (VGS = 4.0 V, ID = 3.5 A)
• Low input capacitance
Ciss = 1300 pF (TYP.)
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1764G
Power SOP8
EQUIVALENT CIRCUIT
(1/2 circuit)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage
VDSS
60
V
Gate to Source Voltage
VGSS
±20
V
Drain Current (DC)
ID(DC)
±7
A
Drain Current (pulse)
Note1
ID(pulse)
±28
A
Total Power Dissipation (1 unit)
Note2
PT
1.7
W
Total Power Dissipation (2 unit)
Note2
PT
2.0
W
Tch
150
°C
Channel Temperature
Storage Temperature
Tstg
–55 to +150
°C
Single Avalanche Current
Note3
IAS
7
A
★ Single Avalanche Energy
Note3
EAS
98
mJ
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2
★
2. Mounted on ceramic substrate of 2000 mm x 2.2 mm
3. Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14329EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999,2000
µ PA1764
★ ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
Drain to Source On-state Resistance
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = 10 V, ID = 3.5 A
27
35
mΩ
RDS(on)2
VGS = 4.5 V, ID = 3.5 A
32
42
mΩ
RDS(on)3
VGS = 4.0 V, ID = 3.5 A
34
46
mΩ
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 3.5 A
5.0
9.0
Drain Leakage Current
IDSS
VDS = 60 V, VGS = 0 V
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
Input Capacitance
Ciss
VDS = 10 V
1300
pF
Output Capacitance
Coss
VGS = 0 V
230
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
110
pF
Turn-on Delay Time
td(on)
ID = 3.5 A
15
ns
VGS(on) = 10 V
69
ns
td(off)
VDD = 30 V
65
ns
tf
RG = 10 Ω
27
ns
Total Gate Charge
QG
ID = 7.0 A
29
nC
Gate to Source Charge
QGS
VDD = 48 V
3.6
nC
Gate to Drain Charge
QGD
VGS = 10 V
7.4
nC
VF(S-D)
IF = 7.0 A, VGS = 0 V
0.84
V
Reverse Recovery Time
trr
IF = 7.0 A, VGS = 0 V
40
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
66
nC
Gate to Source Cut-off Voltage
Rise Time
tr
Turn-off Delay Time
Fall Time
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
S
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG.
50 Ω
VDD
VGS = 20 → 0 V
RG
PG.
VGS
VGS
Wave Form
0
90 %
ID
VGS
0
ID
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1 %
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
2
IG = 2 mA
RL
50 Ω
VDD
10 %
0 10 %
Wave Form
τ
VDD
PG.
90 %
BVDSS
VDS
ID
90 %
VDD
ID
IAS
VGS(on)
10 %
Data Sheet G14329EJ1V0DS00
tr td(off)
td(on)
ton
tf
toff
µ PA1764
[MEMO]
Data Sheet G14329EJ1V0DS00
3
µ PA1764
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
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the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
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M7 98. 8