DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1840 N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING ORDERING INFORMATION DESCRIPTION The µPA1840 is N-channel MOS FET device that features a low on-state resistance and excellent switching characteristics, and designed for high voltage PART NUMBER PACKAGE µPA1840GR-9JG Power TSSOP8 applications such as DC/DC converter. FEATURES • High voltage rating VDSS = 200 V • Power TSSOP8 package (Single circuit) • Gate voltage rating ±30 V • Low on-state resistance RDS(on) = 0.5 Ω MAX. (VGS = 10 V, I D = 1.5 A) • Low input capacitance Ciss = 320 pF TYP. (VDS = 10 V, VGS = 0 V) • Built-in gate protection diode ABSOLUTE MAXIMUM RATINGS (T A = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 200 V Gate to Source Voltage (VDS = 0 V) VGSS ±30 V Drain Current (DC) (TC = 25°C) ID(DC) ±2.2 A ID(pulse) ±8.8 A PT 2.0 W Channel Temperature Tch 150 °C Storage Temperature Tstg –55 to +150 °C Drain Current (pulse) Note1 Total Power Dissipation Note2 Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2. Mounted on ceramic substrate of 5000 mm 2 x 1.1 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G14758EJ1V0DS00 (1st edition) Date Published November 2001 NS CP(K) Printed in Japan © 2000 µ PA1840 ELECTRICAL CHARACTERISTICS (T A = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 200 V, VGS = 0 V 100 µA Gate Leakage Current IGSS VGS = ±30 V, VDS = 0 V ±10 µA Gate Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 2.5 4.5 V Forward Transfer Admittance | yfs | VDS = 10 V, ID = 1.5 A 1.0 Drain to Source On-state Resistance RDS(on) VGS = 10 V, ID = 1.5 A 0.37 Input Capacitance Ciss VDS = 10 V 320 pF Output Capacitance Coss VGS = 0 V 96 pF Reverse Transfer Capacitance Crss f = 1 MHz 55 pF Turn-on Delay Time td(on) VDD = 100 V, ID = 1.5 A 14 ns Rise Time tr VGS = 10 V 13 ns Turn-off Delay Time td(off) RG = 10 Ω 30 ns Fall Time tf 13 ns Total Gate Charge QG VDD = 160 V 16 nC Gate to Source Charge QGS VGS = 10 V 2.3 nC Gate to Drain Charge QGD ID = 2.2 A 9.0 nC Body Diode Forward Voltage VF(S-D) IF = 2.2 A, VGS = 0 V 1.0 V Reverse Recovery Time trr IF = 2.2 A, VGS = 0 V 150 ns Reverse Recovery Charge Qrr di/dt = 50 A/µs 0.4 µC TEST CIRCUIT 1 SWITCHING TIME VGS VGS Wave Form 0 PG. VDD ID 90% 90% 10% 0 10% Wave Form τ = 1 µs Duty Cycle ≤ 1% tr td(off) td(on) ton IG = 2 mA RL 50 Ω VDD 90% ID τ 2 VGS 10% ID VGS 0 Ω 0.5 D.U.T. RL PG. S TEST CIRCUIT 2 GATE CHARGE D.U.T. RG 2.0 tf toff Data Sheet G14758EJ1V0DS µ PA1840 TYPICAL CHARACTERISTICS (T A = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA FORWARD BIAS SAFE OPERATING AREA 100 80 ID - Drain Current - A dT - Derating Factor - % 100 60 40 20 ID(pulse) 10 d ite im V) )L 10 (on = S RD VGS ID(DC) (@ 30 60 120 90 TA - Ambient Temperature - ˚C we rD isp ira 0.1 =1 ms ms tio TA = 25˚C Single Pulse Mounted on Ceramic 2 Substrate of 5000 mm x 1.1mm 150 nL im ite d 10 1 100 VDS - Drain to Source Voltage - V TRANSFER CHARACTERISTICS 10 Pulsed VDS = 10 V Pulsed 1 8 ID - Drain Current - A ID - Drain Current - A 10 0m s DC Po DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 10 10 1 0.01 0 PW VGS = 10 V 6 4 2 TA = −25˚C 25˚C 75˚C 125˚C 0.1 0.01 0.001 0.0001 0 0.0 1.0 3.0 2.0 4.0 5.0 0 1 VDS - Drain to Source Voltage - V 4.0 3.5 3.0 2.5 −50 0 50 100 150 | yfs | - Forward Transfer Admittance - S VGS(off) - Gate to Source Cut-off Voltage - V VDS = 10 V ID = 1 mA 3 4 5 6 7 8 9 VGS - Gate to Sorce Voltage - V 10 FORWARD TRANSFER ADMITTANCE Vs. DRAIN CURRENT GATE TO SOURCE CUTOFF VOLTAGE vs. CHANNEL TEMPERATURE 4.5 2 10 VDS = 10 V Pulsed 1 TA = −25˚C 25˚C 75˚C 125˚C 0.1 0.01 0.01 Tch - Channel Temperature - ˚C 0.1 1 10 ID - Drain Current - A Data Sheet G14758EJ1V0DS 3 1.0 VGS = 10 V Pulsed 0.8 TA = 125˚C 0.6 75˚C 0.4 25˚C 0.2 −25˚C 0 0.01 0.1 1 ID - Drain Current - A 10 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 1.0 ID = 1.5 A 0.8 0.6 VGS = 10 V 0.4 0.2 0 −50 0 50 100 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 1.0 ID = 1.5 A Pulsed 0.8 0.6 0.4 0.2 CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10000 f = 1 MHz VGS = 0 V 1000 Ciss 100 Coss Crss 10 0 0 10 20 1 0.1 VGS - Gate to Source Voltage - V 1 10 100 VDS - Drain Source Voltage - V SWITCHING CHARACTERISTICS td(on), tr, td(off), tf - Switching Time - ns 1000 100 tf td(off) tr td(on) 10 1 0.1 VDD = 100 V VGS = 10 V RG = 10 Ω 1 10 ID - Drain Current - A 4 150 Tch - Channel Temperature - ˚C Ciss, Coss, Crss - Capacitance - pF RDS (on) - Drain to Source On-state Resistance - Ω RDS(on) - Drain to Source On-state Resistance - Ω DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT RDS (on) - Drain to Source On-state Resistance - Ω µ PA1840 Data Sheet G14758EJ1V0DS 1000 µ PA1840 DYNAMIC INPUT CHARACTERISTICS 1 0.1 0.01 0.4 0.6 0.8 1.0 1.2 1.4 160 VDD = 160 V 140 18 16 14 100 V 120 12 40 V 100 10 80 8 VGS 60 40 6 4 VDS 20 0 1.6 ID = 2.2 A VGS = 10 V 2 45 6 8 2 VGS - Gate to Source Voltage - V 180 VDS - Drain to Source Voltage - V IF - Source to Drain Current - A SOURCE TO DRAIN DIODE FORWARD VOLTAGE 10 VGS = 0 V Pulsed 10 12 141516 18 20 Qg - Gate Charge - nC VF(S-D) - Source to Drain Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(ch-A) - Transient Thermal Resistance - ˚C/W 1000 Mounted on ceramic Substrate of 5000 mm2 x 1.1 mm Single Pulse 100 62.5˚C/W 10 1 0.1 0.001 0.01 0.1 1 10 100 1000 PW - Pulse Width - s Data Sheet G14758EJ1V0DS 5 µ PA1840 PACKAGE DRAWING (Unit: mm) Power TSSOP8 8 5 1, 8 : Drain 5 : Source 4 : Gate 2, 3, 6, 7: NC 1.2 MAX. 1.0±0.05 0.25 3° +5° –3° 0.1±0.05 1 4 6.4 ±0.2 0.27 0.145 ±0.055 3.15 ±0.15 3.0 ±0.1 0.65 0.5 0.6 +0.15 –0.1 4.4 ±0.1 0.1 0.8 MAX. +0.03 –0.08 1.0 ±0.2 0.10 M Caution The terminal assignment is different from that of the NEC standard Power TSSOP8 package. EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Source Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. 6 Data Sheet G14758EJ1V0DS µ PA1840 [MEMO] Data Sheet G14758EJ1V0DS 7 µ PA1840 • The information in this document is current as of November, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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