NEC UPD161644P

PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD161644
241 OUTPUT GATE DRIVER WITH POWER SUPPLY FOR TFT-LCD GATE DRIVER
DESCRIPTION
The µPD161644 is a TFT-LCD gate driver with power supply for TFT-LCD driver. Because this gate driver has a
level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. This
ICs can generate the levels which TFT-LCD driver need, from 2.7 V.
FEATURES
• High breakdown voltage output (VDD1-VSS3 = 40 V MAX.)
• 2.7 V CMOS level input
• Number of output: 241 output selectable
• To generate 4 levels from single voltage input
• To integrate regulator circuit for source driver
• Mode setting from source driver: Serial I/F or pin control
• On-chip VCOM driver
• On-chip gate output low-level selector
ORDERING INFORMATION
Part number
Package
µPD161644P
Chip
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15797EJ1V4PM00 (1st edition)
Date Published October 2002 NS CP(K)
Printed in Japan
The mark ! shows major revised points.
©
2001
µPD161644
1. BLOCK DIAGRAM/SYSTEM DIAGRAM
C1
C1+
C1-
C1
C2
C2-
DC/DC converter
+
VDC
+
C2
C3
C3+
C4
C2
C4C5 +
C5 -
C2
C6
C6 -
C2
V DD1
C2
VSS2
C2
VSS3
C2
DC/DC converter
+
DCCLK
GCS
GCL
GDA
VDD2
C2
DC/DC converter
VDC
OSC
VR
Regurator
VR
C2
Serial interface
register
VS
Regurator
VS
VREF
VSS4
C2
VGD
MVS
DCON
Source driver
C3 5 V
4V
RGONR
VCD2
VCIN
D/A
VMS
Common
driver
circuit
FS0
FS2
D/A
CLS0
RGON
VCOM
COMH
C2
COML
C2
VCOMIN
Switch
VSEL
EXRV
ACS0
Gate output
low level select circuit
SCN0
VM
SCN1
SCN2
IFSEL
PUPT0
/GRESET
DUPF0
R,/L
CLK
FRM
STVR
SR1
SR2
SR121 SR122
SR119 SR120
SR240
SR241
STVL
MPX
OE1
OE2
VMON
TESTIN1
TESTIN2
V DC
VCC1
TESTOUT1
TESTOUT2
VSS1
PV CC1
PVSS1
Level Shifter
VB
PVSS3
O1
O2
O119
O120
O122
O122
O240
O241
Remarks 1./xxx indicates active low signal.
2.Level Shifter (LS): Interfaces between 2.7 V CMOS level and VDD1 to VB level.
2
Preliminary Product Information S15797EJ1V4PM
Source driver
Common
µPD161644
1.1 Boost Voltage Construction
The boost voltage generated in µPD161644 is shown below.
VDD1 = VR x 3
= 15 V
VGD = VR
VDD1 = VDD2 x 3
= 16.2 V
VGD = VDD2
VDD2: 5.4 V
VDD2: 5.4 V
VR: 5 V
VR: 5 V
VDC: 2.7 V
VDC: 2.7 V
VSS1: 0 V
VSS1: 0 V
VSS4 = VDC x −1
= −2.7 V
VSS4 = VDC x −1
= −2.7 V
VSS2 = VR x −2
= −10 V
VSS3 = VR x −3
= −15 V
VSS2 = VDD2 x −2
= −10.8 V
VSS3 = VDD2 x −3
= −16.2 V
1.2 Boost Voltage Auto Start and Rising Order
VDD1 = 3 x VR
VGD = VR, VCD2 = H
VDD2 = 3 x VDC
VR
DCON
VSS1
VSS4 = −VDC
T1
T2
T3
T4
VSS2 = −2 x VR
VSS3 = −3 x VR
T1, T2, T3, T4: changeable by PUPT0, PUPT01, DUPF0, DUPF1
1.3 VS_AMP Circuit
VS_AMP circuits are shown below.
VDD2
TESTOUT1
VREF
+
MVS
C3
−
RbS
VREF
VS
MVS
5V
4V
C3
VDD2
TESTOUT1
RbS
C3
−
+
VS
5V
4V
C3
RaS
RcS
RaS
Internal Resistor Mode
EXRV = L
External Resistor Mode
EXRV = H
RbS
)VREF
VS = (1+
RaS
Preliminary Product Information S15797EJ1V4PM
3
µPD161644
1.4 Common Drive Circuit
The common drive circuit is shown below.
VS
CDA0
CDA1
CDA2
CDA3
CDA4
CDA5
CDA6
CDA7
VDD2
+
VS
D/A
+
LS
VCOM
VCC1
VS
4
C3
−
VCOMIN
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
COMH
−
+
COML
−
VS
D/A
C3
VSS4
+
−
Preliminary Product Information S15797EJ1V4PM
VCIN
µPD161644
1.5 Variable Boost Steps
The boost steps of VDD1, VSS2, VSS3 are selected according to how the external capacitor is connected.
The examples of connection are shown below. VS is selected as a boost reference voltage in these examples (short
between the VS and VGD pins).
VDD2 = VDC x 3
VDD2 = VDC x 2
(dual mode)
C1+
C1+
C1−
C1−
VDD2
VDD2 = VDC x 2
(single mode)
C1+
VDD2
C1−
C2+
C2+
C2+
C2−
C2−
C2−
VDD1 = VGD x 3
VSS2 = VGD x −2
VSS3 = VGD x −3
C3+
VDD1
VSS2
C5+
VSS4
VDD1 = VGD x 2
VSS2 = VGD x −1
VSS3 = VGD x −2
C3+
VDD1
C3−
VSS2
C4+
VSS3
C5+
VDD1 = VGD x 2
VSS2 = −
VSS3 = VGD x −1
C3+
VDD1
C3−
VSS2
C4−
C5−
VSS4 = VDC x −1
C6−
C4+
VSS3
C5−
C6 +
VDD1
C4−
C4−
C5+
C3+
C3−
C3−
C4+
VDD1 = VGD x 3
VSS2 = −
VSS3 = VGD x −2
VDD2
C4+
VSS2
C4−
VSS3
C5−
C5+
VSS3
C5−
VSS4 = −
C6+
VSS4
C6−
Preliminary Product Information S15797EJ1V4PM
5
µPD161644
2. PIN CONFIGURATION (Pad Layout)
Chip size: 2.8 x 9.4 mm
2
Bump size
Input/Left/Right (includes DUMMY of input side)
: 100 x 40 µm
Output (includes DUMMY output side)
: 86 x 35 µm
2
2
Figure 2-1. Chip Schematic
No.145
No.391
+
+
Bump side up
X
Y
(0,0)
+
No.1
No.144
A
B
Opening in protective film
C
Note
D
Note A part of the protective film on the chip surface is absent to enable a transistor check at shipment.
The position of this opening is indicated by the shaded section in the above chip schematic. The specific
coordinates of this opening are as follows.
X (µm)
Y (µm)
A
−847.74
−3143.37
B
−687.75
−3143.37
C
−687.75
−3438.78
D
−847.74
−3438.78
Alignment Mark Coordinate (mark center, unit: mm)
X
Y
Shape of Alignment Mark
−1.125
−4.5705
Type A
0.9705
4.5495
Type B
0.9705
−4.5495
Type B
Alignment Mark
Type A
Type B
10 µm 10 µm 10 µm
6
30 µm 30 µm 30 µm
10 µm
30 µm
10 µm
30 µm
10 µm
30 µm
Preliminary Product Information S15797EJ1V4PM
µPD161644
Table 2-1. Pad Layout (1/3)
PADTYPE : BUMP SIZE 100 µ m x 40 µ m
GATE INPUTS
PAD No.
PAD NAME
X [mm]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DUMMY
TESTOUT2
TESTIN2
TESTIN1
TESTOUT1
PVCC1
DUPF0
PUPT0
SCN2
SCN1
SCN0
ACS0
EXRV
VSEL
CLS0
FS2
FS0
VMS
RGONR
PVSS1
PVSS3
VMON
DUMMY
PVCC1
R,/L
IFSEL
PVSS1
VCOMIN
VCOM
VCOM
VCOM
COML
COML
COMH
COMH
VM
VM
VB
VB
VSS3
VSS3
VSS3
VSS4
VSS4
VSS4
VSS2
VSS2
VSS2
C6C6C6+
C6+
C5C5C5+
C5+
C4C4C4+
C4+
C3C3C3+
C3+
VDD1
VDD1
VDD1
C2C2C2C2C2+
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
Y [mm]
-4.5500
-4.4900
-4.4300
-4.3700
-4.3100
-4.2500
-4.1900
-4.1300
-4.0700
-4.0100
-3.9500
-3.8900
-3.8300
-3.7700
-3.7100
-3.6500
-3.5900
-3.5300
-3.4700
-3.4100
-3.3500
-3.2900
-3.2300
-3.1700
-3.1100
-3.0500
-2.9900
-2.9200
-2.8500
-2.7900
-2.7300
-2.6600
-2.6000
-2.5300
-2.4700
-2.4000
-2.3400
-2.2700
-2.2100
-2.1400
-2.0800
-2.0200
-1.9500
-1.8900
-1.8300
-1.7600
-1.7000
-1.6400
-1.5700
-1.5100
-1.4400
-1.3800
-1.3100
-1.2500
-1.1800
-1.1200
-1.0500
-0.9900
-0.9200
-0.8600
-0.7900
-0.7300
-0.6600
-0.6000
-0.5300
-0.4700
-0.4100
-0.3400
-0.2800
-0.2200
-0.1600
-0.0900
PADTYPE : BUMP SIZE 100 µ m x 40 µ m
GATE INPUTS
PAD No.
PAD NAME
X [mm]
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
C2+
C2+
C2+
C1C1C1C1C1+
C1+
C1+
C1+
VDD2
VDD2
VDD2
VDD2
VSS1
VSS1
VSS1
VSS1
DUMMY
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VCC1
VCC1
VCC1
VCC1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VR
VR
VR
VGD
VGD
VGD
MVS
VS
VS
VS
VS
VS
VS
DUMMY
PVCC1
VCD2
RGON
DCON
FRM
VCIN
PVSS1
/GRESET
GCS
GCL
GDA
STVR
STVL
DCCLK
CLK
OE1
OE2
DUMMY
VSS3
DUMMY
Preliminary Product Information S15797EJ1V4PM
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
-1.242
Y [mm]
-0.0300
0.0300
0.0900
0.1600
0.2200
0.2800
0.3400
0.4100
0.4700
0.5300
0.5900
0.6600
0.7200
0.7800
0.8400
0.9100
0.9700
1.0300
1.0900
1.1600
1.2300
1.2900
1.3500
1.4100
1.4700
1.5300
1.5900
1.6500
1.7200
1.7800
1.8400
1.9000
1.9700
2.0300
2.0900
2.1500
2.2100
2.2700
2.3400
2.4000
2.4600
2.5300
2.5900
2.6500
2.7200
2.7900
2.8500
2.9100
2.9700
3.0300
3.0900
3.1600
3.2300
3.3000
3.3700
3.4400
3.5100
3.5800
3.6500
3.7200
3.7900
3.8600
3.9300
4.0000
4.0700
4.1400
4.2100
4.2800
4.3500
4.4200
4.4900
4.5600
7
µPD161644
Table 2-1. Pad Layout (2/3)
PADTYPE : BUMP SIZE 86 µ m x 35 µ m
GATE OUTPUTS 35 µ m pitch
PAD No.
PAD NAME
X [mm]
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
8
DUMMY
DUMMY
DUMMY
O241
O240
O239
O238
O237
O236
O235
O234
O233
O232
O231
O230
O229
O228
O227
O226
O225
O224
O223
O222
O221
O220
O219
O218
O217
O216
O215
O214
O213
O212
O211
O210
O209
O208
O207
O206
O205
O204
O203
O202
O201
O200
O199
O198
O197
O196
O195
O194
O193
O192
O191
O190
O189
O182
O187
O186
O185
O184
O183
O182
O181
O180
O179
O178
O177
O176
O175
O174
O173
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
Y [mm]
4.3050
4.2700
4.2350
4.2000
4.1650
4.1300
4.0950
4.0600
4.0250
3.9900
3.9550
3.9200
3.8850
3.8500
3.8150
3.7800
3.7450
3.7100
3.6750
3.6400
3.6050
3.5700
3.5350
3.5000
3.4650
3.4300
3.3950
3.3600
3.3250
3.2900
3.2550
3.2200
3.1850
3.1500
3.1150
3.0800
3.0450
3.0100
2.9750
2.9400
2.9050
2.8700
2.8350
2.8000
2.7650
2.7300
2.6950
2.6600
2.6250
2.5900
2.5550
2.5200
2.4850
2.4500
2.4150
2.3800
2.3450
2.3100
2.2750
2.2400
2.2050
2.1700
2.1350
2.1000
2.0650
2.0300
1.9950
1.9600
1.9250
1.8900
1.8550
1.8200
PADTYPE : BUMP SIZE 86 µ m x 35 µ m
GATE OUTPUTS 35 µ m pitch
PAD No.
PAD NAME
X [mm]
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
O172
O171
O170
O169
O168
O167
O166
O165
O164
O163
O162
O161
O160
O159
O158
O157
O156
O155
O154
O153
O152
O151
O150
O149
O148
O147
O146
O145
O144
O143
O142
O141
O140
O139
O138
O137
O136
O135
O134
O133
O132
O131
O130
O129
O128
O127
O126
O125
O124
O123
O122
O121
O120
O119
O118
O117
O116
O115
O114
O113
O112
O111
O110
O109
O108
O107
O106
O105
O104
O103
O102
O101
Preliminary Product Information S15797EJ1V4PM
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
Y [mm]
1.7850
1.7500
1.7150
1.6800
1.6450
1.6100
1.5750
1.5400
1.5050
1.4700
1.4350
1.4000
1.3650
1.3300
1.2950
1.2600
1.2250
1.1900
1.1550
1.1200
1.0850
1.0500
1.0150
0.9800
0.9450
0.9100
0.8750
0.8400
0.8050
0.7700
0.7350
0.7000
0.6650
0.6300
0.5950
0.5600
0.5250
0.4900
0.4550
0.4200
0.3850
0.3500
0.3150
0.2800
0.2450
0.2100
0.1750
0.1400
0.1050
0.0700
0.0350
0.0000
-0.0350
-0.0700
-0.1050
-0.1400
-0.1750
-0.2100
-0.2450
-0.2800
-0.3150
-0.3500
-0.3850
-0.4200
-0.4550
-0.4900
-0.5250
-0.5600
-0.5950
-0.6300
-0.6650
-0.7000
µPD161644
Table 2-1. Pad Layout (3/3)
PADTYPE : BUMP SIZE 86 µ m x 35 µ m
GATE OUTPUTS 35 µ m pitch
PAD No.
PAD NAME
X [mm]
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
O100
O99
O98
O97
O96
O95
O94
O93
O92
O91
O90
O89
O88
O87
O86
O85
O84
O83
O82
O81
O80
O79
O78
O77
O76
O75
O74
O73
O72
O71
O70
O69
O68
O67
O66
O65
O64
O63
O62
O61
O60
O59
O58
O57
O56
O55
O54
O53
O52
O51
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
O29
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
Y [mm]
-0.7350
-0.7700
-0.8050
-0.8400
-0.8750
-0.9100
-0.9450
-0.9800
-1.0150
-1.0500
-1.0850
-1.1200
-1.1550
-1.1900
-1.2250
-1.2600
-1.2950
-1.3300
-1.3650
-1.4000
-1.4350
-1.4700
-1.5050
-1.5400
-1.5750
-1.6100
-1.6450
-1.6800
-1.7150
-1.7500
-1.7850
-1.8200
-1.8550
-1.8900
-1.9250
-1.9600
-1.9950
-2.0300
-2.0650
-2.1000
-2.1350
-2.1700
-2.2050
-2.2400
-2.2750
-2.3100
-2.3450
-2.3800
-2.4150
-2.4500
-2.4850
-2.5200
-2.5550
-2.5900
-2.6250
-2.6600
-2.6950
-2.7300
-2.7650
-2.8000
-2.8350
-2.8700
-2.9050
-2.9400
-2.9750
-3.0100
-3.0450
-3.0800
-3.1150
-3.1500
-3.1850
-3.2200
PADTYPE : BUMP SIZE 86 µ m x 35 µ m
GATE OUTPUTS 35 µ m pitch
PAD No.
PAD NAME
X [mm]
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
DUMMY
DUMMY
DUMMY
Preliminary Product Information S15797EJ1V4PM
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
1.127
1.249
Y [mm]
-3.2550
-3.2900
-3.3250
-3.3600
-3.3950
-3.4300
-3.4650
-3.5000
-3.5350
-3.5700
-3.6050
-3.6400
-3.6750
-3.7100
-3.7450
-3.7800
-3.8150
-3.8500
-3.8850
-3.9200
-3.9550
-3.9900
-4.0250
-4.0600
-4.0950
-4.1300
-4.1650
-4.2000
-4.2350
-4.2700
-4.3050
9
µPD161644
3. PIN FUNCTIONS
(1/5)
Symbol
Pin Name
VDC
DC/DC converter
VCC1
Logic reference
Pad No.
I/O
Function
93 to 100
−
Reference voltage input pin for DC/DC converter.
101 to 104
−
2.5 to 3.3 V LS (level shifter) reference voltage input pin.
88 to 91,
−
Connect to the system ground.
reference voltage
voltage
VSS1
Ground
105 to 110
VGD
Power supply input
114 to 116
Input
VDD1
DC/DC converter
Reference voltage input pin for VDD1, VSS1 to VSS4 boost.
Connect to any of VDD2, VR or VS.
for DC/DC converter
65 to 67
Output
Boost output voltage of DC/DC converter (VGD x 2 or x 3).
The boost step number of VDD1 is selected according to how the
output
external capacitor is connected. The boost reference voltage can
be set using VGD. Refer to the function of VGD pin.
VDD2
DC/DC converter
84 to 87
Output
Boost output voltage of DC/DC converter (VDC x 2 or x 3). The
46 to 48
Output
Boost output voltage of DC/DC converter (VGD x −1 or x −2).
boost step number of VDD2 can be set using VCD2.
output
VSS2
DC/DC converter
The boost step number of VSS2 is selected according to how the
output
external capacitor is connected. The boost reference voltage can
be set using VGD. Refer to the function of VGD pin.
VSS3
DC/DC converter
40 to 42, 143
Output
Boost output voltage of DC/DC converter (VGD x −2 or x −3).
The boost step number of VSS3 is selected according to how the
output
external capacitor is connected. The boost reference voltage can
be set using VGD. Refer to VGD pin function.
VSS4
DC/DC converter
43 to 45
Output
Boost output voltage of DC/DC converter (VDC x −1).
36, 37
Output
The voltage level of VSS2 or VSS3 is output synchronized with the
output
VM
Gate output low
level select voltage
VCIN input.
VCIN = 0: Output the voltage level of VSS3
VCIN = 1: Output the voltage level of VSS2
The timing chart is shown in Figure 3-1.
VB
Driver negative
38, 39
Input
voltage
Negative voltage of output buffer. This is the input pin of the
liquid crystal driver negative voltage. Input the negative power
supply of the gate output. VB pin connection examples are
shown in Figure 3-2.
+
C1 , C1
−
C2 , C2 −
+
+
C3 , C3
Capacitor connect
80 to 83, 76 to 79,
pin for boost
72 to 75, 68 to 71,
For the recommended values of the capacitance and
63, 64, 61, 62,
withstanding voltage of each capacitor, refer to
59, 60, 57, 58,
9. RECOMMENDED CAPACITANCE VALUES OF EXTERNAL
55, 56, 53, 54,
CAPACITOR.
−
C4 , C4 −
+
+
C5 , C5
−
C6 , C6 −
+
VR
10
Output
To connect booster for DC/DC converter.
51, 52, 49, 50
Power supply
111 to 113
Output
Positive power supply voltage output for the DC/DC converter.
output for DC/DC
The VR output voltage can be changed by setting VRSEL0 to
converter
VRSEL2.
Preliminary Product Information S15797EJ1V4PM
µPD161644
(2/5)
Symbol
VS
Pin Name
Positive power
Pad No.
118 to 123
I/O
Output
Function
Positive power supply voltage output for source driver. The VS
output voltage can be changed by setting VSEL0 to VSEL2.
output supply for
driver
MVS
External resistor
117
Input
input
Any output voltage can be set by connecting an external resistor.
<EXRV = 0> Leave open.
<EXRV = 1> Connect to external resistor.
6, 24, 125
−
Pull-up voltage for mode setting pin.
Pull-down voltage
20, 27, 131
−
Pull-down voltage for mode setting pin.
Pull-down voltage
21
−
Pull-down voltage for mode setting pin.
Shift clock input
139
Input
PVCC1
Pull-up voltage
PVSS1
PVSS3
CLK
Shift clock input pin of the internal shift resistor. The contents of
internal shift resistor are shifted at the rising edge of CLK.
Connect to GCLK pin of source driver.
STVR,
Start pulse
136,
STVL
input/output pin
137
I/O
Input/output pin of the internal shift resistor.
Start pulse signal is read at the rising edge of shift clock CLK and a
scan signal is output from the driver output pin.
The valid level of the STVR/STVL pin is determined by the setting
of STVSEL.
When STVSEL = L, the pulse becomes low level at the falling
edge of the 240th shift clock CLK and high level at falling edge of
the 241st clock.
OE1
Enable input
140
Input
If the level selected by OE1SEL is input, the driver output is fixed to
low level (When OE1SEL = L the driver output is fixed to low level if
a low level is input). However, the shift resistor is not cleared. And,
output enable actuation is asynchronous in the clock.
Connect to GOE1 pin of source driver.
OE2
Enable input
141
Input
If the level selected by OE2SEL is input, the driver output is fixed to
high level (When OE2SEL = L the driver output is fixed to low level
if a high level is input). However, the shift resistor is not cleared.
And, output enable actuation is asynchronous in the clock.
Connect to GOE2 pin of source driver.
R,/L
Shift direction
25
Input
control
The shift direction control pin of shift register. The shift directions
of the shift registers are as follows.
R,/L = H (right shift): STVR input, O1 →O241, STVL output
R,/L = L (left shift) : STVL input, O241 → O1, STVR output
FRM
Frame signal input
129
Input
Input frame reverse signals.
Connect to GFRAME pin of source driver.
DCCLK
Clock input for
DC/DC converter
138
Input
To input the external clock for the DC/DC converter.
This pin is valid only when CLS0 = 1 and CLS1 = 1. In other
settings, leave open.
Preliminary Product Information S15797EJ1V4PM
11
µPD161644
(3/5)
Symbol
O1 to O241
Pin Name
Driver output pins
Pad No.
388 to 148
I/O
Output
Function
Scan signal output pins that drive the gate electrode of a TFTLCD. The status of each output pin changes in synchronization
with the rising edge of shift clock CLK. The output voltage of the
driver is VDD1 to VB.
COMH
Common high level
34, 35
Output
<COMON = 1> High level of common voltage is output. The voltage
level changes accordance with DA0 to DA7 and CDA0 to CDA7.
output
<COMON = 0> Leave open when not using it.
COML
Common low level
32, 33
Output
<COMON = 1> Low level of common voltage is output. The voltage
level changes accordance with DA0 to DA7 and CDA0 to CDA7.
output
<COMON = 0> Leave open when not using it.
VCOM
Common output
29 to 31
Output
<COMON = 1> The common voltage synchronized with the VCIN
input is output. Connect to common pin of panel.
<COMON = 0> Leave open when not using it.
VCOMIN
VCOM center
28
Input
voltage input
VCOM center voltage input pin. Leave open when COMSEL = 0.
<COMSEL = 0> Internal D/A is valid.
<COMSEL = 1> VCOMIN input voltage is valid.
VCIN
Common pulse
130
Input
input
/GRESET
Reset input
To input common pulse. Connect to VCOUT3 pin of source driver.
Fix this pin to low when not using it.
132
Input
Reset input pin. Connect to /GRESET pin of source driver.
If /GRESET is made low, the serial interface is initialized (the
register values are not initialized). A reset operation is executed
according to the level of the /GRESET signal. Be sure to execute
a reset using this pin at power application.
IFSEL
Interface selection
26
Input
The serial interface input switching pin.
<IFSEL = 0> Serial interface input.
The DCON, RGONR, VCD2, VMS, FS0, FS2, CLS0, RGON, VSEL,
EXRV, ACS0, SCN0 to SCN2, PUPT0, DUPF0 pins should be left
open.
<IFSEL = 1> Control pin input.
The GCS, GCL, GDA pins should be left open.
GCS
Chip select input
133
Input
<IFSEL = 0> To input chip select signals.
Connect to GCS pin of source driver.
<IFSEL = 1> Leave open.
GCL
Serial clock input
134
Input
<IFSEL = 0> To input serial clock signals.
Connect to GCL pin of source driver.
<IFSEL = 1> Leave open.
GDA
Serial data input
135
Input
<IFSEL = 0> To input serial data signals.
Connect to GDA pin of source driver.
<IFSEL = 1> Leave open.
12
Preliminary Product Information S15797EJ1V4PM
µPD161644
(4/5)
Symbol
DCON
Pin Name
DC/DC converter
Pad No.
128
I/O
Input
control
Function
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> The DC/DC converter ON/OFF control signal is input.
Connect to the DCON pin of the source driver.
<DCON = 0> DC/DC converter OFF
<DCON = 1> DC/DC converter ON
RGONR
VR regulator control
19
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> The VR regulator ON/OFF control signal is input.
<RGONR = 0> VR regulator OFF
<RGONR = 1> VR regulator ON
VCD2
VDD2 boost
126
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> The VDD2 boost step number select pin.
selection
<VCD2 = 0> VDD2 = VDC x 2
<VCD2 = 1> VDD2 = VDC x 3
VMS
VDD2 boost
18
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> VDD2 boost mode select pin.
selection
<VMS = 0> VDD2: single boost mode
<VMS = 1> VDD2: dual boost mode
FS0
FS2
CLS0
VDD2, VSS4 boost
17
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
frequency selection
<IFSEL = 1> VDD2, VSS4 boost frequency select pin in scan mode.
in scan mode
<FS0 = 0 > fOSC/2 <FS0 = 1 > fOSC/4
VDD1, VSS2, VSS3
16
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
boost frequency
<IFSEL = 1> VDD1, VSS2, VSS3 boost frequency select pin in scan
selection in scan
mode.
mode
<FS2 = 0 > fOSC/2 <FS2 = 1, > fOSC/4
DC/DC OSC
15
Input
frequency selection
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> Select pin of the OSC oscillation frequency for DC/DC
converter.
<CLS0 = 0> fOSC = 25 kHz, DCCLK: Open
<CLS0 = 1> External CK input mode
RGON
VS regulator control
127
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> The VS regulator ON/OFF control signal is input.
Connect this pin to the RGON pin of the source driver.
<RGON = 0> VS regulator OFF
<RGON = 1> VS regulator ON
VSEL
VS regulator voltage
14
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> Select pin of output voltage for VS regulator.
selection
<VSEL = 1> VS = 4 V
<VSEL = 0> VS = 5 V
EXRV
VS regulating resistor 13
selection
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> Select pin of external resistor for VS regulator.
<EXRV = 0> Internal resistor setting mode.
<EXRV = 1> Any output voltage can be set by connecting MVS to
an external resistor.
Preliminary Product Information S15797EJ1V4PM
13
µPD161644
(5/5)
Symbol
ACS0
Pin Name
Amp. current
Pad No.
12
I/O
Input
Function
<IFSEL = 0> Leave open (Internal resistors are valid).
selection in scan
<IFSEL = 1> Amp. current select pin in scan mode.
mode
<ACS0 = 0> Amp. current = 5 µA
<ACS0 = 1> Amp. current = 15 µA
SCN0,
Gate scan selection
11,
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
SCN1,
10,
<IFSEL = 1> Select pin of gate scan order.
SCN2
9
<SCN0 = 1, SCN1 = 1, SCN2 = 1> MODE1
<SCN0 = 1, SCN1 = 1, SCN2 = 0> MODE2
<SCN0 = 1, SCN1 = 0, SCN2 = 1> MODE3
<SCN0 = 1, SCN1 = 0, SCN2 = 0> MODE4
<SCN0 = 0, SCN1, SCN2 = x> MODE5
PUPT0
Setting pin of
8
Input
VSS4 at DC/DC converter power on time.
power on time
DUPF0
Operating frequency
<IFSEL = 0> Leave open (Internal resistors are valid).
<IFSEL = 1> This pin sets the rising time of VDD1, VDD2, VSS2 to
DC/DC converter
7
Input
<IFSEL = 0> Leave open (Internal resistors are valid).
setting pin at
<IFSEL = 1> This pin sets the operating frequency at DC/DC
DC/DC converter
converter power on time.
power on
<DUPT0 = 0> fOSC/8
<DUPT0 = 1> fOSC/16
VMON
Stand-by current
22
Input
The standby current reduction control pin.
reduction control
<VMON = PVSS3> Normal mode.
pin
A quiescent current of about 0.5 µA is consumed in standby mode.
When the VCC1 voltage drops, the driver output pins are fixed to
ALL-High.
<VMON = PVCC1> Standby current reduction mode.
Makes the quiescent current consumed in standby mode 0.
When the VCC1 voltage drops, the driver output pins are undefined.
TESTOUT1
VREF reference
TESTIN1,
TEST input pin
5
Output
The VREF voltage measurement pin. Leave open.
4,
Input
Test input pins. Leave open.
Output
Test output pin. Leave open.
voltage output
TESTIN2
3
TESTOUT2
TEST output pin
DUMMY
Dummy
2
1, 23, 92, 124,
−
Dummy data
142, 144 to 147,
389 to 391
14
Preliminary Product Information S15797EJ1V4PM
µPD161644
Figure 3-1. VM signal Timing Chart
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
DC/DC converter ON
GOE1ON(R59) = "1"
CLK = "H": Hi-Z
CLK = "H" + OE1 = "L" : Hi-Z
Output Hi-Z term
Remark Hi-Z (High impedance)
Figure 3-2. Examples of VB pin connection
(a) When the negative voltage level of the gate output
is set to VSS3
µPD161644
(b) When the negative voltage level of the gate output
is switched between VSS2 and VSS3
µPD161644
VGD
VGD
VS or VR
VS or VR
VDD1
VDD1
DC/DC converter
DC/DC converter
VSS3
VSS2
open
VSS2
VCIN
VCIN
VM
VM
open
VSS3
O1
O2
O2
Level shifter
Level shifter
O1
to Panel gate line
common
driving signal
VB
VDD1
VB
VDD1
VCOUT3
from µPD161621
VSS2
VSS2
VSS3
VSS3
to Panel gate line
O241
O241
Preliminary Product Information S15797EJ1V4PM
15
µPD161644
4. COMMAND
4.1 Command List
Data bit
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0 R24 DC/DC operation setting
Rn
Register
D7
D6
D5
D4
D3
0
0
0
1
1
0
0
1 R25 DC/DC step setting
0
0
0
1
1
0
1
0 R26 DC/DC oscillation setting
FUP
CLS1
CLS0
FS3
0
0
0
1
1
0
1
1 R27 Regulator output setting
ACS1
ACS0
EXRV
VSEL2
0
0
0
1
1
1
0
0 R28 LPM setting
LACS1 LACS0
LFS3
LFS2
0
0
0
1
1
1
0
1 R29 Gate scan setting
0
0
0
1
1
1
1
0 R30 Gate mode setting
0
0
0
1
1
1
1
1 R31 Common amplitude setting
0
0
1
0
0
0
0
0 R32 Common center setting
0
0
1
0
0
0
0
1 R33 DC/DC power on setting
0
0
1
0
0
0
1
0 R34 Reset
D2
D1
D0
RGONR VS4ON VS3ON VS2ON VD2ON VD1ON DCON
VRSEL2VRSEL1 VRSEL0
FS2
VMS
FS1
VSEL1 VSEL0
OE2SEL OE1SELSTVSEL
VCD2
FS0
RGON
LFS1
LFS0
LPM
SCN2
SCN1
SCN0
COMHI COMSEL COMON NLINE2 NLINE1
DA7
DA6
CDA7
CDA6
DA5
DA4
CDA5
CDA4
PONM
PON
DA3
DA2
DA1
DA0
CDA3
CDA2
CDA1
CDA0
DUPF1 DUPF0 PUPT1 PUPT0
RES
4.2 Command Description
Reset the internal data at power application by inputting a low level to the /GRESET pin.
(1/5)
Resistor
Bit
Symbol
Reset
R24
D0
DCON
0
Function
DC/DC converter control
Description
Control ON/OFF of DC/DC converter.
<DCON = 0> DC/DC converter OFF
<DCON = 1> DC/DC converter ON
D1
VD1ON
0
VDD1 boost control
Control ON/OFF of VDD1 boost.
<VD1ON = 0> VDD1 boost OFF
<VD1ON = 1> VDD1 boost ON
D2
VD2ON
0
VDD2 boost control
Control VDD2 boost ON/OFF.
<VD2ON = 0> VDD2 boost OFF
<VD2ON = 1> VDD2 boost ON
D3
VS2ON
0
VSS2 boost control
Control VSS2 boost ON/OFF.
<VS2ON = 0> VSS2 boost OFF
<VS2ON = 1> VSS2 boost ON
D4
VS3ON
0
VSS3 boost control
Control VSS3 boost ON/OFF.
<VS3ON = 0> VSS3 boost OFF
<VS3ON = 1> VSS3 boost ON
D5
VS4ON
0
VSS4 boost control
Control VSS4 boost ON/OFF.
<VS4ON = 0> VSS4 boost OFF
<VS4ON = 1> VSS4 boost ON
D6
RGONR
0
VR regulator control
Control ON/OFF of VR regulator.
<RGONR = 0> VR regulator OFF
<RGONR = 1> VR regulator ON
16
Preliminary Product Information S15797EJ1V4PM
µPD161644
(2/5)
Resistor
Bit
Symbol
Reset
R25
D0
VCD2
0
Function
VDD2 boost selection
Description
Select the number of VDD2 boost step (x2/x3).
<VCD2 = 0> VDD2 = VDC x 2
<VCD2 = 1> VDD2 = VDC x 3
D1
VMS
1
VDD2 boost mode
Select VDD2 boost mode.
selection
<VMS = 0> VDD2 = Single boost mode
<VMS = 1> VDD2 = Dual boost mode
D2
VRSEL0
1
VR regulator output
Select output voltage of VR regulator. When IFSEL = 1, VR
voltage selection
is fixed to 5 V.
<VRSEL0 = 0, VRSEL1 = 0, VRSEL2 = 0> VR = 3 V
D3
VRSEL1
<VRSEL0 = 1, VRSEL1 = 0, VRSEL2 = 0> VR = 3.5 V
0
<VRSEL0 = 0, VRSEL1 = 1, VRSEL2 = 0> VR = 4 V
<VRSEL0 = 1, VRSEL1 = 1, VRSEL2 = 0> VR = 4.5 V
<VRSEL0 = 0, VRSEL1 = 0, VRSEL2 = 1> VR = 4.75 V
D4
VRSEL2
1
<VRSEL0 = 1, VRSEL1 = 0, VRSEL2 = 1> VR = 5 V
<VRSEL0 = 0, VRSEL1 = 1, VRSEL2 = 1> VR = 5.25 V
<VRSEL0 = 1, VRSEL1 = 1, VRSEL2 = 1> VR = 5.5 V
R26
D0
FS0
1
VDD2, VSS4 boost
Select VDD2, VSS4 boost frequency in scan mode. When
frequency selection in
IFSEL = 1, FS1 is fixed to 0.
<FS0 = 0, FS1 = 0> fOSC/2 <FS0 = 1, FS1 = 0> fOSC/4
D1
FS1
0
scan mode
D2
FS2
1
VDD1, VSS2, VSS3
<FS0 = 0, FS1 = 1> fOSC/8 <FS0 = 1, FS1 = 1> fOSC/16
boost frequency
Select VDD1, VSS2, VSS3 boost frequency in scan mode.
When IFSEL = 1, FS3 is fixed to 0.
D3
FS3
0
selection in scan mode
D4
CLS0
1
DC/DC OSC frequency
Select oscillation frequency of OSC for DC/DC converter.
selection
When IFSEL = 1, CLS1 is fixed to 1.
<FS2 = 0, FS3 = 0> fOSC/2 <FS2 = 1, FS3 = 0> fOSC/4
<FS2 = 0, FS3 = 1> fOSC/8 <FS2 = 1, FS3 = 1> fOSC/16
<CLS0 = 0, CLS1 = 0> fOSC = 18 kHz, DCCLK: Open
D5
CLS1
<CLS0 = 1, CLS1 = 0> fOSC = 25 kHz, DCCLK: Open
0
<CLS0 = 0, CLS1 = 1> fOSC = 37 kHz, DCCLK: Open
<CLS0 = 1, CLS1 = 1> External CK input mode
D6
FUP
0
Switching of DC/DC
OSC frequency
Select oscillation frequency of OSC for DC/DC converter.
When IFSEL = 1, the frequency is fixed to fOSC.
<FUP = 0> fOSC
<FUP = 1> fOSC x 2
Preliminary Product Information S15797EJ1V4PM
17
µPD161644
(3/5)
Resistor
Bit
Symbol
Reset
R27
D0
RGON
0
Function
VS regulator control
Description
Control ON/OFF of VS regulator.
<RGON = 0> VS regulator OFF
<RGON = 1> VS regulator ON
D1
VSEL0
1
VS regulator output
Select the output voltage of VS regulator.
voltage selection
VSEL0 = 0: VS = 5 V, VSEL = 1: VS = 4 V when IFSEL = 1.
<VSEL0 = 0, VSEL1 = 0, VSEL2 = 0> VS = 3 V
D2
VSEL1
<VSEL0 = 1, VSEL1 = 0, VSEL2 = 0> VS = 3.5 V
0
<VSEL0 = 0, VSEL1 = 1, VSEL2 = 0> VS = 4 V
<VSEL0 = 1, VSEL1 = 1, VSEL2 = 0> VS = 4.5 V
<VSEL0 = 0, VSEL1 = 0, VSEL2 = 1> VS = 4.75 V
D3
VSEL2
1
<VSEL0 = 1, VSEL1 = 0, VSEL2 = 1> VS = 5 V
<VSEL0 = 0, VSEL1 = 1, VSEL2 = 1> VS = 5.25 V
<VSEL0 = 1, VSEL1 = 1, VSEL2 = 1> VS = 5.5 V
D4
EXRV
0
VS regulator resistor
Select external resistor of VS regulator.
selection
<EXRV = 0> Internal resistor mode
<EXRV = 1> Connect external resistor to MVS and set any
level of voltage
D5
ACS0
0
Amp. current selection
Select Amp. current of VR and VS regulators in scan mode.
in scan mode
When IFSEL = 1, ACS1 is fixed to 0.
<ACS0 = 0, ACS1 = 0> Amp. current = 5 µA
D6
ACS1
<ACS0 = 0, ACS1 = 1> Amp. current = 10 µA
0
<ACS0 = 1, ACS1 = 0> Amp. current = 15 µA
<ACS0 = 1, ACS1 = 1> Amp. current = 30 µA
R28
D0
LPM
0
Low power mode
Control in low power mode. When IFSEL = 1, LPM is fixed
control
to 0.
<LPM = 0> Scan mode
<LPM = 1> Low power mode
D1
D2
LFS0
LFS1
0
0
VDD2, VSS4 boost
Select boost frequency of VDD2, VSS4 in low power mode.
frequency selection in
<LFS0 = 0, LFS1 = 0> fOSC/8
low power mode
<LFS0 = 1, LFS1 = 0> fOSC/16
<LFS0 = 0, LFS1 = 1> fOSC/32
<LFS0 = 1, LFS1 = 1> fOSC/64
D3
D4
LFS2
LFS3
0
0
VDD1, VSS2, VSS3
Select boost frequency of VDD1, VSS2, VSS3 in low power
boost frequency
mode.
selection in low power
<LFS2 = 0, LFS3 = 0> fOSC/8
mode
<LFS2 = 1, LFS3 = 0> fOSC/16
<LFS2 = 0, LFS3 = 1> fOSC/32
<LFS2 = 1, LFS3 = 1> fOSC/64
D5
D6
LACS0
LACS1
0
0
Amp. current selection
Select Amp. current in low power mode.
in low power mode
<LACS0 = 0, LACS1 = 0> Amp. current = 1.25 µA
<LACS0 = 0, LACS1 = 1> Amp. current = 2.5 µA
<LACS0 = 1, LACS1 = 0> Amp. current = 5 µA
<LACS0 = 1, LACS1 = 1> Amp. current = 7.5 µA
18
Preliminary Product Information S15797EJ1V4PM
µPD161644
(4/5)
Resistor
Bit
Symbol
Reset
R29
D0
SCN0
1
Function
Gate scan selection
Description
Select scan order of gate scan.
<SCN0 = 1, SCN1 = 1, SCN2 = 1> MODE1
D1
SCN1
1
D2
SCN2
1
<SCN0 = 1, SCN1 = 1, SCN2 = 0> MODE2
<SCN0 = 1, SCN1 = 0, SCN2 = 1> MODE3
<SCN0 = 1, SCN1 = 0, SCN2 = 0> MODE4
<SCN0 = 0, SCN1, SCN2 = X> MODE5
D3
STVSEL
0
Start pulse input/output
Select start pulse input/output valid level to STVR/STVL.
valid level selection
But there is no pin to select start pulse input/output valid
level. When IFSEL = H (When using control pins), low-fixed
is valid. Refer to 4.3 Command Setting Values When
IFSEL = H (When Using Control Pins).
<STVSEL= 0> Low level is valid.
<STVSEL= 1> High level is valid.
D4
OE1SEL
0
OE1 valid level selection
Select valid level of OE1. But there is no pin to select valid
level of OE1. When IFSEL = H (When using control pins),
low-fixed is valid. Refer to 4.3 Command Setting Values
When IFSEL = H (When Using Control Pins).
<OE1SEL = 0> OE1 = Low, gate output OFF
<OE1SEL = 1> OE1 = High, gate output OFF
D5
OE2SEL
0
OE2 valid level selection
Select valid level of OE2. There is no pin to select valid
level of OE2. When IFSEL = H (When using control pins),
low-fixed is valid. Refer to 4.3 Command Setting Values
When IFSEL = H (When Using Control Pins).
<OE2SEL = 0> OE2 = Low, gate output ON
<OE2SEL = 1> OE2 = High, gate output ON
R30
D0
NLINE1
1
Gate mode selection
Select 1-line skip, 2-line skip or N frame inversion of a gate
scan. When IFSEL = 1, this is fixed to normal mode.
<NLINE1 = 1, NLINE2 = 1> Normal mode
D1
NLINE2
<NLINE1 = 1, NLINE2 = 0> 1-line skip mode
1
<NLINE1 = 0, NLINE2 = 1> 2-line skip mode
<NLINE1 = 0, NLINE2 = 0> N frame inversion
D2
COMON
0
COM output control
Control ON/OFF of COM output. When IFSEL = 1, COMON
is fixed to 0.
<COMON = 0> COM_AMP, COM output OFF
<COMON = 1> COM_AMP, COM output ON
D3
COMSEL
0
VCOM center input
Select VCOM center voltage input.
selection
<COMSEL = 0> Internal D/A is valid.
VCOM output selection
Select VCOM output.
<COMSEL = 1> VCOMIN input voltage is valid.
D4
COMHI
0
<COMHI = 0> VCOM = Hi-Z
<COMHI = 1> VCOM = Output
Preliminary Product Information S15797EJ1V4PM
19
µPD161644
(5/5)
Resistor
Bit
Symbol
Reset
R31
D0 to D7
DA0 to DA7
0
COM amplitude control
Control COM output amplitude using 8-bit D/A.
R32
D0 to D7 CDA0 to CDA7
0
COM center level control
Control COM output center level using 8-bit D/A.
0
Setting of DC/DC
This pin sets the ON time of VDD1 and VDD2, VSS2 to VSS4,
converter power on time
and RGON when the DC/DC converter is started up. This
R33
D0
PUPT0
D1
PUPT1
1
D2
DUPF0
1
Function
Description
setting is valid only when PONM = 1. When IFSEL = 1,
PUPT1 is fixed to 0.
D3
DUPF1
Setting of DC/DC
This pin sets the DC/DC operating frequency when the
converter power on
DC/DC converter is started up. When IFSEL = 1, DUPF1 is
operating frequency
fixed to 0.
<DUPF0 = 0, DUPF1 = 0> fOSC/8
0
<DUPF0 = 1, DUPF1 = 0> fOSC/16
<DUPF0 = 0, DUPF1 = 1> fOSC/2
<DUPF0 = 1, DUPF1 = 1> fOSC/4
D4
PON
0
Switching DC/DC
This pin selects the VDD1, VDD2, VSS2 to VSS4 rising
converter startup
operating frequency when the DC/DC converter is started
operating frequency
up. This setting is valid only when PONM = 1.
<PON = 0> Normal operation
<PON = 1> Power on operation startup operation
D5
PONM
1
DC/DC operation startup
Select internal/external sequence of DC/DC converter
operating selection
power on operation.
<PONM = 0> External sequence
<PONM = 1> Internal sequence
R34
D0
RES
−
Command reset
This is the command reset function. A command reset
must always be executed after power application. All
contents of registers are initialized.
This bit is automatically cleared after command reset
execution (RES = 1). It is therefore not necessary to set
this bit to 0 again by software (to select normal operation).
Also, because this bit changes from 1 to 0 very quickly
following a command reset, it is not necessary to leave any
time before setting the next command after setting a
command reset.
<RES = 0> Normal operation
<RES = 1> Command reset
20
Preliminary Product Information S15797EJ1V4PM
µPD161644
4.3 Command Setting Values When IFSEL = H (When Using Control Pins)
(1/2)
Register
Bit
Symbol
Setting value
R24
D0
DCON
−
DCON control pin is valid.
D1
VD1ON
1
<VD1ON = 1> VDD1 boost ON
D2
VD2ON
1
<VD2ON = 1> VDD2 boost ON
D3
VS2ON
1
<VS2ON = 1> VSS2 boost ON
D4
VS3ON
1
<VS3ON = 1> VSS3 boost ON
R25
R26
R27
R28
R29
Conditions
D5
VS4ON
0
<VS4ON = 0> VSS4 boost OFF
D6
RGONR
−
RGONR control pin is valid.
D0
VCD2
−
VCD2 control pin is valid.
D1
VMS
−
VMS control pin is valid.
D2
VRSEL0
1
<VRSEL0 = 1, VRSEL1 = 0, VRSEL2 = 1 > VR = 5 V
D3
VRSEL1
0
D4
VRSEL2
1
D0
FS0
−
FS0 control pin is valid.
D1
FS1
0
<FS0 = 0> fOSC/2, <FS0 = 1> fOSC/4
D2
FS2
−
FS2 control pin is valid.
D3
FS3
0
<FS2 = 0> fOSC/2, <FS2 = 1> fOSC/4
D4
CLS0
−
CLS1 control pin is valid.
D5
CLS1
1
<CLS0 = 0> fOSC = 37 kHz, <CLS0 = 1> External
D6
FUP
0
<FUP = 0> fOSC
D0
RGON
−
RGON control pin is valid.
D1
VSEL0
−
VSEL control pin is valid.
D2
VSEL1
−
<VSEL = 0> VS = 5 V
D3
VSEL2
−
<VSEL = 1> VS = 4 V
D4
EXRV
−
EXRV control pin is valid.
D5
ACS0
−
ACS0 control pin is valid.
D6
ACS1
0
<ACS0 = 0> Current = 5 µA, <ACS0 = 1> Current = 15 µA
D0
LPM
0
<LPM = 0> Scan mode
D1, D2
LFS0, LFS1
0,1
<LFS0 = 0, LFS1 = 1> fOSC/32
D3, D4
LFS2, LFS3
0,1
<LFS2 = 0, LFS3 = 1> fOSC/32
D5, D6
LACS0, LACS1
0,1
<LACS0 = 0, LACS1 = 1> Amp. current = 2.5 µA
D0
SCN0
−
SCN0 control pin is valid
D1
SCN1
−
SCN1 control pin is valid
D2
SCN2
−
SCN2 control pin is valid
D3
STVSEL
0
<STVSEL = 0> low-level is valid
D4
OE1SEL
0
<OE1SEL = 0> OE1 = low-level, gate output OFF
D5
OE2SEL
0
<OE2SEL = 0> OE2 = low-level, gate output ON
Remark When IFSEL = H (when using the control pins), the GCS, GCL, and GDA pins are pulled down to low level, so
be sure to leave these pins open.
When IFSEL = L (when using the serial interface), DCON, RGONR, VCD2, VMS, FS0, FS2, CLS0, RGON,
VSEL, EXRV, ACS0, SCN0, SCN1, SCN2, PUPT0, DUPF0 pins should be left open.
Preliminary Product Information S15797EJ1V4PM
21
µPD161644
(2/2)
Register
Bit
Symbol
Setting value
Conditions
R30
D0
NLINE1
1
D1
NLINE2
1
D2
COMON
0
<COMON = 0> COM_AMP, COM output OFF
<NLINE = 1, NLINE2 = 1> normal mode
R31
D0 to D7
DA0 to DA7
0
<DA0 to DA7> 0
R32
D0 to D7
CDA0 to CDA7
0
<CDA0 to CDA7> 0
R33
D0
PUPT0
−
PUPT0 control pin is valid
D1
PUPT1
0
D2
DUPF0
−
D3
DUPF1
0
D4
PON
1
<PON = 1> Internal sequence
D5
PONM
1
<PONM = 1> Internal sequence
D0
RES
0
<RES = 0> Normal operation
R34
<PUPT0 = 0> RGONR = 2048/fOSC
<PUPT0 = 1> RGONR = 256/fOSC
DUPF0 control pin is valid
<DUPF0 = 0> fOSC/8
<DUPF0 = 1> fOSC/16
Remark When IFSEL = H (when using the control pins), the GCS, GCL, and GDA pins are pulled down to low level, so
be sure to leave these pins open.
When IFSEL = L (when using the serial interface), DCON, RGONR, VCD2, VMS, FS0, FS2, CLS0, RGON,
VSEL, EXRV, ACS0, SCN0, SCN1, SCN2, PUPT0, DUPF0 pins should be left open.
22
Preliminary Product Information S15797EJ1V4PM
µPD161644
5. MODE DESCRIPTION
5.1 Output Mode and Gate Scan Selection
Normal mode: NLINE1 =1, NLINE2 = 1
Scan MODE
R,/L
MODE1
H
1→240, 241
L
241→2,1
H
1→121 • 241→123, 122
L
122→241 • 121→2, 1
H
1→161 • 241→163, 162
L
162→241 • 161→2, 1
MODE4
H
1→201, 241→203, 202
L
202→241 • 201→2, 1
MODE5
H
1, 241, 2, 240, 3, 239…..118, 124, 119, 123, 120, 122, 121
L
121, 122, 120, 123, 119, 124…..4, 239, 3, 240, 2, 241, 1
MODE2
MODE3
Scan direction
Dummy output
Cascade output
241
240
1
2
122
123
1
2
162
163
1
2
202
203
1
2
121
122
1
241
Dummy output
Cascade output
241
240
1
2
122
123
1
2
162
163
1
2
202
203
1
2
1-line step mode: NLINE1 =1, NLINE2 = 0
Scan MODE
R,/L
MODE1
H
1, 3, 5…235, 237, 239, 241 • 2, 4, 6…236, 238, 240
L
241, 239, 237…7, 5, 3, 1 • 240, 238, 236…6, 4, 2
H
1, 3, 5…117, 119, 121 • 240, 238, 236…128, 126, 124, 122,
MODE2
Scan direction
• 2, 4, 6…116, 118, 120 • 241, 239, 237…127, 125, 123
L
122, 124, 126…236, 238, 240 • 121, 119, 117…7, 5, 3, 1,
• 123, 125, 127…237, 239, 241 • 120, 118, 116…6, 4, 2
MODE3
H
1, 3, 5…157, 159, 161 • 240, 238, 236…168, 166, 164, 162
L
162, 164, 166…236, 238, 240 • 161, 159, 157…7, 5, 3, 1,
H
1, 3, 5…197, 199, 201 • 240, 238, 236…208, 206, 204, 202,
• 2, 4, 6…156, 158, 160 • 241, 239, 237…167, 165, 163
• 163, 165, 167…237, 239, 241 • 160, 158, 156…6, 4, 2
MODE4
• 2, 4, 6…196, 198, 200 • 241, 239, 237…207, 205, 203
L
202, 204, 206…236, 238, 240 • 201, 199, 197…7, 5, 3, 1,
• 203, 205, 207…237, 239, 241 • 200, 198, 196…6, 4, 2
Preliminary Product Information S15797EJ1V4PM
23
µPD161644
2-line step mode: NLINE1 = 0, NLINE2 = 1
Scan MODE
R,/L
MODE1
H
Scan direction
1, 4, 7…232, 235, 238, 241 • 2, 5, 8…233, 236, 239
Dummy output
Cascade output
241
240
1
2
122
123
1
2
162
163
1
2
202
203
1
2
Dummy output
Cascade output
• 3, 6, 9…234, 237, 240
L
241, 238, 235…10, 7, 4, 1 • 240, 237, 234…9, 6, 3
• 239, 236, 233…8, 5, 2
MODE2
H
1, 4, 7…115, 118, 121 • 239, 236, 233…131, 128, 125, 122,
• 2, 5, 8…113, 116, 119 • 241, 238, 235…130, 127, 124
• 3, 6, 9…114, 117, 120 • 240, 237, 234,…129, 126, 123
L
122, 125, 128…233, 236, 239 • 121, 118, 115…10, 7, 4, 1,
• 123, 126, 129…234, 237, 240 • 120, 117, 114…9, 6, 3
• 124, 127, 130…235, 238, 241 • 119, 116, 113…8, 5, 2
MODE3
H
1, 4, 7…154, 157, 160 • 240, 237, 234…171, 168, 165, 162,
• 2, 5, 8…155, 158, 161 • 239, 236, 233…170, 167, 164
• 3, 6, 9…153, 156, 159 • 241, 238, 235…169, 166, 163
L
162, 165, 168…234, 237, 240 • 160, 157, 154…10, 7, 4, 1,
• 163, 166, 169…235, 238, 241 • 159, 156, 153…9, 6, 3
• 164, 167, 170…233, 236, 239 • 161, 158, 155..8, 5, 2
MODE4
H
1, 4, 7…193, 196, 199 • 241, 238, 235…211, 208, 205, 202,
• 2, 5, 8…194, 197, 200 • 240, 237, 234…210, 207, 204
• 3, 6, 9…195, 198, 201 • 239, 236, 233…209, 206, 203
L
202, 205, 208…235, 238, 241 • 199, 196, 193…10, 7, 4, 1,
• 203, 206, 209…2337, 236, 239 • 201, 198, 195…9, 6, 3
• 204, 207, 210…234, 240, 200 • 197, 194…8, 5, 2
N-frame reverse: NLINE1 = 0, NLINE2 = 0
Scan MODE
R,/L
FMR
MODE1
H
1
1→240, 241
241
240
0
241→2, 1 (reverse operation)
241
2
1
241→2, 1
1
2
0
1→240, 241 (reverse operation)
1
240
L
Scan direction
5.2 DC/DC OSC Frequency Selection
24
CLS0
CLS1
OSC oscillation frequency for DC/DC converter
DCCLK
0
0
fOSC = 18 kHz
Open
1
0
fOSC = 25 kHz
Open
0
1
fOSC = 37 kHz
Open
1
1
fOSC = External CK
External CK input
Preliminary Product Information S15797EJ1V4PM
µPD161644
5.3 DC/DC Converter Control
DCON
VD1ON
VD2ON
VS2ON
VS3ON
VS4ON
State of VDD1, VDD2, VSS2, VSS3, VSS4
0
x
x
x
x
x
VDD1, VDD2, VSS2, VSS3, VSS4: OFF
1
0
−
−
−
−
VDD1: OFF
1
1
−
−
−
−
VDD1: ON
1
−
0
−
−
−
VDD2: OFF
1
−
1
−
−
−
VDD2: ON
1
−
−
0
−
−
VSS2: OFF
1
−
−
1
−
−
VSS2: ON
1
−
−
−
0
−
VSS3: OFF
1
−
−
−
1
−
VSS3: ON
1
−
−
−
−
0
VSS4: OFF
1
−
−
−
−
1
VSS4: ON
Remark x: 0 or 1
5.4 VDD2 Boost Selection
VCD2
VDD2
0
VDC x 2 boost
1
VDC x 3 boost
5.5 Division Ratio Selection of the DC/DC Converter at Power on
PONM
PON
DUPF0
DUPF1
Division ratio of the DC/DC converter OSC frequency
1
x
0
0
Internal sequence: OSC = fOSC/8
1
x
1
0
Internal sequence: OSC = fOSC/16
1
x
0
1
Internal sequence: OSC = fOSC/2
1
x
1
1
Internal sequence: OSC = fOSC/4
0
1
0
0
External sequence: OSC = fOSC/8
0
1
1
0
External sequence: OSC = fOSC/16
0
1
0
1
External sequence: OSC = fOSC/2
0
1
1
1
External sequence: OSC = fOSC/4
0
0
x
x
Normal mode
Remark x: 0 or 1
5.6 DC/DC Converter Power on Time Selection
PONM
PON
PUPT0
PUPT1
VD2ON
RGONR
VS2ON to VS4ON
VD1ON
1
x
0
0
16/fOSC
2048/fOSC
1.5 x 2048/fOSC
2.5 x 2048/fOSC
Internal sequence
1
x
1
0
16/fOSC
256/fOSC
1.5 x 256/fOSC
2.5 x 256/fOSC
Internal sequence
1
x
0
1
16/fOSC
512/fOSC
1.5 x 512/fOSC
2.5 x 512/fOSC
Internal sequence
1
x
1
1
16/fOSC
1024/fOSC
1.5 x 1024/fOSC
2.5 x 1024/fOSC
Internal sequence
0
1
x
x
External input
External input
External input
External input
External sequence
0
0
x
x
Normal mode
Remark x: 0 or 1
Preliminary Product Information S15797EJ1V4PM
25
µPD161644
5.7 Division Ratio Selection of the DC/DC Converter OSC Frequency
Division ratio of the DC/DC converter
OSC frequency
LPM
FS0
FS1
FS2
FS3
LFS0
LFS1
LFS2
LFS3
0
0
0
x
x
x
x
x
x
VDD2, VSS4: fOSC/2
0
1
0
x
x
x
x
x
x
VDD2, VSS4: fOSC/4
0
0
1
x
x
x
x
x
x
VDD2, VSS4: fOSC/8
0
1
1
x
x
x
x
x
x
VDD2, VSS4: fOSC/16
0
x
x
0
0
x
x
x
x
VDD1, VSS2, VSS3: fOSC/2
0
x
x
1
0
x
x
x
x
VDD1, VSS2, VSS3: fOSC/4
0
x
x
0
1
x
x
x
x
VDD1, VSS2, VSS3: fOSC/8
0
x
x
1
1
x
x
x
x
VDD1, VSS2, VSS3: fOSC/16
1
x
x
x
x
0
0
x
x
VDD2, VSS4: fOSC/8
1
x
x
x
x
1
0
x
x
VDD2, VSS4: fOSC/16
1
x
x
x
x
0
1
x
x
VDD2, VSS4: fOSC/32
1
x
x
x
x
1
1
x
x
VDD2, VSS4: fOSC/64
1
x
x
x
x
x
x
0
0
VDD1, VSS2, VSS3: fOSC/8
1
x
x
x
x
x
x
0
0
VDD1, VSS2, VSS3: fOSC/16
1
x
x
x
x
x
x
1
1
VDD1, VSS2, VSS3: fOSC/32
1
x
x
x
x
x
x
1
1
VDD1, VSS2, VSS3: fOSC/64
Remark x: 0 or 1
5.8 Amp. Current Selection
RGON, RGONR
LPM
ACS0
ACS1
LACS0
LACS1
VR condition
VS condition
0
x
x
x
x
x
VSS1
VSS1
Amp, CS Power OFF
1
0
0
0
x
x
Output
Output
Amp. current = 5 µA
1
0
0
1
x
x
Output
Output
Amp. current = 10 µA
1
0
1
0
x
x
Output
Output
Amp. current = 15 µA
1
0
1
1
x
x
Output
Output
Amp. current = 30 µA
1
1
x
x
0
0
Output
Output
Amp. current = 1.25 µA
1
1
x
x
0
1
Output
Output
Amp. current = 2.5 µA
1
1
x
x
1
0
Output
Output
Amp. current = 5 µA
1
1
x
x
1
1
Output
Output
Amp. current = 7.5 µA
Remark x: 0 or 1
5.9 VR Regulator Selection Output
Register control
RGONR
VRSEL0
VRSEL1
VRSEL2
0
x
x
x
VR regulator OFF (VR = VSS1)
VR
1
0
0
0
3V
1
1
0
0
3.5 V : Internal resistor connection
1
0
1
0
4V
1
1
1
0
4.5 V : Internal resistor connection
1
0
0
1
4.75 V: Internal resistor connection
1
1
0
1
5V
1
0
1
1
5.25 V: Internal resistor connection
1
1
1
1
5.5 V : Internal resistor connection
: Internal resistor connection
: Internal resistor connection
: Internal resistor connection
Remark x: 0 or 1
26
Preliminary Product Information S15797EJ1V4PM
State of Circuit Current
µPD161644
Pin control
RGONR
VR
0
VR regulator OFF (VR = VSS1)
1
5 V: Internal resistor connection
5.10 VS Regulator Selection Output
Register control
RGON
EXRV
VSEL0
VSEL1
VSEL2
MVS condition
0
x
x
x
x
Hi-Z
VS
1
1
x
x
x
Amp.-input
1
0
0
0
0
Hi-Z
3V
: Internal resistor connection
1
0
1
0
0
Hi-Z
3.5 V
: Internal resistor connection
1
0
0
1
0
Hi-Z
4V
: Internal resistor connection
1
0
1
1
0
Hi-Z
4.5 V
: Internal resistor connection
1
0
0
0
1
Hi-Z
4.75 V
: Internal resistor connection
1
0
1
0
1
Hi-Z
5V
: Internal resistor connection
1
0
0
1
1
Hi-Z
5.25 V
: Internal resistor connection
1
0
1
1
1
Hi-Z
5.5 V
: Internal resistor connection
VS regulator OFF (VS = VSS1)
External resistor connection
Remark x: 0 or 1
Pin control
RGON
VSEL
VR
0
x
VS regulator OFF (VS = VSS1)
1
0
5 V : Internal resistor connection
1
1
4 V : Internal resistor connection
Remark x: 0 or 1
5.11 Control of VM Output Control, VCOM Output
COMON
COMHI
DAC, COM_AMP
VCOM
0
x
OFF
Hi-Z
1
0
ON
Hi-Z
1
1
ON
Output
Remark x: 0 or 1
Preliminary Product Information S15797EJ1V4PM
27
µPD161644
5.12 VCOM Output Frequency Adjustment
This is used to adjust the output amplitude of VCOM output. The VCOM output amplitude voltage (VCOMpp) can be
adjusted as shown by the expression below using power supply control register 9 (R31), which is the output voltage of a
D/A converter circuit for which VS is the reference potential.
VCOMpp = VS x 2 x {4/5 x (DAR31/255) }
Remark DAR31: R31 setting values
The values of R31 that can be set are determined by the relationship of booster voltages VDD2 and VSS4 to the potential
level of the actual common drive waveform after VCOM center adjustment.
Set the VCOM output amplitude voltage according to R31, the VCOM output center potential voltage setting level
according to power supply control register 10 (R32), or the VCOM output center potential input from VCOMIN in the
relationships shown in the figure below.
1/2VCOMpp
VDD2
VDD2 −0.2 V
Common drive waveform
VCOMpp
VCOMH
VSS
Voltage ranges that
can be set for common
drive waveform
Figure 5-1. Voltage Ranges that can be set for Common Drive Waveform
VCOMC
VCOML
VSS4 +0.2 V
1/2VCOMpp
★
VSS4
<Conditions on common drive waveform voltage settings>
VCOMpp ≥ 2 V
VCOMH ≤ VDD2 − 0.2 V
VCOML ≥ VSS4 + 0.2 V
Remark VCOMH = 1/2 VCOMpp + VCOMC
VCOML = 1/2 VCOMpp − VCOMC
VCOMC: R32 setting values [COMSEL(R30) = 0] or VCOMIN input voltage level [COMSEL (R30) = 1]
28
Preliminary Product Information S15797EJ1V4PM
µPD161644
VCOM output amplitude voltage (VCOMpp) adjustment and D/A converter setting values
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DAR31
VCOMpp (VS = 5 V)
0
0
0
0
0
0
0
0
0
0.0000 V (Setting prohibited)
0
0
0
0
0
0
0
1
1
0.0314 V (Setting prohibited)
0
0
0
0
0
0
1
0
2
0.0627 V (Setting prohibited)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
1
1
1
1
1
0
62
1.9451 V (Setting prohibited)
0
0
1
1
1
1
1
1
63
1.9765 V (Setting prohibited)
0
1
0
0
0
0
0
0
64
2.0078 V
0
1
0
0
0
0
0
1
65
2.0392 V
0
1
0
0
0
0
1
0
66
2.0706 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
1
253
7.9373 V
1
1
1
1
1
1
1
0
254
7.9686 V
1
1
1
1
1
1
1
1
255
8.0000 V
Remark The range in which the VCOM output amplitude can be varied is restricted by the output voltage of VDD2 and
VSS4.
★
5.13 VCOM Output Center Adjustment
This is used to adjust the center potential level of VCOM output. The VCOM output center potential voltage (VCOMC)
can be adjusted as shown by the expression below using power supply control register 9 (R32), which is the output
voltage of a D/A converter circuit for which VS is the reference potential.
VCOMpp = VS x {4/5 x (DAR32/255) }
Remark DAR32: R32 setting values
VCOM output center potential voltage (VCOMC) and D/A converter setting values
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DAR31
VCOMC (VS = 5 V)
0
0
0
0
0
0
0
0
0
0.0000 V
0
0
0
0
0
0
0
1
1
0.0157 V
0
0
0
0
0
0
1
0
2
0.0314 V
0
0
0
0
0
0
1
1
3
0.0471 V
0
0
0
0
0
1
0
0
4
0.0627 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
1
253
3.9686 V
1
1
1
1
1
1
1
0
254
3.9843 V
1
1
1
1
1
1
1
1
255
4.0000 V
Remark The range in which the VCOM output center can be varied is restricted by the output voltage of VDD2 and VSS4.
Preliminary Product Information S15797EJ1V4PM
29
µPD161644
The values of R32 that can be set are determined by the relationship of booster voltages VDD2 and VSS4 to the potential
level of the actual common drive waveform due to VCOM output amplitude voltage (VCOMpp) adjustment.
Refer to 5.12 VCOM Output Frequency Adjustment for the relationship between the VCOM output center potential
voltage according to R32 and the VCOM output amplitude voltage (VCOMpp) according to power supply control register 9
(R31).
5.14 VCOM Center Adjustment Selection
The method of setting the center voltage of common drive waveform VCOM is selected according to the setting of
COMSEL (R30).
When COMSEL is set to 1, directly input the VCOM center voltage to the VOMIN pin from outside the IC.
30
COMSEL
VCOM center adjustment
0
Internal D/A is valid (R31 setting is valid).
1
VCOMIN input voltage is valid.
Preliminary Product Information S15797EJ1V4PM
µPD161644
6. PANNEL CONNECTION EXAMPLES
[MODE1]
MODE1R (SCN0 = 1, SCN1 = 1, SCN2 = 1, R,/L = 1)
MODE1R (SCN0 = 1, SCN1 = 1, SCN2 = 1, R,/L = 1)
1
1
TFT
TFT
121
Panel
122
Panel
240
1
240
240
1
µPD161644
MODE1L (SCN0 = 1, SCN1 = 1, SCN2 = 1, R,/L = 0)
µPD161644
Source driver
241
1
240
µPD161644
Source driver
Source driver
MODE1L (SCN0 = 1, SCN1 = 1, SCN2 = 1, R,/L = 0)
Source driver
2
µPD161644
241 122,121
241
2
241
TFT
TFT
122
Panel
121
Panel
2
2
MODE1R (SCN0 = 1, SCN1 = 1, SCN2 = 1, R,/L = 1)
2
1
3
4
MODE1L (SCN0 = 1, SCN1 = 1, SCN2 = 1, R,/L = 0)
Source driver
µPD161644
241
2
TFT
237
239
1
TFT
238
240
240
µPD161644
240
238
241
239
Panel
Source driver
Panel
5
3
Preliminary Product Information S15797EJ1V4PM
4
2
31
µPD161644
[MODE2]
MODE2R (SCN0 = 1, SCN1 = 1, SCN2 = 0, R,/L = 1)
1
MODE2L (SCN0 = 1, SCN1 = 1, SCN2 = 0, R,/L = 0)
Source driver
µPD161644
241 122,121
2
TFT
121
Panel
241
122
123
241
TFT
1
121
Panel
121,123 241
µPD161644
Source driver
2
[MODE3]
MODE3R (SCN0 = 1, SCN1 = 0, SCN2 = 1, R,/L = 1)
1
MODE3L (SCN0 = 1, SCN1 = 0, SCN2 = 1, R,/L = 0)
µPD161644
Source driver
241 162,161
2
TFT
161
Panel
162
241
241
163
1
TFT
161
Panel
161,163 241
µPD161644
Source driver
2
[MODE4]
MODE4R (SCN0 = 1, SCN1 = 0, SCN2 = 0, R,/L = 1)
1
MODE4L (SCN0 = 1, SCN1 = 0, SCN2 = 0, R,/L = 0)
µPD161644
Source driver
241 202,201
TFT
202
Panel
201
241
241
201
TFT
203
1
201,203 241
µPD161644
32
Panel
Source driver
2
Preliminary Product Information S15797EJ1V4PM
2
µPD161644
O240
O241
DUMMY
OPEN (pull-down)
1 uF/25 V
VCC+ VSS
2.5 to 3.3 V
2.5 to 3.3 V
0.1 uF/10 V
0.1 uF/10 V
0.1 uF/10 V
1 uF/10 V
1 uF/25 V
Schottky diode
IFSEL : L (when in serial interface input)
IFSEL : H (control pin input)
DUMMY
TESTOUT2
TESTIN2
TESTIN1
TESTOUT1
PVCC1
DUPF0
PUPT0
SCN2
SCN1
SCN0
ACS0
EXRV
VSEL
CLS0
FS2
FS0
VMS
RGONR
PVSS1
PVSS3
VMON
DUMMY
PVCC1
R,/L
IFSEL
PVSS1
VCOMIN
VCOM
COML
COMH
VM
VB
VSS3
VSS4
VSS2
C6C6+
C5C5+
C4C4+
C3C3+
VDD1
C2C2+
C1C1+
VDD2
VSS1
DUMMY
VDC
VCC1
VSS1
VR
VGD
MVS
VS
DUMMY
PVCC1
VCD2
RGON
DCON
FRM
VCIN
PVSS1
/GRESET
GCS
GCL
GDA
STVR
STVL
DCCLK
CLK
OE1
OE2
VSS3
DUMMY
1 uF/10 V
1 uF/10 V
BUMP SIDE UP
DUMMY
O1
O2
Connect to PVSS/PVCC1
7. CONNECTION EXAMPLE WITH SOURCE DRIVER
DUMMY
VC2
DUMMY
GOE2
GOE1
GCLK(CPV)
DMSTB
GSTB(STV)
GDA
GCL
GCS
/GRESET
VCOUT3
GFRM
VCC1
TOUT
TOUT
TOUT
TOUT
DUMMY
TOUT
DUMMY
DAC0-DAC7
TBGR
TBSEL2
TBSEL1
DUMMY
VC2
DUMMY
Y528
Y527
Y526
VSS(MODE)
VCOUT2
V0-V5
VS
FBRSEL
VSS(MODE)
BGRIN
VCOMR
RGB00-25
DOTCLK
HSYNC
VSYNC
VCC1(MODE)
TDELAY1-6
VSS(MODE)
BLCS_I
SO
SCL
SI
VSS(MODE)
CPU interface
BUMP SIDE UP
VSS(MODE)
TOSCO
TOSCI
TOSCSELI
TOSCSELO
TSTRTST
TSTVIHL
Generate logic part supply voltage inside µPD161621.
RGB interface
VSS(MODE)
Because of using specified interface for gate driver interface,
leave them open.
VSS(MODE)
DUMMY
VCOM
DUMMY
VCOUT1
DUMMY
CVPH
CVPL
CVNH
CVNL
VSS
VSTBY
VCC1
VCC11
SF_VCC1
DCON
RGON
LPM
VCD2
RGB/CPU
/RD
/WR
RS
/RESET
/CS
VSS(MODE)
D0-D17
CSTB
VSS(MODE)
IF_SHARE
VCC1(MODE)
DDS
VSS(MODE)
Using D17-D01 only as parallel interface.
BWS2
VCC1(MODE)
BWS1
VSS(MODE)
BWS0
VCC1(MODE)
DTX2
VSS(MODE)
DTX1
VCC1(MODE)
C86
VSS(MODE)
PSX
VCC1(MODE)
DCKEG
VSS(MODE)
VSEG
VCC1(MODE)
HSEG
VSS(MODE)
SCLEG0
VSS(MODE)
OSCIN
VSS(MODE)
OSCOUT
VSS(MODE)
OSCSEL
VCC1(MODE)
TOUT0-17
VCC1(MODE)
BLSDA
BLSCL
/BLCS_O
VSS(MODE)
Y3
Y2
Y1
DUMMY
VC1
DUMMY
GOE2
GOE1
GCLK
DMSTB
GSTB
GDA
GCL
GCS
/GRESET
VCOUT3
GFRM
DUMMY
VC1
DUMMY
Back panel LCD control
SCLEG1
Select on-chip oscillator
VCC1(MODE)
Preliminary Product Information S15797EJ1V4PM
33
µPD161644
8. VALUE OF WIRING RESISTANCE TO EACH PIN
The recommended wiring resistance values are shown below. The wiring resistance values affect the current capacity
of the power supply, so be sure to design using values that do not exceed those recommended.
Table 8-1. Recommended Wiring Resistor Values
Pin name
Wiring Resistor Values (Ω)
VSS1
< 10
VCC1
< 10
VDC
< 10
VS
< 10
VDD2
< 10
C1
+
C1
C2
+
C2
−
< 10
< 10
< 10
< 10
VDD1
< 50
VSS2
< 50
VSS3
< 50
VSS4
< 50
C3
+
C3
C4
−
+
C5
C6
−
+
C4
C5
−
+
C6
34
−
−
< 50
< 50
< 50
< 50
< 50
< 50
< 50
< 50
Preliminary Product Information S15797EJ1V4PM
µPD161644
9. RECOMMENDED CAPACITANCE VALUES OF EXTERNAL CAPACITOR
The recommended capacitance values of the external capacitor are shown below. These values should be finally
determined only after performing sufficient evaluation on the module.
Table 9-1. Recommended Values of External Capacitor
Pin name
VS
Recommended value of
capacitors (µF)
Withstanding voltage (V)
1 to 4.7
6.3 or more
VR
1 to 4.7
6.3 or more
VDD1
0.47 to 1
25 or more
VDD2
1 to 4.7
15 or more
VSS2
0.47 to 1
25 or more
VSS3
0.47 to 1
25 or more
VSS4
1 to 4.7
10 or more
COMH
1 to 4.7
6.3 or more
COML
1 to 4.7
6.3 or more
1 to 4.7
10 or more
+
−
+
−
+
−
+
−
+
−
+
−
C1 , C1
C2 , C1
C3 , C1
C4 , C1
C5 , C1
C6 , C1
1 to 4.7
10 or more
0.47 to 1
10 or more
0.47 to 1
10 or more
0.47 to 1
10 or more
1 to 4.7
10 or more
Preliminary Product Information S15797EJ1V4PM
35
µPD161644
10. SERIAL INTERFACE
When the serial interface has been selected, if the chip is active (GCS = L), serial data input (GDA) and serial clock
input (GCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial clock, via
the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to parallel
data for processing.
The serial interface signal chart is shown below.
Figure 10-1. Serial Interface Signal Chart
GCS
GDA
A7
A6
A5
A4
A3
A2
A1
A0
D7
1
2
3
4
5
6
7
8
9
D6
D5
D4
D3
D2
D1
D0
GCL
10
11
12
13
14
15
16
Data to set command
Command
Note that odd bytes of data received after the reset command is input are recognized as commands, and even bytes
of data are recognized as data values to be set to commands.
Remarks 1. The shift register and counter are reset to their initial values when the chip select signal is inactive. Do not
set the chip select signal to inactive between transmission of an 8-bit command and transmission of the 8bit data set for the command.
2. When using GCL wiring, take care concerning the possible effects of terminating reflection and noise from
external sources. We recommend checking operation with the actual device.
36
Preliminary Product Information S15797EJ1V4PM
µPD161644
11. TIMING CHARTS (MODE1: SCN0 = 1, SCN1 = 1, SCN2 = 1)
R,/L = H, STVSEL = 0, OE1SEL = 0, OE2SEL = 0
1
2
3
4
239
240
241
242
243
244
245
246
247
240
241
242
243
244
245
246
247
CLK
OE1
OE2
STVR
O1
O2
O3
O239
O240
O241
STVL
(O1)
(O2)
(O3)
(O4)
(O5)
(O6)
R,/L = L, STVSEL = 1, OE1SEL = 1, OE2SEL = 1
1
2
3
4
239
CLK
OE1
OE2
STVL
O240
O239
O238
O2
O1
O241
STVR
(O240)
(O239)
(O238)
(O237)
(O236)
(O235)
Preliminary Product Information S15797EJ1V4PM
37
µPD161644
12. POWER ON/OFF SEQUENCE
There are three ways to turn on the power of the µPD161644:
<When power supply is controlled by serial interface>
• Simple sequence
• Command control sequence
<When power supply is controlled by pin>
• Simple sequence
12.1 Power ON sequence
(1) Power supply control via serial interface (simple sequence)
Control /GRESET pin and each command of PONM, VD2ON, RGONR, RGON, VS2ON, VS3ON, VD1ON, and DCON
using the following sequence, after applying power to VDC, VCC1, and VCC11.
VDC
2.5 V
VCC1
0 ns MIN.
1.8 V
VCC11
0 ns MIN.
/GRESET
Wait 0 ns MIN.
PONM
Wait 0 ns MIN.
Turn on the power
Note
supply to be used
Wait 0 ns MIN.
DCON
<1> Issue the reset command (R34)
Power-on operation is complete after the
time specified by PUPT0 and PUPT1 has
elapsed.
<2> Set a value to R25 to R33 (any value)
Note Turn on the power supply to be used among VD2ON, RGONR, RGON, VS2ON, VS3ON, and VD1ON.
38
Preliminary Product Information S15797EJ1V4PM
µPD161644
(2) Power control by serial interface (command control sequence)
Control /GRESET pin and each command of PON, DCON, VD2ON, RGONR, RGON, VS2ON, VS3ON, VD1ON, and
VS4ON after power on of VDC, VCC1, VCC11 as shown below.
VDC
2.5 V
VCC1
0 ns MIN.
1.8 V
VCC11
0 ns MIN.
/GRESET
Wait 0 ms MIN.
PON
Wait 0 ms MIN.
DCON
Wait 1 ms MIN.
VD2ON
Wait 25 ms MIN.
RGONR
NOTE 1
Wait 0 ms MIN.
RGON
Wait 40 ms MIN.
VS2ON, VS3ON
NOTE 2
Wait 60 ms MIN.
VD1ON
Wait 60 ms MIN.
VS4ON
NOTE 3
Wait 60 ms MIN.
<1> Issue the reset command (R34)
Power-on operation is complete.
<2> Set a value to R25 to R32 (any value)
Notes 1. This pin only needs to be controlled when the VR amplifier is used.
2. VS2ON only needs to be controlled when VSS2 is used.
3. This pin only needs to be controlled when VCOM is used.
Preliminary Product Information S15797EJ1V4PM
39
µPD161644
(3) Power control by pins (simple sequence)
Control each pin of /GRESET, RGON, and DCON after power on of VDC, VCC1, VCC11 as shown below.
VDC
VCC1
2.5 V
0 ns MIN.
1.8 V
VCC11
0 ns MIN.
/GRESET
wait 10 ms MIN.
RGON
wait 0 ms MIN.
DCON
Power supply startup is complete after the time
specified by PUPT0 and PUPT1 has elapsed
Remarks 1. When using RGON, pull it up to the high level by wiring the RGONR pin.
2. When using VSS4, pull it up to the high level by wiring the COMON pin.
40
Preliminary Product Information S15797EJ1V4PM
µPD161644
12.2 Power OFF sequence
When turning the power off, turn off the pins and commands used for control simultaneously, both when performing
control via the serial interface and via the pins.
(1) Power control by serial interface (Simplified sequence)
Control DCON pin as shown below.
VDC
0 ns
VCC1
0 ns
VCC11
0 ns
/GRESET
0 ns
DCON
(2) Power control by serial interface (Command control sequence)
Control each pin of /GRESET, RGON, and DCON as shown below.
VDC
0 ns
VCC1
0 ns
VCC11
0 ns
/GRESET
PON
0 ms
VS4ON Note1
0 ms
VD1ON
0 ms
VS2ON, VS3ON Note2
0 ms
RGON
0 ms
RGONR Note3
0 ms
VD2ON
0 ms
DCON
Notes 1. This pin only needs to be controlled when the VCOM is used.
2. VS2ON only needs to be controlled when VSS2 is used.
3. This pin only needs to be controlled when VR amplifier is used.
Preliminary Product Information S15797EJ1V4PM
41
µPD161644
(3) Power control by pins (Simplified sequence)
Control each pin of /GRESET, RGON, and DCON as shown below.
VDC
0 ns
VCC1
0 ns
VCC11
0 ns
/GRESET
0 ns
DCON
RGON
0 ns
Remarks 1. When using RGON, pull it up to the high level by wiring the RGONR pin.
2. When using VSS4, pull it up to the high level by wiring the COMON pin.
42
Preliminary Product Information S15797EJ1V4PM
µPD161644
13. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Parameter
Symbol
Rating
Unit
Supply Voltage
VCC1
−0.5 to +4.0
V
Supply Voltage
VDC
−0.5 to +4.0
V
Supply Voltage
VSS3
VDD1 −42 V to +0.5
V
Supply Voltage
VDD1-VSS3
−0.5 to +42
V
Input Voltage Note 1
VI
−0.5 to VCC1+0.5
V
Input Current Note 1
II
±1
mA
Output Current Note 2
IO1
±10
mA
Output Current Note 3
IO2
+10
mA
Operating Ambient Temperature
TA
−40 to +85
°C
Storage Temperature
Tstg
−55 to +150
°C
Notes 1. CLK, STVR, STVL, R,/L, OE1, OE2, GCS, GCL, GDA, DCCLK, VCIN, DCON, RGON, VCD2, /GRESET,
IFSEL, EXRV, SCN0, SCN1
2. STVR, STVL, VM, VCOM
3. VS
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = –40 to +85°°C, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
V
Supply Voltage
VCC1
2.5
2.7
3.3
Supply Voltage
VDC
2.5
2.7
3.3
V
Supply Voltage
VDD1
10
15
20
V
Supply Voltage
VSS3
−20
−15
−10
V
Supply Voltage
VDD1-VSS3
20
30
40
V
Supply Voltage
VGD
6.0
V
Input Voltage Note
VI
VCC1
V
0
Note CLK, STVR, STVL, R,/L, OE1, OE2, GCS, GCL, GDA, DCCLK, VCIN, DCON, RGON, VCD2, /GRESET, IFSEL,
EXRV, SCN0, SCN1
Preliminary Product Information S15797EJ1V4PM
43
µPD161644
Electrical Characteristics (TA = −40 to +85°°C, VCC1 = 2.5 to 3.3 V, VDC = 2.5 to 3.3 V, VDD1 = 15 V, VSS3 = −15 V,
VS = 5 V, VSS1 = 0 V)
(1/2)
Parameter
Symbol
High-level input voltage
VIH1
Low-level input voltage
VIL1
High-level output voltage
Condition
MIN.
TYP.
MAX.
Unit
Note 1
0.8 VCC1
V
VOH
STVR, STVL, IOH = − 40 µA
VCC1 −0.4
Low-level output voltage
VOL
STVR, STVL, IOH = +40 µA
VDD1 boost voltage
VDD1
IDD1 = 300 µA, 3 x boost, Note 2
2.7 VGD
−
VDD2 boost voltage1
VDD21
IDD2 = 1 mA , VCD2 = L, VMS = H (2 x
boost, dual), Note 2
1.9 VDC
−
2 VDC
V
VDD2 boost voltage2
VDD22
IDD2 = 1 mA , VCD2 = L, VMS = L (2 x
boost, single), Note 2
1.8 VDC
−
2 VDC
V
VDD2 boost voltage3
VDD23
IDD2 = 1 mA , VCD2 = H (3 x boost),
Note 2
2.7 VDC
−
3 VDC
V
VSS2 boost voltage
VSS2
ISS2 = − 300 µA, −2 x boost, Note 2
−2 VS
−
−1.8 VS
V
VSS3 boost voltage
VSS3
ISS3 = − 300 µA, −3 x boost, Note 2
−3 VS
−
−2.7 VS
V
VSS4 boost voltage
VSS4
ISS4 = − 300 µA, −1 x boost, Note 2
−VDC
−
−0.9 VDC
V
VDD1 output resister
RVDD1
IDD1 = 300 µA, 3 x boost, Note 2
−
3
5
kΩ
VDD2 output resistor1
RVDD21
IDD2 = 1 mA , VCD2 = L, VMS = H (2x
boost, dual), Note 2
−
100
200
Ω
VDD2 output resistor2
RVDD22
IDD2 = 1 mA , VCD2 = L, VMS = L (2x
boost, single), Note 2
−
250
400
Ω
VDD2 output resistor3
RVDD23
IDD2 = 1 mA , VCD2 = H (3 x boost),
Note 2
−
450
700
Ω
VSS2 output resistor
RVSS2
ISS2 = − 300 µA , −2 x boost, Note 2
−
3
5
kΩ
VSS3 output resistor
RVSS3
ISS2 = − 300 µA , −3 x boost, Note 2
−
3
5
kΩ
VSS4 output resistor
RVSS4
ISS2 = − 300 µA , −1 x boost, Note 2
−
300
500
Ω
VS output voltage
VS
No load
4.5
5
5.5
V
VR output voltage
VR
No load
4.5
5
5.5
V
VS output resistor
RVS
VDD2 = 6 V, IS = 1 mA, VS = 5 V
−
15
30
Ω
VR output resistor
RVR
VDD2 = 6 V, IR = 1 mA, VR = 5 V
−
15
30
Ω
COMH output voltage
VcomH
No load, DA (7:0) = CDA (7:0) = A0H
4.5
5
5.5
V
COML output voltage
VcomL
No load, DA (7:0) = CDA (7:0) = A0H
−0.5
0
0.5
V
VCOM output high-level
voltage
VVcomH
IVCOM = 1 mA, DA (7:0) = CDA (7:0) =
A0H, VCIN = H
4.5
5
5.5
V
VCOM output low-level
voltage
VVcomL
IVCOM = −1 mA, DA (7:0) = CDA (7:0) =
A0H, VCIN = L
−0.5
0
0.5
V
COM output resistor1
RCOM1
COM output = High, ICOM = 1 mA
−
100
200
Ω
COM output resistor2
RCOM2
COM output = Low, ICOM = −1 mA
−
100
200
Ω
V
0
0.2 VCC1
V
VCC1
V
0.4
V
3 VGD
V
VM output high-level voltage VM1H
No load
0.9 VSS2
VSS2
1.1 VSS2
VM output low-level voltage
VM1L
No load
0.9 VSS3
VSS3
1.1 VSS3
V
VM output resistance
RM1
When IVM = 100 µA, VSS2 is selected.
−
300
400
Ω
Output ON resistance
RON1
O1 to O241
1
2
4
kΩ
Notes 1. CLK, STVR, STVL, R,/L, OE1, OE2, GCS, GCL, GDA, VCOM, DCON, RGON, LPM, VCD2, /GRESET, IFSEL,
EXRV, SCN0, SCN1, VCIN
2. External capacitor: 1 µF, CLS0 = H, CLS1 = L, FS0 = H, FS1 = L, FS2 = H, FS3 = L, FUP = L
3. ACS0 = H, ACS1 = H, VDD2 = VDC x 2, dual mode, VDD1 = VGD x 3, VSS2 = VGD x (−2), VSS3 = VGD x (−3),
VSS4 = VDC x (−1), VGD = VS, CLS0 = H, CLS1 = L, FS0 = H, FS1 = L, FS2 = H, FS3 = L, FUP = L
44
Preliminary Product Information S15797EJ1V4PM
µPD161644
(2/2)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input current
II1
Note 1
–1
0
1
µA
Input leak current
IIL
STVR, STVL
–1
0
1
µA
Dynamic current
ICC1
VCC1, fCLK = 12.5 kHz, no load, Note 3
−
−
200
µA
Dynamic current
IDC
VDC, fCLK = 12.5 kHz, no load, Note 3
−
−
1.8
mA
Static current
ICC1
VCC1, stand-by
−
−
5
µA
Static current
IDC
VDC, stand-by
−
−
5
µA
VREF voltage
VREF
1.08
1.20
1.32
V
Notes 1. CLK, STVR, STVL, R,/L, OE1, OE2, GCS, GCL, GDA, VCOM, DCON, RGON, LPM, VCD2, /GRESET, IFSEL,
EXRV, SCN0, SCN1, VCIN
2. External capacitor: 1 µF, CLS0 = H, CLS1 = L, FS0 = H, FS1 = L, FS2 = H, FS3 = L, FUP = L
3. ACS0 = H, ACS1 = H, VDD2 = VDC x 2, dual mode, VDD1 = VGD x 3, VSS2 = VGD x (−2), VSS3 = VGD x (−3),
VSS4 = VDC x (−1), VGD = VS, CLS0 = H, CLS1 = L, FS0 = H, FS1 = L, FS2 = H, FS3 = L, FUP = L
Preliminary Product Information S15797EJ1V4PM
45
µPD161644
Switching Characteristics (TA = −40 to +85°°C, VCC1 = 2.5 to 3.3 V, VDC = 2.5 to 3.3 V, VDD1 = 15 V, VSS3 = −15 V,
VS = 5 V, VSS1 = 0 V)
Parameter
Symbol
Cascade Output Delay Time
Condition
MIN.
TYP.
MAX.
Unit
ns
tPHL1
CL = 20 pF
800
tPLH1
CLK → STVL (STVR)
800
ns
tPHL2
CL = 50 pF
1
µs
tPLH2
CLK → On
1
µs
tPHL3
CL = 50 pF
1
µs
tPLH3
OE1 → On
1
µs
tPHL4
CL = 50 pF
1
µs
tPLH4
OE2 → On
1
µs
Output Rise Time
tTLH
CL = 50 pF
1
µs
Output Fall Time
tTHL
1
µs
Driver Output Delay Time 1
Driver Output Delay Time2
Driver Output Delay Time 3
Input Capacitance
CI
TA = 25°C
DC/DC Oscillation Frequency
fDCDC
CLS1 = L, CLS0 = H, FUP = L
12.5
25
15
pF
37.5
kHz
DCCLK Input Frequency
fDCCLK
50
kHz
VCIN Input Frequency
fVCIN
50
kHz
Clock Input Frequency
fCLK
400
kHz
When connected in cascade
Timing Requirement (TA = −40 to +85°°C, VCC1 = 2.5 to 3.3 V, VDC = 2.5 to 3.3 V, VDD1 = 15 V, VSS3 = −15 V,
VS = 5 V, VSS1 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock Pulse High Period
PW CLK(H)
CLK
500
ns
Clock Pulse Low Period
PW CLK(L)
CLK
500
ns
Enable Pulse High Period
PW OE
OE1, OE2
1.0
µs
Data Setup Time
tSETUP
STVR (STVL) ↓ →CLK↑
200
ns
Data Hold Time
tHOLD
CLK↑→STVR (STVL) ↑
200
ns
Serial Clock Cycle
tSCYC
GCL
250
ns
GCL High-level Pulse Width
tSHW
GCL
100
ns
GCL Low-level Pulse Width
tSLW
GCL
100
ns
GDA Data Setup Time
tSDS
GDA
100
ns
GDA Data Hold Time
tSDH
GDA
100
ns
GCS-GCL Time
tCSS
GCS
150
ns
GCL-GCS Time
tCSH
GCS
150
ns
46
Preliminary Product Information S15797EJ1V4PM
µPD161644
Switching Characteristics Waveform (R,/L = H, STVSEL = 0, OE1SEL = 0, OE2SEL = 0)
(a) Gate interface
( ): R,/L = L
1/fCLK
PWCLK(H)
PWCLK(L)
VCC1
CLK
50%
50%
50%
50%
VSS1
tSETUP
tHOLD
VCC1
STVR
(STVL)
50%
50%
VSS1
tPHL1
tPLH1
VCC1
STVL
(STVR)
50%
50%
VSS1
tPLH2
tTLH
tPHL2
90%
tTHL
VDD1
90%
On
10%
10%
VB
PWOE
VCC1
OE1
50%
50%
VSS1
tPHL3
tPLH3
VDD1
90%
On
10%
VB
PWOE
VCC1
OE2
50%
50%
VSS1
tPLH4
tPHL4
VDD1
90%
On
10%
VB
Preliminary Product Information S15797EJ1V4PM
47
µPD161644
(b) Serial interface
tCSS
tCSH
GCS
tSCYC
tSLW
GCL
t SHW
tf
tSDS
tr
t SDH
GDA
48
Preliminary Product Information S15797EJ1V4PM
µPD161644
[MEMO]
Preliminary Product Information S15797EJ1V4PM
49
µPD161644
[MEMO]
50
Preliminary Product Information S15797EJ1V4PM
µPD161644
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Product Information S15797EJ1V4PM
51