DATA SHEET MOS INTEGRATED CIRCUIT µPD16432B 1/8, 1/15 DUTY LCD CONTROLLER/DRIVER DESCRIPTION The µPD16432B is a controller/driver with 1/8 and 1/15 duty dot matrix LCD display capability. It has 60 segment outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12 columns × 2 lines (at 1/15 duty). LED drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use in a car stereo front panel, etc. FEATURES • Dot matrix LCD controller/driver • Pictograph display segment drive capability (max. 64) • LCD driver unit power supply VLCD independently settable (Max. 10 V) • On-chip key scan circuit (8 × 4 matrix) • Alphanumeric character and symbol display capability provided by on-chip ROM (5 × 7 dots) 240 characters + 16 user-defined characters • Display contents 1/8 duty: 13 columns × 1 line, 64 pictograph displays, 4 LEDs 1/15 duty: 12 columns × 2 lines, 60 pictograph displays, 4 LEDs • Serial data input/output (SCK, STB, DATA) • On-chip oscillator • Reduced power consumption possible using standby mode ORDERING INFORMATION Part Number µPD16432BGC-001-9EU Document No. S11092EJ5V0DS00 (5th edition) Date Published April 1998 N CP(K) Printed in Japan Package 100-pin plastic QFP (0.5 pitch, 14 × 14), Standard ROM code © 1998 µPD16432B 4 5 LED Driver COM0 5 Segment Driver 4 COM9 SEG65/COM10 SEG61/COM14 SEG60 SEG8/KS8 SEG9 SEG1/KS1 LED4 LED1 BLOCK DIAGRAM Common Driver 5 65 4-Bit LED Output Latch 15 65-Bit Output Latch 4 15-Bit Shift Register 65 2 65-Bit Shift Register Timing Generator Parallel/Serial Conversion 5 8 5 OSCIN CG RAM 5×7 × 16 CG ROM 5 × 7 × 240 8 OSC Display Data RAM 8 × 25 Character Display RAM 64 Bits OSCOUT 5 8 STB SCK Serial I/F SYNC 2 KEY4 VLC5 VLC4 VLC3 VLC1 VLCD VSS VDD RESET KEY REQ Command Decoder LCD OFF KEY1 Key Data RAM 4×8 VLC2 DATA µPD16432B SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 PIN CONFIGURATION 75 76 51 50 100 1 26 25 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8/KS8 SEG7/KS7 SEG6/KS6 SEG5/KS5 SEG4/KS4 SEG3/KS3 SEG2/KS2 SEG1/KS1 LED1 LED2 LED3 LED4 VSS VLC5 VLC4 VLC3 VLC2 VLC1 VLCD VDD SYNC LCD OFF RESET KEY REQ SCK DATA STB OSCIN OSCOUT KEY1 KEY2 KEY3 KEY4 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61/COM14 SEG62/COM13 SEG63/COM12 SEG64/COM11 SEG65/COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 3 µPD16432B PIN DESCRIPTIONS Pin Symbol Pin Name Function SEG1/KS1 to SEG8/KS8 Segment output/key source output dual-function pins 26 to 33 Pins with dual function as dot matrix LCD segment outputs and key scanning key source outputs SEG9 to SEG60 Segment outputs 34 to 85 Dot matrix LCD segment outputs SEG61/COM14 to SEG85/COM10 Segment output/common output dual-function pins 86 to 90 Switchable to either dot matrix LCD segment outputs or common outputs COM0 to COM9 Common outputs 91 to 100 Dot matrix LCD common outputs LED1 to LED4 LED output pins 1 to 4 LED outputs are Nch open-drain. SCK Shift clock input 17 Data shift clock Data is read on rising edge, and output on falling edge. DATA Data input/output 18 Performs input of commands, key data, etc., and key data output. Input is performed from the MSB on the rise of the shift clock, and the first 8 bits are recognized as a command. Output is performed from the MSB on the fall of the shift clock. Output is Nch open-drain. STB Strobe input 19 Data input is enabled when “H”. Command processing is performed on a fall. KEY REQ Key request output 16 “H” if there is key data, “L” if there is none. Key data can be read irrespective of the state of this pin. Output is CMOS output. RESET Reset input 15 Initial state is set when “L”. LCD OFF LCD off input 14 When “L”, a forced LCD off operation is performed, and SEGn & COMn output the unselected waveform. SYNC Synchro 13 Synchronization signal input/output pin. When 2 or more chips are used, wired-OR connection is made to each chip. A pull-up resistor is also required when one chip is used. OSCIN Oscillation pins 20 Connect oscillator resistor. OSCOUT 4 Pin No. 21 KEY1 to KEY4 Key data inputs 22 to 25 Key scanning key data inputs. VDD Logic power supply pin 12 Internal logic power supply pin VSS GND pin 5 GND pin VLCD LCD drive voltage pin 11 LCD drive power supply pin VLC1 to VLC5 LCD drive power supply 10 to 6 Dot matrix LCD drive power supply µPD16432B LCD DISPLAY In the µPD16432B LCD display, a 5 × 7-segment display and pictograph display segments can be driven. The pictograph display segment common output is allocated to COM0, and up to 64 can be driven. (1) Example of 1/8 duty connections SEG 1 2 3 4 5 6 7 8 9 10 61 62 63 64 65 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0 64 Pictograph Segments (2) Example of 1/15 duty connections SEG 1 2 3 4 5 6 7 8 9 10 56 57 58 59 60 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM0 60 Pictograph Segments 5 µPD16432B CHARACTER CODES AND CHARACTER PATTERNS The relation between character codes and character patterns is shown below. Character codes 00H to 0FH are allocated to CGRAM. Character codes 10H to 1FH and E0H to FFH are undefined. Higher Bits 0XH 1XH 2XH 3XH 4XH 5XH 6XH 7XH 8XH 9XH AXH BXH CXH DXH EXH FXH Lower Bits 6 X0HRAM CG (1) X1HRAM CG (2) X2HRAM CG (3) X3HRAM CG (4) X4HRAM CG (5) X5HRAM CG (6) X6HRAM CG (7) X7HRAM CG (8) X8HRAM CG (9) X9HRAM CG (10) XAHRAM CG (11) XBHRAM CG (12) XCHRAM CG (13) XDHRAM CG (14) XEHRAM CG (15) XFHRAM CG (16) µPD16432B DISPLAY RAM ADDRESSES Display RAM addresses are allocated as shown below irrespective of the display mode. Column No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Line 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH Line 2 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H PICTOGRAPH DISPLAY RAM ADDRESSES Pictograph display RAM addresses are allocated as shown below. Segment Output No. Address b7 b6 b5 b4 b3 b2 b1 b0 00H 1 2 3 4 5 6 7 8 01H 9 10 11 12 13 14 15 16 02H 17 18 19 20 21 22 23 24 03H 25 26 27 28 29 30 31 32 04H 33 34 35 36 37 38 39 40 05H 41 42 43 44 45 46 47 48 06H 49 50 51 52 53 54 55 56 07H 57 58 59 60 61 62 63 64 Note When 1/15 duty is used (12 columns × 2 lines), 61 to 64 are disabled. 7 µPD16432B CGRAM COLUMN ADDRESSES A maximum of any sixteen 5 × 7-dot characters can be written in CGRAM. The row address within one character is allocated as shown below, and is specified by bits b7 to b5. The character code for which a write is to be performed must be specified beforehand with an address setting command. Dot Data Row Address b7 b6 b5 b4 b3 b2 b1 b0 00H 0 0 0 * * * * * 01H 0 0 1 * * * * * 02H 0 1 0 * * * * * 03H 0 1 1 * * * * * 04H 1 0 0 * * * * * 05H 1 0 1 * * * * * 06H 1 1 0 * * * * * Row Address Font Data (5 × 7 Dots) * Font data (1: on, 0: off) 8 µPD16432B KEY MATRIX AND KEY DATA RAM CONFIGURATION The key matrix has an 8 × 4 configuration, as shown below. KEY1 KEY2 = KEY3 KEY4 KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8 Key data is stored as shown below, and is read in MSB-first order by a read command. b7 b4 b3 b0 KS8 KS7 KS6 KS5 KS4 KS3 KS2 KS1 Key data is as follows: 1: On 0: Off Read Order KEY4 KEY3 KEY2 KEY1 Key Input Equivalent Circuit VDD Pull-Up Control Signal R To Key Data RAM KEYn In the event of key source output, the pull-up control signal becomes “H”, and the pull-up transistor is turned on. 9 µPD16432B KEY REQUEST (KEY REQ) A key request is output as shown below according to the state. Note KEY REQ State Key Scan Internal Pull-Up Resistor In key scan operation High level is output while any key Note data is “1”. During key scan : ON During display : OFF In standby mode or when SEGn & COMn are fixed at VLC5 High level is output in case of key input only. Always ON When key scanning is stopped Fixed at low level Always OFF Note KEY REQ does not become low until the key data is all “0”. (It is not synchronized with the key data reads.) LED OUTPUT LATCH CONFIGURATION The low-order 4 bits of the LED output latch are enabled, and the high-order 4 bits disabled, as shown below. MSB × LSB × × × b3 b2 b1 b0 × : Don’t Care LED1 LED2 LED3 LED4 Latch data is as follows: 1: On 0: Off 10 µPD16432B COMMANDS Commands set the display mode and status. The first byte after a rise edge on the STB pin is regarded as a command. If STB is driven low during command/data transfer, serial communication is initialized and the command/data being transferred is invalidated. (However, a command or data that has already been transferred is valid.) (1) Display Setting Command This command initializes the µPD16432B Note , and sets the duty, number of segments, number of commons, master/ slave operation, and the drive voltage supply method. The state set when this command is executed is: LCD off, LED on, key scanning stopped. To restart the display, it is necessary to execute “status command” normal operation. However, nothing is done if the same mode is selected. MSB 0 LSB 0 × × × b2 b1 b0 × : Don’t Care Duty setting 0: 1/8 duty (SEG61/COM14 to SEG65/COM10 → segment outputs) 1: 1/15 duty (SEG61/COM14 to SEG65/COM10 → common outputs) Master/slave setting 0: Master 1: Slave Drive voltage supply method selection 0: External 1: Internal After powering on × × × 0 0 0 Note When multiple chips are used, only the chip that sent the command is enabled. If initialization is performed during display, the display may be affected (especially when multiple chips are used). 11 µPD16432B (2) Data Setting Command Sets the data write mode, read mode, and address increment mode. MSB 0 LSB × 1 × b3 b2 b1 × : Don’t Care b0 Data write mode/read mode setting 000: Write to display data RAM 001: Write to character display RAM 010: Write to CGRAM 011: Write to LED output latch 100: Read key data Address increment mode setting (Display data RAM, character display RAM) 0: Increment after data write 1: Address fixed After powering on × × 0 0 0 0 (3) Address Setting Command Sets the display data RAM or character display RAM address. MSB 1 LSB 0 × b4 b3 b2 b1 b0 ×: Don’t Care Address : 00H to 18H Display data RAM Character display RAM : 00H to 07H : 00H to 0FH CGRAM After powering on × 0 0 0 0 0 Note If an unspecified address is set, data cannot be written until a correct address is next set. The address is not incremented even in increment mode. 12 µPD16432B (4) Status Command Controls the status of the µPD16432. MSB 1 LSB 1 b5 b4 b3 b2 b1 b0 LCD cotrol 00: LCD forced off (SEGn, COMn = VLC5) 01: LCD forced off (SEGn, COMn = unselected waveform) 10: Normal operation 11: Normal operation LED control 0: LED forced off 1: Normal operation Key scan control 0: Key scanning stopped 1: Key scan operation Note Standby mode setting 0: Normal operation 1: Standby mode Test mode setting 0: Normal operation 1: Test mode After powering on 0 0 0 0 0 0 Note The following states are use prohibited modes, and key scanning does not operate if these states are set. 0 0 1 0 0 0 0 0 1 1 0 0 13 µPD16432B STANDBY MODE If standby mode is selected with bit b4 of the status command, the following state is set irrespective of bits b3 to b0 of the status command. (1) LCD forced off (SEGn, COMn = VLC5) (2) LED forced off (3) Key scanning stopped (but KEY n = key input wait) (4) OSC stopped There are two ways of releasing standby mode, as follows: (1) Using Status Command Select normal operation with bit b4 of the status command. Example of Use of Status Command Command/Data Item STB Standby mode L Status command H Standby transition time L Status command H End L Description b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 0 0 0 0 0 Standby release (OSC oscillation start), LCD control off (SEGn, COMn = VLC5), LED forced off, key scanning stopped 10 µs 1 1 0 0 1 1 1 0 Note Normal operation Note If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD may flicker. 14 µPD16432B (2) Using KEYn If any key is set to the ON state, the standby mode is released and OSC oscillation starts. Also, KEY REQ is set to “H”, informing the microcomputer that a key has been pressed and standby mode has been released. In this state, the key data is not memorized, and therefore it is necessary to set key scanning to the normal state after the standby transition time, and fetch the key data. Example of Use of KEYn Command/Data Item STB Description b7 b6 b5 b4 b3 b2 b1 b0 Standby mode L Key data present L Standby release (KEY REQ = H, OSC oscillation start) Standby transition time L 10 µs Status command H Key scan L Data setting command H 0 1 0 0 0 1 0 0 Key data read, address increment Key data H * * * * * * * * For KS8, KS7 Key data H * * * * * * * * For KS6, KS5 Key data H * * * * * * * * For KS4, KS3 Key data H * * * * * * * * For KS2, KS1 End L 1 1 0 0 1 0 0 1 Note LCD forced off (unselected waveform), LED forced off, key scan operation 1 frame or more Key distinction Note If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD may flicker. 15 µPD16432B SERIAL COMMUNICATION FORMATS (1) Reception (Command/Data Write) If data continues STB DATA SCK b7 b6 1 b5 2 b2 3 6 b1 b0 7 8 (2) Transmission (Command/Data Read) STB b7 DATA SCK 1 b6 2 b5 3 b2 6 b1 7 b0 8 1 b7 b6 b5 b4 b3 2 3 4 5 6 1 µs Data Read Command Setting Wait Time tWAIT Data Read Caution As the DATA pin is an Nch open-drain output, a pull-up resistor must be connected externally. (1 kΩ Ω to 10 kΩ Ω) 16 µPD16432B ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V) Parameter Symbol Rating Unit Logic supply voltage VDD –0.3 to +7.0 V Logic input voltage VIN –0.3 to +VDD + 0.3 V Logic output voltage (Dout, LED) VOUT –0.3 to +7.0 V LCD drive supply voltage VLCD –0.3 to +12.0 V VLC1 to VLC5 –0.3 to +VLCD + 0.3 V VOUT2 –0.3 to +VLCD + 0.3 V LED drive current IOL1 20 mA Package allowable dissipation PT 1000 mW Operating ambient temperature TA –40 to +85 °C Storage temperature range Tstg –55 to +150 °C LCD drive power supply input voltage Driver output voltage (Segment, Common) RECOMMENDED OPERATING RANGES Parameter Symbol MIN. TYP. MAX. Unit Logic supply voltage VDD 2.7 5.0 5.5 V LCD drive supply voltage VLCD VDD 8.0 10.0 V Logic input voltage VIN 0 VDD V Driver input voltage VLCD1 to VLCD5 0 VLCD V 15 mA LED drive current IOL1 17 µPD16432B ELECTRICAL SPECIFICATIONS (UNLESS SPECIFIED OTHERWISE, TA = –40 to +85°C, VDD = 5 V ±10%, VLCD = 8 V ±10%) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit High-level input voltage VIH 0.7 VDD VDD V Low-level input voltage VIL 0 0.3 VDD V High-level input current IIH SCK, STB, LCDOFF, RESET, KEY1 to KEY4 1 µA Low-level input current IIL SCK, STB, LCDOFF, RESET, KEY1 to KEY4 –1 µA Low-level output voltage VOL1 LED1 to LED4, IOL1 = 15 mA 1.0 V High-level output voltage VOH2 OSCOUT, KEY REQ, IOH2 = –1 mA Low-level output voltage VOL2 DATA, OSCOUT, SYNC, IOL2 = 4 mA High-level leak current ILOH2 Low-level leak current 0.9 VDD V 0.1 VDD V DATA, SYNC, VIN/OUT = VDD 1 µA ILOL2 DATA, SYNC, VIN/OUT = VSS –1 µA Common output ONresistance RCOM VLCD to VLC5 → COM0 to COM14, | IO | = 100 µA 2.4 kΩ Segment output ONresistance RSEG VLCD to VLC5 → SEG1 to SEG60, | IO | = 100 µA 4.0 kΩ Current consumption (Logic) IDD1 Normal operationNote, VI = VDD or VSS, fOSC = 250 kHz 500 µA IDD2 Standby mode, VI = VDD or VSS, fOSC stopped 5 µA ILCD1 Normal operation, internal bias selected, no load 1 000 µA ILCD2 Standby mode, internal bias used, no load 5 µA Current consumption (Driver) Note Normal operation: VDD = 5 V, VLCD = 8 V Remarks TYP. values are reference values for TA = 25°C. 18 µPD16432B SWITCHING SPECIFICATIONS (UNLESS SPECIFIED OTHERWISE, TA = –40 to +85°C, VDD = VLCD = 5 V ±10%, RL = 5 kΩ Ω, CL = 150 pF) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 175 250 325 kHz Oscillator frequency fOSC R = 100 kΩ Output data delay time tPZL SCK ↓ → DATA ↓ 100 ns Output data delay time tPLZ SCK ↓ → DATA ↑ 300 ns 1.5 µs SYNC delay time tDSYNC Note The time for one frame is found as follows. 1 frame = 1/fOSC × 128 clocks × duty number + 1/fOSC × 64 clocks If fOSC = 250 kHz and duty = 1/15, 1 frame = 4 µs × 128 × 15 + 4 µs × 64 = 7.94 ms REQUIRED TIMING CONDITIONS (UNLESS SPECIFIED OTHERWISE, TA = –40 to +85°C, VDD = 5 V ±10%, VLCD = 8 V ±10%, RL = 5 kΩ Ω, CL = 150 pF) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Clock frequency fOSC OSCIN external clock 100 500 kHz High-level clock pulse width tWHC OSCIN external clock 1 5 µs Low-level clock pulse width tWLC OSCIN external clock 1 5 µs Shift-clock cycle tCYK SCK 900 ns High-level shift clock pulse width tWHK SCK 400 ns Low-level shift clock pulse width tWLK SCK 400 ns tHSTBK STB ↑ → SCK ↓ 1.5 µs Data setup time tDS DATA → SCK ↑ 100 ns Data hold time tDH SCK ↑ → DATA 200 ns STB hold time tHKSTB SCK ↑ → STB ↓ 1 µs STB hold time tWSTB 1 µs Wait time tWAIT 1 µs SYNC removal time tSREM 250 ns Standby transition time tPSTB 10 µs Reset pulse width tWRS RESET 0.1 µs Power-ON reset time tPON From Power-ON 4 CLK Shift clock hold time 8th SCK ↑ → 9th SCK ↓, in data read 19 µPD16432B OUTPUT LOAD CIRCUIT VDD 5 kΩ DATA 150 pF SWITCHING SPECIFICATION WAVEFORM DIAGRAMS 1/fC tWHC VIH OSCIN VIL tWLC VIH VIH STB VIL tHSTBK tHKSTB tCYK tWLK tWLK VIH SCK VIL tDS DATA 20 VIH VIL tDH tWSTB µPD16432B SWITCHING SPECIFICATION WAVEFORM DIAGRAMS SYNC Timing (Master) One Frame One Frame SYNC Timing (Slave) One Frame One Frame fOSC tDSYNC tSREM SYNC Internal Reset SCK VIL tPZL tPLZ DATA VOL2 RESET RESET tWRE 21 µPD16432B OUTPUT WAVEFORMS (1) 1/8 Duty (1/4 Bias: VLC2: VLC3) * Key scan period 0 COM0 VLCD VLC1 VLC2 VLC4 VLC5 COM1 VLCD VLC1 VLC2 VLC4 VLC5 COM7 VLCD VLC1 VLC2 VLC4 VLC5 SEG1 VLCD VLC1 VLC2 VLC4 VLC5 SEG2 VLCD VLC1 VLC2 VLC4 VLC5 VLCD 3/4VLCD SEG1-COM0 2/4VLCD 1/4VLCD 0 –1/4VLCD –2/4VLCD –3/4VLCD –VLCD VLCD 3/4VLCD SEG1-COM1 2/4VLCD 1/4VLCD 0 –1/4VLCD –2/4VLCD –3/4VLCD –VLCD 1 2 3 4 512 µ s 6 7 256 µ s 4.4 ms 22 5 * K 0 1 µPD16432B Enlargement of Key Scan Period 7 K 1 COM0 SEG1 SEG2 SEG8 SEG9 to SEG65 2 3 4 0 5 6 7 8 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 = Key source output 23 µPD16432B (2) 1/15 Duty (1/5 Bias) 0 COM0 1/2VLCD COM1 1/2VLCD COM14 1/2VLCD SEG1 1 2 3 4 5 6 7 8 9 10 11 12 13 * Key scan period * 14 K 1 2 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD 3/5VLCD 1/2VLCD 1/5VLCD SEG1-COM0 0 –1/5VLCD –1/2VLCD –3/5VLCD –VLCD 512 µ s 256 µ s 7.9 ms 24 µPD16432B Enlargement of Key Scan Period 14 K 1 COM0 1/2VLCD SEG1 SEG2 SEG8 SEG9 to SEG65 2 3 4 0 5 6 7 8 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 = Key source output 25 µPD16432B ACCESS PROCEDURES Access procedures are illustrated below by means of flowcharts and timing charts. 1. Initialization (1) Flowchart Start Display setting command (command 1) MSB LSB Initial state initialization 0 0 0 0 0 1 0 Status command (command 2) MSB Key scan start 1 1 0 0 1 0 1 (1/15 duty, master, internal drive) LSB 0 1 (LCD off, LED off, key scan operation) Data setting command (command 3) MSB LSB Display data RAM write 0 1 0 0 0 0 0 0 (Display data RAM, increment) Address setting command (command 4) MSB LSB Address setting 1 0 0 0 0 0 0 0 (Display data RAM: 0H) Display data All data written? NO YES Data setting command (command 5) MSB LSB Character display RAM write 0 Character data All data written? YES 26 NO 1 0 0 0 0 0 1 (Character display RAM, increment) µPD16432B Data setting command (command 6) MSB LSB LED output latch write 0 1 0 0 0 0 1 1 (LED latch, increment) LED data Status command (command 7) MSB LCD, LED on 1 1 0 0 1 1 LSB 1 0 (LCD on, LED on, key scan operation) To next processing (2) Timing chart DATA Command 1 Command 2 Command 3 Command 4 Data n-1 Data n Command 5 Data 1 Data n Command 6 Data Command 7 Data 1 SCK STB DATA SCK STB DATA SCK STB 27 µPD16432B 2. Display Data Rewrite (Address Setting) (1) Flowchart Start Display data RAM write Data setting command (command 1) MSB LSB 0 Address setting 1 0 0 1 0 0 0 (Display data RAM, address fixed) Address setting command (command 2) MSB LSB 1 0 0 0 0 1 0 1 (Display data RAM: 5H) Display data To next processing (2) Timing chart DATA SCK STB 28 Command 1 Command 2 Data µPD16432B 3. Key Data Read (1) Flowchart Start KEY REQ recognition NO KEY REQ = H? YES Data setting command (command 1) MSB LSB Key data read 0 1 0 0 0 1 0 0 (Key data) NO Wait OK? Wait time: 1 µ s YES Key data NO All data read? YES To next processing (2) Timing chart DATA Command 1 SCK Data 1 Data 2 Data 3 tWAIT STB KEY REQ DATA Data 4 SCK STB KEY REQ Cautions 1. Wait time tWAIT (1 µs) is necessary from the rise of the 8th shift clock of command 1 until the fall of the 1st shift clock of data 1. 2. KEY REQ does not become low until the key data is all “0”. (It is not synchronized with the key data reads.) 29 µPD16432B 4. CGRAM Write (1) Flowchart Start Data setting command (command 1) MSB LSB CGRAM write 0 1 0 0 0 0 1 0 (CGRAM, increment) Address setting command (command 2) MSB LSB Address setting 1 0 0 0 0 0 0 0 (CGRAM character code: 0H) CGRAM data All data written? NO YES To next processing (2) Timing chart DATA Command 1 Command 2 SCK STB DATA SCK STB 30 Data 6 Data 7 Data 1 Data 2 µPD16432B 5. Standby (Released by Status Command) (1) Flowchart Start Status command (command 1) MSB Standby 1 1 0 1 0 0 LSB 0 Status command (command 2) MSB Standby release 1 1 0 0 0 0 0 (Standby) LSB 0 0 (Standby release) NO Transition time OK? Standby transition time: 10 µ s YES Normal operation Status command (command 3) MSB 1 1 0 0 1 1 LSB 1 0 (LCD on, LED on, key scan operation) To next processing (2) Timing chart DATA Command 1 Command 2 Command 3 SCK tSTBY STB 31 µPD16432B 6. Standby (Released by KEYN) (1) Flowchart Start Status command (command 1) MSB Standby 1 1 0 1 0 0 LSB 0 0 (Standby) Key (KEYn) input → KEY REQ = H, OSC oscillation start Key request NO Transition time OK? Standby transition time: 10 µ s YES Normal operation Status command (command 2) MSB 1 1 0 0 1 1 LSB 1 0 (LCD on, LED on, key scan operation) To next processing (2) Timing chart DATA Command 1 Command 2 SCK tSTBY STB KEY REQ 32 µPD16432B PACKAGE INFORMATION (UNIT: mm) 100 PIN PLASTIC TQFP (FINE PITCH) ( 14) A B 75 76 51 50 F 100 1 G R Q S D C detail of lead end 26 25 H I M J M P K N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 16.0±0.2 INCHES 0.630±0.008 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 16.0±0.2 0.630±0.008 F G 1.0 1.0 0.039 0.039 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 0.004 P 1.0±0.1 0.039 +0.005 –0.004 Q 0.1±0.05 0.004±0.002 R 3° +7° –3° 3° +7° –3° S 1.27 MAX. 0.050 MAX. S100GC-50-9EU-1 33 µPD16432B REFERENCE DOCUMENTS 34 NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Semiconductor Device Mounting Technology Manual (C10535E) µPD16432B [MEMO] 35 µPD16432B No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5