DATA SHEET MOS INTEGRATED CIRCUIT µPD16818 MONOLITHIC DUAL H BRIDGE DRIVER CIRCUIT DESCRIPTION The µPD16818 is a monolithic dual H bridge driver IC which uses N-channel power MOS FETs in its output stage. By employing the power MOS FETs for the output stage, this driver circuit has a substantially improved saturation voltage and power consumption as compared with conventional driver circuits that use bipolar transistors. In addition, the drive current can be adjusted by an external resistor in power-saving mode. The µPD16818 is therefore ideal as the driver circuit of a 2-phase excitation, bipolar-driven stepping motor for the head actuator of an FDD. FEATURES • Compatible with 3V-/5V- supply voltage • Pin compatible with µPD16803 • Low ON resistance (sum of ON resistors of top and bottom MOS FETs) RON1= 1.2 Ω (VM = 3.0 V) RON2 = 1.0 Ω (VM = 5.0 V) • Low current consumption: IDD = 0.4 mA TYP. (VDD = 2.7 V to 3.6 V) • Stop mode function that turns OFF all output MOS FETs • Drive current can be set in power-saving mode (set by external resistor) • Compact surface mount package ORDERING INFORMATION Part Number µPD16818GS Package 20-pin plastic SOP (7.62 mm (300)) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Supply voltage Power Symbol Condition Rating Unit V Motor block VM –0.5 to +7.0 Control block VDD –0.5 to +7.0 µPD16818GS PD1 1.0Note 1 PD2 1.25Note 2 consumption Instantaneous H bridge drive current ID (pulse) PW ≤ 5 ms, Duty ≤ 40 % W ±1.0Note 2 A Input voltage VIN –0.5 to VDD + 0.5 V Operating temperature range TA 0 to 60 °C TJ (MAX) 150 °C Tstg –55 to +150 °C Operation junction temperature Storage temperature range Notes 1. IC only 2. When mounted on a glass epoxy printed circuit board (100 mm × 100 mm × 1 mm) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S11365EJ2V1DS00 (2nd edition) Date Published September 2004 N CP(K) Printed in Japan c µPD16818 RECOMMENDED OPERAING CONDITIONS Parameter Supply voltage Symbol MIN. Motor block VM Control block Rx pin connection resistance H bridge drive current (VDD = VM = 3 V)Note µPD16818GS TYP. MAX. Unit 2.7 6.0 V VDD 2.7 6.0 RX 2 kΩ IDR Charge pump capacitor capacitance 430 mA C1-C3 5 20 nF TA 0 60 °C Operating temperature Note When mounted on a glass epoxy printed circuit board (100 mm × 100 mm × 1 mm) ELECTRICAL SPECIFICATIONS (Within recommended operating conditions unless otherwise specified) VDD = VM = 4.0 V to 6.0 V Parameter Symbol Conditions MIN. MAX. Unit 1.0 µA 2.0 mA µA OFF VM pin current IM INC pin low VM = VDD = 6 V VDD pin current IDD Note 1 High-level input current IIH1 TA = 25 °C, VIN = VDD 1.0 0 ≤ TA ≤ 60 °C, VIN = VDD 2.0 (IN1, IN2, INC) Low-level input current IIL1 (IN1, IN2, INC) PS pin high-level input current PS pin low-level input voltage Input pull-up resistance IIH2 IIL2 RINU (IN1, IN2, INC) PS pin input pull-down resistance RIND 1.0 TA = 25 °C, VIN = 0 –0.15 0 ≤ TA ≤ 60 °C, VIN = 0 –0.2 TA = 25 °C, VIN = VDD 0.15 0 ≤ TA ≤ 60 °C, VIN = VDD 0.2 TA = 25 °C, VIN = 0 –1.0 0 ≤ TA ≤ 60 °C, VIN = 0 –2.0 TA = 25 °C 35 0 ≤ TA ≤ 60 °C 25 TA = 25 °C 35 0 ≤ TA ≤ 60 °C 25 75 50 65 mA mA µA kΩ 75 50 65 kΩ Control pin high-level input voltage VIH 3.0 VDD + 0.3 V Control pin low-level input voltage VIL –0.3 0.8 V 2.0 Ω ±15 % H bridge ON resistanceNote 2 RON relative accuracy RON2 VDD = VM = 5 V ∆RON Excitation direction <1>, <3> Excitation direction <2>, Charge pump circuit turn ON time tONG VDD = VM = 5 V H bridge turn ON time tONH H bridge turn OFF time tOFFH C1 = C2 = C3 = 10nF RM = 20 Ω 1.0 ±5 <4>Note 3 Notes 1. When IN1 = IN2 = INC = “H”, PS = “L” 2. Sum of ON resistances of top and bottom MOS FETs 3. For the excitation direction, refer to FUNCTION TABLE. 2 TYP. Data Sheet S11365EJ2V1DS 0.3 2.0 ms 2.0 µs 5.0 µs µPD16818 ELECTRICAL SPECIFICATIONS (Within recommended operating conditions unless otherwise specified) VDD = VM = 2.7 V to 3.6 V Parameter Symbol Conditions MIN. TYP. MAX. Unit 1.0 µA 1.0 mA µA OFF VM pin current IM INC pin low VM = VDD = 3.6 V VDD pin current IDD Note 1 High-level input current IIH1 TA = 25 °C, VIN = VDD 1.0 0 ≤ TA ≤ 60 °C, VIN = VDD 2.0 (IN1, IN2, INC) Low-level input current IIL1 (IN1, IN2, INC) PS pin high-level input current PS pin low-level input voltage Input pull-up resistance IIH2 IIL2 RINU (IN1, IN2, INC) PS pin input pull-down resistance RIND 0.4 TA = 25 °C, VIN = 0 –0.09 0 ≤ TA ≤ 60 °C, VIN = 0 –0.12 TA = 25 °C, VIN = VDD 0.09 0 ≤ TA ≤ 60 °C, VIN = VDD 0.12 TA = 25 °C, VIN = 0 –1.0 0 ≤ TA ≤ 60 °C, VIN = 0 –2.0 TA = 25 °C 35 0 ≤ TA ≤ 60 °C 25 TA = 25 °C 35 0 ≤ TA ≤ 60 °C 25 75 50 65 mA mA µA kΩ 75 50 65 kΩ Control pin high-level input voltage VIH 2.0 VDD + 0.3 V Control pin low-level input voltage VIL –0.3 0.8 V 2.4 Ω ±15 % H bridge ON resistanceNote 2 RON relative accuracy RON1 VDD = VM = 3 V ∆RON Excitation direction <1>, <3> Excitation direction <2>, Vx voltage in power-saving modeNote 4 Vx relative accuracy in power- VX ∆V X saving mode 1.2 ±5 <4>Note 3 VDD = VM = 3 V RX = 270 kΩ 1.4 V Excitation direction <1>, <3> ±5 % Excitation direction <2>, <4> ±5 Charge pump circuit turn ON time tONG VDD = VM = 3 V H bridge turn ON time tONH H bridge turn OFF time tOFFH 1.0 1.2 0.3 2.0 ms C1 = C2 = C3 = 10nF 2.0 µs RM = 20 Ω 5.0 µs Notes 1. When IN1 = IN2 = INC = “H”, PS = “L” 2. Sum of ON resistances of top and bottom MOS FETs 3. For the excitation direction, refer to FUNCTION TABLE. 4. Vx is a voltage at point A (FORWARD) or B (REVERSE) of the H bridge in FUNCTION TABLE. Data Sheet S11365EJ2V1DS 3 µPD16818 PIN CONFIGURATION (Top View) 20-pin plastic SOP (7.62 mm (300)) C1H 1 20 C1L C2L 2 19 C2H VM1 3 18 VG 1A 4 17 1B PGND 5 16 PGND 2A 6 15 2B VDD 7 14 VM2 IN1 8 13 RX IN2 9 12 PS INC 10 11 DGND FUNCTION TABLE Excitation Direction INC IN1 IN2 H1 H2 <1> H H H F F <2> H L H R F <3> H L L R R <4> H H L F R – L × × H 1F <4> <1> H2R H2F Stop <3> F: FORWARD <2> H1R R: REVERSE FORWARD REVERSE STOP VM VM VM ON OFF A OFF 4 OFF B ON A ON ON OFF B OFF A OFF Data Sheet S11365EJ2V1DS OFF B OFF µPD16818 BLOCK DIAGRAM 0.01 µ F VDD C1L OSC CIRCUIT 0.01 µ F C1H C2L C2H 0.01 µ F VG VM CHARGE PUMP VM1 RX LEVEL CONTROL CIRCUIT BAND GAP REFERENCE 1A “H” BRIDGE 1 INC 50 kΩ 50 kΩ IN1 IN2 50 kΩ PS 50 kΩ Note SWITCH CIRCUIT 1B PGND VM2 CONTROL CIRCUIT LEVEL SHIFT 2A “H” BRIDGE 2 2B DGND PGND Note The power-saving mode is set when the PS pin goes high. In this mode, the voltage of the charge pump circuit is lowered and the ON resistance of the H bridge driver transistor increases, limiting the current. Remark is connected in diffusion layer. Data Sheet S11365EJ2V1DS 5 µPD16818 CHARACTERISTIC CURVES IDD vs. TA Characteristics IDD vs. TA Characteristics 0.3 2 VDD = 6 V Supply current IDD (mA) Supply current IDD (mA) VDD = 3.6 V 0.2 0.1 0 –20 0 20 40 60 Ambient temperature TA (°C) 1.5 1 0.5 0 –20 80 IIHL1 vs. VDD Characteristics 0 20 40 60 Ambient temperature TA (°C) IIHL1 vs. VDD Characteristics –0.1 –0.2 IN1, IN2, and INC pins Input current IIH1, IIL1 (mA) Input current IIH1, IIL1 (mA) IN1, IN2, and INC pins –0.08 IIL1 –0.06 –0.04 –0.02 IIH1 0 6 80 2.8 3 3.2 3.4 Supply voltage VDD (V) 3.6 –0.15 IIL1 –0.1 –0.05 0 IIH1 4 5 Supply voltage VDD (V) Data Sheet S11365EJ2V1DS 6 µPD16818 IIHL1 vs. TA Characteristics IIHL1 vs. TA Characteristics –0.2 IN1, IN2, and INC pins VIN = VDD = 3 V –0.08 –0.06 Input current IIH1, IIL1 (mA) Input current IIH1, IIL1 (mA) –0.1 IIL1 –0.04 –0.02 IN1, IN2, and INC pins VIN = VDD = 5 V –0.15 –0.1 IIL1 –0.05 IIH1 IIH1 0 –20 0 20 40 60 Ambient temperature TA (°C) 0 –20 80 IIHL2 vs. VDD Characteristics 40 60 80 IIHL2 vs. VDD Characteristics 0.2 PS pin VIN = 0 0.08 Input current IIH2, IIL2 (mA) Input current IIH2, IIL2 (mA) 20 Ambient temperature TA (°C) 0.1 IIH2 0.06 0.04 0.02 0 0 2.8 IIL2 3 3.2 3.4 Supply voltage VDD (V) PS pin VIN = 0 0.15 IIH2 0.1 0.05 3.6 Data Sheet S11365EJ2V1DS 0 IIL2 4 5 6 Supply voltage VDD (V) 7 µPD16818 IIHL2 vs. TA Characteristics IIHL2 vs. TA Characteristics 0.2 PS pin VIN = 0 VDD = 3 V 0.08 0.06 Input current IIH2, IIL2 (mA) Input current IIH2, IIL2 (mA) 0.1 IIH2 0.04 0.02 PS pin VIN = 0 VDD = 5 V 0.15 0.1 IIH2 0.05 IIL2 0 –20 0 20 40 60 Ambient temperature TA (°C) IIL2 0 –20 80 VIHL vs. VDD Characteristics 80 VIHL vs. VDD Characteristics Input voltage VIH, VIL (V) Input voltage VIHL (V) 8 20 40 60 Ambient temperature TA (°C) 3 2 1.5 1 0.5 0 0 2.8 3 3.2 3.4 Supply voltage VDD (V) 3.6 VIH 2.5 VIL 2 1.5 1 4 5 Supply voltage VDD (V) Data Sheet S11365EJ2V1DS 6 µPD16818 VIHL vs. TA Characteristics VIHL vs. TA Characteristics 2 3 VDD = 5 V Input voltage VIH, VIL (V) Input voltage VIHL (V) VDD = 3 V 1.5 1 0.5 0 –20 0 20 40 60 Ambient temperature TA (°C) 2.5 VIH 2 VIL 1.5 1 –20 80 0 RON vs. TA Characteristics 2 H bridge ON resistance RON (Ω ) H bridge ON resistance RON (Ω ) 80 RON vs. TA Characteristics 2 VDD = VM = 3 V RM = 20 Ω 1.5 1 0.5 0 –20 20 40 60 Ambient temperature TA (°C) 0 20 40 60 Ambient temperature TA (°C) VDD = VM = 5 V RM = 12 Ω 1.5 1 0.5 80 Data Sheet S11365EJ2V1DS 0 –20 0 20 40 60 Ambient temperature TA (°C) 80 9 µPD16818 tONG vs. TA Characteristics Charge pump turn ON time tONG (ms) Charge pump turn ON time tONG (ms) tONG vs. TA Characteristics 1 VDD = VM = 3 V RM = 12 Ω 0.8 0.6 0.4 0.2 0 –20 0 20 40 60 Ambient temperature TA (°C) 80 1 VDD = VM = 5 V RM = 20 Ω 0.8 0.6 0.4 0.2 0 –20 0 10 2 tONH VDD = VM = 3 V RM = 12 V 1.5 1 0.5 tOFFH 0 –20 0 20 40 60 Ambient temperature TA (°C) 80 tONH, tOFFH vs. TA Characteristics H bridge switching time tONH, tOFFH ( µ s) H bridge switching time tONH, tOFFH ( µ s) tONH, tOFFH vs. TA Characteristics 20 40 60 Ambient temperature TA (°C) 80 1 0.8 VDD = VM = 5 V RM = 20 Ω tONH 0.6 0.4 0.2 tOFFH 0 –20 Data Sheet S11365EJ2V1DS 0 20 40 60 Ambient temperature TA (°C) 80 µPD16818 Vx vs. Rx Characteristics VDD = VM = 3.3 V RM = 12 Ω 2 1 0 100 200 300 400 Power-saving setting resistance Rx (kΩ) 500 Vx voltage in power-saving mode Vx (V) Vx voltage in power-saving mode Vx (V) Vx vs. Rx Characteristics 3 4 VDD = VM = 5 V RM = 12 Ω 3 2 1 0 100 200 300 400 Power-saving setting resistance Rx (kΩ) 500 PD vs. TA Characteristics ( µPD16818GS) 1.4 Average power consumption PD (W) When mounted on a printed circuit board 1.2 IC only 1.0 0.8 0.6 0.4 0.2 0 20 40 60 80 Ambient temperature TA (°C) 100 Data Sheet S11365EJ2V1DS 11 µPD16818 PACKAGE DRAWING 20-PIN PLASTIC SOP (7.62 mm (300)) 20 11 detail of lead end P 1 10 A H I G J S L B C D M M N K S E F NOTE ITEM Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. A MILLIMETERS 12.7±0.3 B 0.78 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.1±0.1 F 1.8 MAX. G 1.55±0.05 H 7.7±0.3 I 5.6±0.2 J 1.1 K 0.22 +0.08 −0.07 L M 0.6±0.2 0.12 N 0.10 P 3° +7° −3° P20GM-50-300B, C-7 12 Data Sheet S11365EJ2V1DS µPD16818 RECOMMENDED SOLDERING CONDITIONS The µPD16818 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Surface Mount Type µPD16818GS Soldering Method 20-pin plastic SOP (7.62 mm (300)) Soldering Conditions Symbol of Recommended Soldering Infrared reflow Package peak temperature: 235°C, Time: 30 seconds MAX.(210°C MIN.), Number of times: 3 MAX., Number of days: NoneNote, Flux: Rosin-based flux with little chlorine component (chlorine: 0.2 Wt% MAX.) IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds MAX.(200°C MIN.), Number of times: 3 MAX., Number of days: NoneNote, Flux: Rosin-based flux with little chlorine component (chlorine: 0.2 Wt% MAX.) VP15-00-3 Wave soldering Package peak temperature: 260°C, Time: 10 seconds MAX., Preheating temperature: 120 °C MAX., Number of times: 1, Flux: Rosin-based flux with little chlorine component (chlorine: 0.2 Wt% MAX.) WS60-00-1 Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25 °C, 65 % RH MAX. Caution Do not use two or more soldering methods in combination. Data Sheet S11365EJ2V1DS 13 µPD16818 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. 14 Data Sheet S11365EJ2V1DS µPD16818 • The information in this document is current as of September, 2004. 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