NEC UPD30121F1-168-GA1

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30121
TM
VR4121
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30121 (VR4121) is one of NEC’s VR SeriesTM RISC (Reduced Instruction Set Computer) microprocessors
and is a high-performance 64-/32-bit microprocessor employing the MIPS TM RISC architecture.
The VR4121 uses the high-performance, super power-saving VR4120TM as the CPU core, and has many peripheral
functions such as a DMA controller, software modem interface, serial interface, keyboard interface, IrDA interface,
touch panel interface, real-time clock, A/D converter, and D/A converter. Configured with these functions, the
VR4121 is suitable for high-speed battery-driven portable information systems. The external memory bus width can
be selected from 32 bits and 16 bits, realizing high-speed data transfer.
Detailed function descriptions are provided in the following user’s manual. Be sure to read it before
designing.
• VR4121 User’s Manual (U13569E)
FEATURES
• Employs 64-bit MIPS architecture
• Conforms to MIPS III instruction set (deleting FPU,
LL, LLD, SC, and SCD instructions)
• Optimized 6-stage pipeline
• Supports MIPS16 instruction set
• Supports high-speed product-sum operation
instructions
• Supports four types of operating modes, enabling
more effective power-consumption management
• Internal maximum operating frequency: 131/168 MHz
• On-chip clock generator
• Address space physical: 32 bits
virtual:
40 bits
Integrates 32 double entry TLBs
• High-capacity instruction/data separated cache
memories
Instruction: 16 Kbytes
Data:
8 Kbytes
• Memory controller (ROM, EDO-type DRAM,
synchronous DRAM (SDRAM), synchronous ROM
(SROM), and flash memory supported)
• Keyboard interface and touch panel interface
• 4-channel DMA controller
• Serial interface (NS16550 compatible)
• IrDA interface for infrared communication
• Software modem interface
• A/D and D/A converters to support digital voice I/O
• Supports ISA bus subset
• Power supply voltage: VDD2 = 2.5 V (internal), VDD3 =
3.3 V (external) (131 MHz model)
• Package: 224-pin fine-pitch FBGA
APPLICATIONS
• Battery-driven portable information systems
• Embedded controllers, etc.
ORDERING INFORMATION
Part Number
Package
Internal Maximum Operating Frequency
µPD30121F1-131-GA1
224-pin plastic FBGA (16 × 16)
131 MHz
µPD30121F1-168-GA1
224-pin plastic FBGA (16 × 16)
168 MHz
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14691EJ1V0DS00 (1st edition)
Date Published June 2000 N CP(K)
Printed in Japan
©
2000
µPD30121
PIN CONFIGURATION
• 224-pin plastic FBGA (16 × 16)
µPD30121F1-131-GA1
µPD30121F1-168-GA1
Bottom view
Top view
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V U T R P N M L K J H G F E D C B A
2
A B C D E F G H J K L M N P R T U V
Index mark
Data Sheet U14691EJ1V0DS00
µPD30121
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
Power
Supply
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Pin Name
VDD3
SHB#
BUSCLK
HLDACK#
IOCHRDY
MEMW#
ADD23
VDD3
ADD18
ADD15
ADD8
ADD7
VDD2
DCD#/GPIO15
TXD/CLKSEL2
IRDOUT#
IRING
VDD3
DATA1
IOR#
IOW#
LEDOUT#
FIRCLK
HLDRQ#
ZWS#
ADD24
ADD21
ADD12
ADD6
GND2
DSR#
IRDIN
FIRDIN#/SEL
BATTINH/BATTINT#
OFFHOOK
MUTE
DATA2
DATA0
SMODE2
CKE
GND3
IOCS16#
MEMR#
ADD22
ADD20
ADD17
ADD13
ADD5
RXD
DTR#/CLKSEL0
Pin No.
C15
C16
C17
C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
E1
E2
E3
E4
E15
E16
E17
E18
F1
F2
F3
F4
F15
F16
F17
F18
G1
G2
G3
G4
G15
G16
G17
G18
H1
H2
H3
H4
Power
Supply
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
Pin Name
RTS#/CLKSEL1
GND3
ILCSENSE
AFERST#
DATA5
DATA3
DATA6
GND3
MEMCS16#
ADD25/SCLK
GND3
ADD19
ADD16
ADD14
VDD3
GND3
ADD4
CTS#
GND3
GND3
SDI
SDO
DATA9
DATA4
DATA7
DATA10
OPD#
HSPSCLK
FS
HC0
DATA13
DATA8
DATA11
DATA14
KPORT3
HSPMCLK
TELCON
KPORT1
VDD2
DATA12
DATA15
GND3
KPORT7
KPORT2
KPORT0
KPORT5
DATA16/GPIO16
GND2
DATA18/GPIO18
VDD3
Pin No.
H15
H16
H17
H18
J1
J2
J3
J4
J15
J16
J17
J18
K1
K2
K3
K4
K15
K16
K17
K18
L1
L2
L3
L4
L15
L16
L17
L18
M1
M2
M3
M4
M15
M16
M17
M18
N1
N2
N3
N4
N15
N16
N17
N18
P1
P2
P3
P4
P15
P16
Power
Supply
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
Pin Name
GND3
KPORT6
KPORT4
VDD2
DATA20/GPIO20
DATA17/GPlO17
DATA22/GPlO22
DATA19/GPIO19
KSCAN9/GPIO41
VDD3
GND2
KSCAN11/GPIO43
DATA23/GPIO23
DATA26/GPIO26
DATA25/GPIO25
DATA21/GPIO21
KSCAN7/GPIO39
KSCAN10/GPIO42
KSCAN5/GPIO37
KSCAN8/GPIO40
DATA27/GPIO27
DATA31/GPIO31
DATA29/GPIO29
DATA24/GPIO24
KSCAN3/GPIO35
KSCAN6/GPIO38
KSCAN0/GPIO32
KSCAN4/GPIO36
DATA30/GPIO30
VDD3
GND3
DATA28/GPIO28
KSCAN2/GPIO34
MIPS16EN
GND3
KSCAN1/GPIO33
VDD2
ADD3
ADD10
GND2
GND3
VDD3
VDDP
GND3
ADD9
ADD0
ADD2
ADD11
VDD2 (VDDPD)
GNDP
Remark # indicates active low.
Data Sheet U14691EJ1V0DS00
3
µPD30121
Pin No.
P17
P18
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
T2
T3
T4
T5
Power
Supply
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Pin Name
CLKX2
GND2 (GNDPD)
ADD1
POWER
GND3
GND3
AUDIOIN
DVDD
MRAS2#/ULCAS#
MRAS1#
ROMCS1#
RSTOUT
GND3
SMODE1/GPIO49
DDIN/GPIO45
GPIO12
GND3
CVDD
RTCX2
CLKX1
POWERON
RSTSW#
GND3
PIUVDD
ADIN0
Pin No.
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
Power
Supply
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Pin Name
AVDD
LCAS#
ROMCS2#
RD#
WR#
DBUS32/GPIO48
DDOUT/GPIO44
GPIO11
GPIO8
GND3
GND3
GPIO0
RTCX1
MPOWER
RTCRST#
AGND
TPX1
TPY0
ADIN1
DGND
UCAS#
ROMCS3#
LDCRDY
DRTS#/GPIO46
GPIO13
Remark # indicates active low.
4
Data Sheet U14691EJ1V0DS00
Pin No.
U13
U14
U15
U16
U17
U18
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
Power
Supply
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Pin Name
GPIO9
SYSDIR/GPIO6
SCAS#/GPIO5
GPIO1
GPIO2
CGND
VDD3
PIUGND
TPX0
TPY1
ADIN2
AUDIOOUT
MRAS3#/UUCAS#
MRAS0#
ROMCS0#
VDD3
LCDCS#
DCTS#/GPIO47
GPIO14
GPIO10
SPOWER/GPIO7
SRAS#/GPIO4
GPIO3
VDD3
µPD30121
PIN IDENTIFICATION
ADD (0:25):
ADIN (0:2):
AFERST#:
AGND:
AUDIOIN:
AUDIOOUT:
AVDD:
BATTINH:
BATTINT#:
BUSCLK:
CGND:
CKE:
CLKSEL (0:2):
CLKX1:
CLKX2:
CTS#:
CVDD:
DATA (0:31):
DBUS32:
DCD#:
DCTS#:
DDIN:
DDOUT:
DGND:
DRTS#:
DSR#:
DTR#:
DVDD:
FIRCLK:
FIRDIN#:
FS:
GND2, GND3:
GNDP, GNDPD:
GPIO (0:49):
HC0:
HLDACK#:
HLDRQ#:
HSPMCLK:
HSPSCLK:
ILCSENSE:
IOCHRDY:
IOCS16#:
IOR#:
IOW#:
IRDIN:
IRDOUT#:
IRING:
KPORT (0:7):
KSCAN (0:11):
LCAS#:
Address Bus
General Purpose Input for A/D
AFE Reset
GND for A/D
Audio Input
Audio Output
VDD for A/D
Battery Inhibit
Battery Interrupt Request
System Bus Clock
GND for Oscillator
Clock Enable
Clock Select
Clock X1
Clock X2
Clear to Send
VDD for Oscillator
Data Bus
Data Bus 32
Data Carrier Detect
Debug Serial Clear to Send
Debug Serial Data Input
Debug Serial Data Output
GND for D/A
Debug Serial Request to Send
Data Set Ready
Data Terminal Ready
VDD for D/A
FIR Clock
FIR Data Input
Frame Synchronization
Ground
Ground for PLL
General Purpose I/O
Hardware Control 0
Hold Acknowledge
Hold Request
HSP Codec Master Clock
HSP Codec Serial Clock
Input Loop Current Sensing
I/O Channel Ready
I/O Chip Select 16
I/O Read
I/O Write
IrDA Data Input
IrDA Data Output
Input Ring
Key Code Data Input
Key Scan Line
Lower Column Address Strobe
LCDCS#:
LCDRDY:
LEDOUT#:
MEMCS16#:
MEMR#:
MEMW#:
MIPS16EN:
MPOWER:
MRAS(0:3)#:
MUTE:
OFFHOOK:
OPD#:
PIUGND:
PIUVDD:
POWER:
POWERON:
RD#:
ROMCS(0:3)#:
RSTOUT:
RSTSW#:
RTCRST#:
RTCX1:
RTCX2:
RTS#:
RxD:
SCAS#:
SCLK:
SDI:
SDO:
SEL:
SHB#:
SMODE (1:2):
SPOWER:
SRAS#:
SYSDIR:
TELCON:
TPX (0:1):
TPY (0:1):
TxD:
UCAS#:
ULCAS#:
UUCAS#:
VDD2, VDD3:
VDDP, VDDPD:
WR#:
ZWS#:
LCD Chip Select
LCD Ready
LED Output
Memory Chip Select 16
Memory Read
Memory Write
MIPS16 Enable
Main Power
DRAM Row Address Strobe
Mute
Off Hook
Output Power Down
GND for Touch Panel Interface
VDD for Touch Panel Interface
Power Switch
Power On State
Read
ROM Chip Select
System Bus Reset Output
Reset Switch
Real-time Clock Reset
Real-time Clock X1
Real-time Clock X2
Request to Send
Receive Data
Column Address Strobe for
SDRAM/SROM
SDRAM/SROM Clock
HSP Serial Data Input
HSP Serial Data Output
IrDA Module Select
System Hi-Byte Enable
SDRAM Mode
SDRAM Power Control
Row Address Strobe for
SDRAM/SROM
System Bus Buffer Direction
Telephone Control
Touch Panel X I/O
Touch Panel Y I/O
Transmit Data
Upper Column Address Strobe
Lower Byte of Upper Column
Address Strobe
Upper Byte of Upper Column
Address Strobe
Power Supply Voltage
VDD for PLL
Write
Zero Wait State
Remark # indicates active low.
Data Sheet U14691EJ1V0DS00
5
µPD30121
INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS
32.768 kHz 18.432 MHz
CODEC
OSB
OSB
PLL
GIU
HSP
LCD module
LCD panel
480 × 240
KIU
RTC
µPD16666
µ PD16661
AFE
LED
DSU
VR4120 CPU core
131/168 MHz
PC card
PCMCIA
/buffer
AIU
ICU
D/A
PMU
PIU
ROM/SROM/flash
memory
Touch panel
CMU
A/D
DCU
EDO DRAM/
SDRAM
BCU
SIU
DMAAU
FIR
VR4121
RS-232C
driver
IR
driver
48 MHz
CPU CORE INTERNAL BLOCK DIAGRAM
Virtual address bus
Internal data
bus
Control (o)
Control (i)
Bus
interface
Data
cache
(8 Kbytes)
Instruction
cache
(16 Kbytes)
Address/data (o)
TLB
Address/data (i)
Clock
generator
Internal clock
6
CP0
Data Sheet U14691EJ1V0DS00
CPU
µPD30121
CONTENTS
1.
PIN FUNCTIONS.................................................................................................................................. 8
1.1
Pin Functions .............................................................................................................................................8
1.2
Pin Status in Specific Status...................................................................................................................17
1.3
Recommended Connection and I/O Circuit Types................................................................................21
1.4
Pin I/O Circuits .........................................................................................................................................24
2.
ELECTRICAL SPECIFICATIONS...................................................................................................... 25
3.
PACKAGE DRAWING ....................................................................................................................... 71
4.
RECOMMENDED SOLERING CONDITIONS .................................................................................. 72
Data Sheet U14691EJ1V0DS00
7
µPD30121
1. PIN FUNCTIONS
Remark # indicates active low.
1.1 Pin Functions
(1) System bus interface signals
(1/3)
Signal
ADD25/SCLK
I/O
O
Function
This function differs depending on how the SMODE (1:2) signal is set.
<When SMODE (1:2) signal = 00>
This is a 25-bit address bus.
<When SMODE (1:2) signal ≠ 00>
This is the operating clock for SDRAM and SROM.
ADD (0:24)
O
This is a 25-bit address bus. The VR4121 uses this to specify addresses for the SDRAM, SROM,
DRAM, ROM, LCD, or system bus (ISA).
DATA (0:15)
I/O
This is a 16-bit data bus. The VR4121 uses this to transmit and receive data with a SDRAM, SROM,
DRAM, ROM, LCD, or system bus.
DATA (16:31)/
GPIO (16:31)
I/O
This function differs depending on how the DBUS32 signal is set.
<When DBUS32 signal = 1>
This is the high-order 16 bits of the 32-bit data bus.
This bus is used for transmitting and receiving data between the VR4121 and the DRAM and ROM.
<When DBUS32 signal = 0>
This is a general-purpose I/O port.
LCDCS#
O
This is the LCD chip select signal. This signal is active when the VR4121 is performing LCD access and
high-speed system bus access using the ADD/DATA bus.
RD#
O
This is active when the VR4121 is reading data from the LCD, SDRAM, SROM, DRAM, or ROM.
WR#
O
This is active when the VR4121 is writing data to the LCD, SDRAM, or DRAM.
LCDRDY
I
This is the LCD ready signal. Set this signal as active when the LCD controller is ready to receive
access from the VR4121.
ROMCS (2:3)#
O
The function differs with the setting of the DBUS32 signal.
<When DBUS32 signal = 1>
This becomes the chip select signal for the extended ROM, SROM, DRAM, or SDRAM.
<When DBUS32 signal = 0>
This is the ROM or SROM chip select signal.
ROMCS (0:1)#
O
This is the ROM or SROM chip select signal.
CKE
O
This is the SDRAM or SROM clock enable signal. When using neither SDRAM nor SROM, connect to
GND or leave open.
UUCAS#/
MRAS3#
O
This function differs depending on how the DBUS32 signal is set or types of memory to be accessed.
<When DBUS32 signal = 1>
When accessing DRAM (EDO type): This signal is active (UUCAS#) when a valid column address is
output via the ADD bus during access of DATA (24:31) in the 32-bit data bus.
When accessing SDRAM: This is the I/O buffer control signal (UUDQM#) that is used during access
of DATA (24:31) signal in the 32 bit data bus.
During 32-bit access of LCD/high-speed system memory: Byte enable signal that is used during
access of DATA (24:31) signal.
<When DBUS32 signal = 0>
When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS3#). This signal is
active when a valid row address is output via the ADD bus for the DRAM connected to the high-order
address.
When accessing SDRAM: This is the SDRAM's chip select signal (CS3#). This signal is active when
a command is issued for the SDRAM connected to the high-order address.
8
Data Sheet U14691EJ1V0DS00
µPD30121
(2/3)
Signal
ULCAS#/
MRAS2#
I/O
O
Function
This function differs depending on how the DBUS32 signal is set and type of memory being accessed.
<When DBUS32 signal = 1>
When accessing DRAM (EDO type): This signal is active (ULCAS#) when a valid column address is
output via the ADD bus during access of DATA (16:23) signal in the 32-bit data bus.
When accessing SRAM: This is the I/O buffer control signal (ULDQM#) that is used during access of
DATA (16:23) signal in the 32-bit data bus.
During 32-bit access of LCD/high-speed system memory: Byte enable signal that is used during
access of DATA (16:23) signal.
<When DBUS32 signal = 0>
When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS2#). This signal is
active when a valid row address is output via the ADD bus for the DRAM connected to the next
highest address after the highest high-order address.
When accessing SDRAM: This is the SDRAM's chip select signal (CS2#). This signal is active when
a command is issued for the SDRAM connected to the second highest high-order address.
MRAS (0:1)#
O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is the DRAM's RAS-only signal.
<When accessing SDRAM>
This is the SDRAM's chip select signal (CS (0:1)#).
UCAS#
O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is the DRAM's CAS signal. This signal is active when a valid column address is output via the
ADD bus during access of DATA (8:15) signal in the DRAM.
<When accessing SDRAM>
This is the I/O buffer control signal (UDQM#) that is used during access of DATA (8:15) signal.
< During 32-bit access of LCD/high-speed system memory >
This is the byte enable signal that is used during access of DATA (8:15) signal. This signal is active
when a valid address is output via the ADD bus for access to DATA (8:15) signal when the size of
the access bus to the LCD is 32 bits.
LCAS#
O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is the DRAM's CAS signal. This signal is active when a valid column address is output via the
ADD bus during access of DATA (0:7) signal in the DRAM.
<When accessing SDRAM>
This is the I/O buffer control signal (LDQM#) that is used during access of DATA (0:7) signal.
< During 32-bit access of LCD/high-speed system memory >
This is the byte enable signal that is used during access of DATA (0:7) signal.
BUSCLK
O
This is the system bus clock. It is used to output the clock that is supplied to the controller on the
system bus. Its frequency is determined based on the status of the CLKSEL (0:2) signal. Ordinarily,
the frequency is 1/4 of the TClock frequency. (See (5) RS-232C interface signals). The frequency
can be changed via the PMU register settings.
SHB#
O
This is the system bus high-byte enable signal. During 16-bit system bus access, this signal is active
when the high-order byte is valid on the data bus.
IOR#
O
This is the system bus I/O read signal. It is active when the VR4121 accesses the system bus to read
data from an I/O port.
IOW#
O
This is the system bus I/O write signal. It is active when the VR4121 accesses the system bus to write
data to an I/O port.
MEMR#
O
This is the system bus memory read signal. It is active when the VR4121 accesses the system bus to
read data from memory.
MEMW#
O
This is the system bus memory write signal. It is active when the VR4121 accesses the system bus to
write data to memory.
ZWS#
I
This is the system bus zero wait state signal. Set this signal as active to enable the controller on the
system bus to be accessed by the VR4121 without a wait interval.
Data Sheet U14691EJ1V0DS00
9
µPD30121
(3/3)
Signal
I/O
Function
RSTOUT
O
This is the system bus reset signal. It is active when the VR4121 resets the system bus controller
(during bus timeout, manipulation of BCUCNTREG1 register, and power-down mode).
MEMCS16#
I
This is a dynamic bus sizing request signal. Set this signal as active when system bus memory
accesses data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed
system bus.
IOCS16#
I
This is a dynamic bus sizing request signal. Set this signal as active when system bus I/O accesses
data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed system
bus.
IOCHRDY
I
This is the system bus ready signal. Set this signal as active when the system bus controller is ready to
be accessed by the VR4121.
HLDRQ#
I
This is a hold request signal for the system bus and DRAM bus that is sent from an external bus master.
HLDACK#
O
This is a hold acknowledge signal for the system bus and DRAM bus that is sent to an external bus
master.
SRAS#/GPIO4
I/O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the RAS signal for SDRAM and SROM only.
SCAS#/GPIO5
I/O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the CAS signal for SDRAM and SROM only.
SYSDIR/GPIO6
I/O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the direction control signal for the buffer used to reduce the DATA bus's load.
SPOWER/
GPIO7
I/O
This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the SDRAM's power supply control signal.
(2) Clock interface signals
Signal
I/O
Function
RTCX1
I
This is the 32.768-kHz oscillator’s input pin. It is connected to one side of a crystal resonator.
RTCX2
O
This is the 32.768-kHz oscillator’s output pin. It is connected to one side of a crystal resonator.
CLKX1
I
This is the 18.432-MHz oscillator’s input pin. It is connected to one side of a crystal resonator.
CLKX2
O
This is the 18.432-MHz oscillator’s output pin. It is connected to one side of a crystal resonator.
FIRCLK
I
This is the 48-MHz clock input pin. Fix this at high level when FIR is not used.
10
Data Sheet U14691EJ1V0DS00
µPD30121
(3) Battery monitor interface signals
Signal
BATTINH/
BATTINT#
I/O
I
Function
This function differs depending on how the MPOWER signal is set.
<When MPOWER signal = 0>
BATTINH function
This signal enables/prohibits activation due to power-on.
1 : Enable activation
0 : Prohibit activation
<When MPOWER signal = 1>
BATTINT# function
This is an interrupt signal that is output when remaining power is low during normal operations. The
external agent checks the remaining battery power. Activate the signal at this pin if voltage sufficient
for operations cannot be supplied.
(4) Initialization interface signals
Signal
I/O
Function
MPOWER
O
This signal indicates the VR4121 is operating. This signal is inactive during Hibernate mode.
POWERON
O
This signal indicates the VR4121 is ready to operate. It becomes active when a power-on factor is
detected and becomes inactive when the BATTINH/BATTINT# signal check operation is completed.
POWER
I
This is a VR4121 activation signal.
RSTSW#
I
This is a VR4121 reset signal.
RTCRST#
I
This signal resets RTC. When power is first supplied to a device, the external agent must assert the
signal at this pin for about 2 s.
Data Sheet U14691EJ1V0DS00
11
µPD30121
(5) RS-232C interface signals
Signal
I/O
Function
RxD
I
This is a receive data signal. It is used when the RS-232C controller sends serial data to the VR4121.
CTS#
I
This is a transmit enable signal. Assert this signal when the RS-232C controller is ready to receive
transmission of serial data.
DCD#/
GPIO15
I
This is a carrier detection signal. Assert this signal when valid serial data is being received. It is also
used when detecting a power-on factor for the VR4121.
When this pin is not used for DCD# signal, this pin can be used as an interrupt detection function for the
GIU unit.
DSR#
I
This is the data set ready signal. Assert this signal when the RS-232C controller is ready to
receive/transmit serial data between the controller and the VR4121.
TxD/
CLKSEL2,
RTS#/
CLKSEL1,
DTR#/
CLKSEL0
I/O
This function differs depending on the operating status.
<During normal operation (output)>
Signals used for serial communication
TxD signal :
This is a transmit data signal. It is used when the VR4121 sends serial data to the RS-232C
controller.
RTS# signal :
This is a transmit request signal. This signal is asserted when the VR4121 is ready to receive serial
data from the RS-232C controller.
DTR# signal :
This is a terminal equipment ready signal. This signal is asserted when the VR4121 is ready to
transmit or receive serial data.
<When RTC reset (input)>
Signals (CLKSEL (2:0) signal) used to set the CPU core operation frequency, BUSCLK signal
frequency, and internal bus clock frequency. These signals are sampled when the RTCRST# signal
changes from low level to high level.
The relationships between the CLKSEL (2:0) signal setting and each clock frequency are shown below.
CLKSEL
(2:0)
signal
SDRAM/SROM
CPU core
operation
frequency
operation frequency
(VTClock)
(PClock)
MIN.
MAX.
BUSCLK
signal
frequency
BUSCLK
signal
requency
(When
TClock
output)
(When 1/4
of TClock)
Interrupt
control
clock
frequency
(MasterOut)
Note 1
RFU
RFU
RFU
RFU
RFU
RFU
Note 2
168.5 MHz
28.1 MHz
56.2 MHz
28.1 MHz
7.0 MHz
7.0 MHz
Note 2
147.5 MHz
29.5 MHz
59.0 MHz
29.5 MHz
7.4 MHz
7.4 MHz
100
131.1 MHz
32.8 MHz
65.5 MHz
32.8 MHz
8.2 MHz
8.2 MHz
011
118.0 MHz
29.5 MHz
59.0 MHz
29.5 MHz
7.4 MHz
7.4 MHz
010
98.3 MHz
32.8 MHz
65.5 MHz
32.8 MHz
8.2 MHz
8.2 MHz
001
90.7 MHz
30.2 MHz
60.5 MHz
30.2 MHz
7.6 MHz
7.6 MHz
000
78.6 MHz
26.2 MHz
52.4 MHz
26.2 MHz
6.6 MHz
6.6 MHz
111
110
101
Notes 1. Do not set CLKSEL (2:0) = 111.
2. The settings CLKSEL (2:0) = 110 and 101 are only guaranteed for the 168 MHz model. Do not apply
these settings to the 131 MHz model.
12
Data Sheet U14691EJ1V0DS00
µPD30121
(6) IrDA interface signals
Signal
IRDIN
FIRDIN#/SEL
I/O
I
I/O
Function
This is an IrDA serial data input signal. It is used when the VR4121 sends serial data to the IrDA
controller, for both FIR and SIR. If the IrDA controller used is an HP product, however, this signal should
be used for only SIR.
This function differs according to the IrDA controller used.
<HP’s controller>
FIRDIN#: It is an FIR receive data input signal.
<TEMIC’s controller>
SEL: It is an output port for external FIR/SIR switching.
<SHARP’s controller>
Use is prohibited.
IRDOUT#
O
This is the IrDA serial data output signal. It is used when the IrDA controller sends serial data from the
VR4121.
(7) Debug serial interface signals
Signal
I/O
Function
DDOUT/
GPIO44
O
This is the debug serial data output signal. It is used when the VR4121 sends serial data to an external
debug serial controller.
When this pin is not used for the DDOUT signal, it can be used as a general-purpose output port.
DDIN/
GPIO45
I/O
This is the debug serial data input signal. It is used when an external debug serial data controller sends
serial data to the VR4121.
When this pin is not used for the DDIN signal, it can be used as a general-purpose output port.
DRTS#/
GPIO46
O
This is a transmission request signal. The VR4121 asserts this signal before sending serial data.
When this pin is not used for the DRTS# signal, it can be used as a general-purpose output port.
DCTS#/
GPIO47
I/O
This is a transmit acknowledge signal. The VR4121 asserts this signal when it is ready to receive
transmitted serial data.
When this pin is not used for the DCTS# signal, it can be used as a general-purpose output port.
(8) Keyboard interface signals
Signal
I/O
Function
KPORT (0:7)
I
This is a keyboard scan data input signal. It is used to scan for pressed keys on the keyboard.
KSCAN (0:11)/
GPIO (32:43)
O
These signal are used as keyboard scan data output signals and a general-purpose output port. The scan
line is set as active when scanning for pressed keys on the keyboard.
Signals that are not used for KSCAN signals can be used as a general-purpose output port.
(9) Audio interface signals
Signal
I/O
Function
AUDIOIN
I
This pin is the audio input signal.
AUDIOOUT
O
This is an audio output signal. Analog signals that have been converted via the on-chip 10-bit D/A
converter are output.
Data Sheet U14691EJ1V0DS00
13
µPD30121
(10) Touch panel/general purpose A/D interface signals
Signal
I/O
Function
TPX (0:1)
I/O
This is an I/O signal that is used for the touch panel. It uses the voltage applied to the X coordinate and
the voltage input to the Y coordinate to detect which coordinates on the touch panel are being pressed.
TPY (0:1)
I/O
This is an I/O signal that is used for the touch panel. It uses the voltage applied to the Y coordinate and
the voltage input to the X coordinate to detect which coordinates on the touch panel are being pressed.
ADIN (0:2)
I
This is a general-purpose A/D input signal.
(11) General-purpose I/O Signals
Signal
I/O
Function
GPIO (0:3)
I/O
These are maskable power-on factors. After start-up, they are used as ordinary generalpurpose I/O ports.
GPIO4/SRAS#
I/O
See (1) System bus interface signals.
GPIO5/SCAS#
I/O
See (1) System bus interface signals.
GPIO6/SYSDIR
I/O
See (1) System bus interface signals.
GPIO7/SPOWER
I/O
See (1) System bus interface signals.
GPIO8
I/O
These are general-purpose I/O ports.
GPIO (9:12)
I/O
These are maskable power-on factors. After start-up, they are used as ordinary generalpurpose I/O ports.
GPIO (13:14)
I/O
These are general-purpose I/O ports.
GPIO (16:31)/DATA (16:31)
I/O
See (1) System bus interface signals.
GPIO (32:43)/KSCAN (0:11)
O
See (8) Keyboard interface signals.
GPIO44/DDOUT
O
See (7) Debug serial interface signals.
GPIO45/DDIN
I/O
See (7) Debug serial interface signals.
GPIO46/DRTS#
O
See (7) Debug serial interface signals.
GPIO47/DCTS#
I/O
See (7) Debug serial interface signals.
GPIO48/DBUS32
I/O
See (14) Initial setting signals.
GPIO49/SMODE1
I/O
See (14) Initial setting signals.
(12) HSP MODEM interface signals
Signal
I/O
Function
IRING
I
RING signal detect signal. This pin becomes active when the RING signal is detected.
ILCSENSE
I
Handset detect signal
OFFHOOK
O
On-hook relay control signal
MUTE
O
Modem speaker mute control signal
AFERST#
O
CODEC reset signal
SDI
I
Serial input signal from CODEC
FS
I
Frame synchronization signal from CODEC
SDO
O
Serial output signal to CODEC
HSPSCLK
I
Operation clock input of modem interface block for CODEC
TELCON
O
Handset relay control signal
HC0
O
CODEC control signal
HSPMCLK
O
Clock output to CODEC
OPD#
O
Use this pin for controlling power of CODEC and DAA. This signal is set as active when the power
supply of CODEC and DAA is ON.
14
Data Sheet U14691EJ1V0DS00
µPD30121
(13) LED interface signal
Signal
LEDOUT#
I/O
Function
O
This is an output signal for lighting LEDs.
(14) Initial setting signals
Signal Name
I/O
Function
DBUS32/
GPIO48
I/O
The function differs depending on the operating status.
<During normal operation (output)>
This can be used as a general-purpose output port.
<After an RTC reset (input)>
This is the switching signal for the data bus width. This signal is sampled at 1RTC clock cycle
after the RTCRST# signal changes from low level to high level.
1: The data bus has a 32-bit width.
0: The data bus has a 16-bit width.
SMODE1/
GPIO49
I/O
The function differs depending on the operating status.
<During normal operation (output)>
This can be used as a general-purpose output port.
< After an RTC reset (input)>
This is a switching signal for the memory being used. It is used in combination with the
SMODE2 signal. This signal is sampled at 1RTC clock cycle after the RTCRST# signal
changes from low level to high level.
SMODE2
I
This a switching signal for the memory being used. It is used in combination with the SMODE1
signal. This signal is sampled when the RTCRST# signal changes from low level to high level.
The relation between the SMODE (2:1) signal and the memory being used is shown below.
SMODE (2:1) signal
11
10
01
00
MIPS16EN
I
Used Memory
ROM: SROM
RAM: SDRAM
ROM: Flash memory, PageROM, ordinary ROM
RAM: SDRAM
ROM (boot bank): Flash memory, PageROM, ordinary ROM
ROM (except boot bank): SROM
RAM: SDRAM
ROM: Flash memory, PageROM, ordinary ROM
RAM: DRAM (EDO type)
This pin enables the use of MIPS16 instructions. This signal is sampled at 1RTC clock cycle after
the RTCRST# signal changes from low level to high level.
1: Enables the use of MIPS16 instructions.
0: Disables the use of MIPS16 instructions.
Data Sheet U14691EJ1V0DS00
15
µPD30121
(15) Dedicated VDD and GND signals
Signal Name
Power-Supply System
Function
VDDP
2.5 V
Dedicated VDD for the PLL analog unit
GNDP
2.5 V
Dedicated GND for the PLL analog unit
VDDPD
2.5 V
Dedicated VDD for the PLL digital unit. Its function is identical to VDD2.
GNDPD
2.5 V
Dedicated GND for the PLL digital unit. Its function is identical to GND2.
CVDD
3.3 V
Dedicated VDD for the oscillator
CGND
3.3 V
Dedicated GND for the oscillator
DVDD
3.3 V
Dedicated VDD for the D/A converter. The voltage applied to this pin
becomes the maximum of the analog output of AUDIOOUT signal.
DGND
3.3 V
Dedicated GND for D/A converter. The voltage applied to this pin
becomes the minimum of the analog output of AUDIOOUT signal.
AVDD
3.3 V
Dedicated VDD for the A/D converter. The voltage applied to this pin
becomes the maximum voltage that can be detected by the A/D interface
signals (8 lines).
AGND
3.3 V
Dedicated GND for the A/D converter. The voltage applied to this pin
becomes the minimum voltage that can be detected by the A/D interface
signals (8 lines).
PIUVDD
3.3 V
Dedicated VDD for touch-sensitive panel interface
PIUGND
3.3 V
Dedicated GND for touch-sensitive panel interface
VDD2
2.5 V
Normal 2.5-V system VDD
GND2
2.5 V
Normal 2.5-V system GND
VDD3
3.3 V
Normal 3.3-V system VDD
GND3
3.3 V
Normal 3.3-V system GND
Caution
The VR4121 has two types of power supplies. There are no restrictions as to the sequence in which
these power supplies are applied. However, do not apply one type of power for more than one
second while the other power supply is not applied.
16
Data Sheet U14691EJ1V0DS00
µPD30121
1.2 Pin Status in Specific Status
(1/4)
Pin Name
After Reset by
the RTC Reset
After Reset by the
Deadman’s Switch
or RSTSW# Signal
In the Suspend
Mode
In the Hibernate
Mode or Shut Down
by the HAL Timer
During a Bus
Hold
ADD25/SCLK
0
Note 1
Note 2
0
Hi-Z
ADD (0:24)
0
0
Note 2
0
Hi-Z
DATA (0:15)
0
0
Note 2
0
Hi-Z
DATA (16:31)/
0/
Hi-Z
0/
Hi-Z
Note 2
GPIO (16:31)
0/
Hi-Z
Hi-Z/
Note 2
LCDCS#
Hi-Z
1
1
Hi-Z
1
RD#
Hi-Z
1
1
Hi-Z
Hi-Z
Hi-Z
WR#
Hi-Z
1
1
Hi-Z
LCDRDY
−
−
−
−
−
ROMCS (2:3)#
Hi-Z
Note 3
Note 3
Note 3
Note 3
ROMCS (0:1)#
Hi-Z
1
1
Hi-Z
1
UUCAS#/MRAS3#
Note 4
Note 5
Note 6
0
Hi-Z
ULCAS#/MRAS2#
Note 4
Note 5
Note 6
0
Hi-Z
MRAS (0:1)#
Hi-Z
1
1
1
Hi-Z
UCAS#
0
Note 7
0
0
Hi-Z
LCAS#
0
Note 7
0
0
Hi-Z
BUSCLK
0
0
Note 2
0
Note 8
Notes 1. This differs depending on the setting of the SCLK bit in the SDRAMMODEREG register.
When SCLK bit has a value of "1": outputs clock.
When SCLK bit has a value of "0": low level is output.
2. Maintains the state of the previous Full-speed Mode.
3. When used as the chip select for the ROM or extended ROM, this is the same as ROMCS (0:1)# pins.
When used as the RAS for the extended DRAM, this is the same as MRAS (0:1)# pins.
4. When DBUS32 signal = 1, this becomes the high impedance state.
When DBUS32 signal = 0, the high level is output.
5. When DBUS32 signal = 1: See Note 7 below.
When DBUS32 signal = 0: high level is output.
6. When DBUS32 signal = 1: low level is output.
When DBUS32 signal = 0: high level is output.
7. Reset by the RSTSW# signal: The pin outputs a low level. (Self refresh)
Reset by the Deadman’s switch: The pin outputs a high level.
8. Bus hold from the Suspend Mode: The state of the previous Full-speed Mode is maintained.
Bus hold from Full-speed Mode or Standby Mode: Outputs clocks.
Remark 0: low level, 1: high level, Hi-Z: high impedance
Data Sheet U14691EJ1V0DS00
17
µPD30121
(2/4)
Pin Name
After Reset by
the RTC Reset
After Reset by the
Deadman’s Switch
or RSTSW# Signal
In the Suspend
Mode
In the Hibernate
Mode or Shut Down
by the HAL Timer
During a Bus
Hold
SHB#
Hi-Z
1
1
Hi-Z
Hi-Z
IOR#
Hi-Z
1
1
Hi-Z
Hi-Z
IOW#
Hi-Z
1
1
Hi-Z
Hi-Z
MEMR#
Hi-Z
1
1
Hi-Z
Hi-Z
MEMW#
Hi-Z
1
1
Hi-Z
Hi-Z
ZWS#
−
−
−
−
−
RSTOUT
Hi-Z
1
0
Hi-Z
Note 1
IOCS16#
−
−
−
−
−
MEMCS16#
−
−
−
−
−
IOCHRDY
−
−
−
−
−
HLDRQ#
−
−
−
−
−
HLDACK#
Hi-Z
1
Note 1
Hi-Z
Note 1
CKE
0
Note 2
Note 3
Note 3
Hi-Z
RTCX1
−
−
−
−
−
RTCX2
−
−
−
−
−
CLKX1
−
−
−
−
−
CLKX2
−
−
−
−
−
FIRCLK
−
−
−
−
−
BATTINH/
BATTINT#
−
−
−
−
−
MPOWER
0
1
1
0
1
POWERON
0
0
0
0
0
POWER
−
−
−
−
−
−
RSTSW#
−
−
−
−
RTCRST#
−
−
−
−
−
RxD
−
−
−
−
−
TxD/CLKSEL2
Hi-Z
Note 4
1
1
1
Note 1
RTS#/CLKSEL1
Hi-Z
Note 4
1
1
1
Note 1
−
−
−
−
−
CTS#
DCD#/GPIO15
DTR#/CLKSEL0
−
Hi-Z
Note 4
−
−
−
−
1
1
1
Note 1
DSR#
−
−
−
−
−
IRDIN
−
−
−
−
−
IRDOUT#
0
0
0
0
Note 1
FIRDIN#/SEL
Hi-Z
Hi-Z
Note 3
Hi-Z
Note 3
Notes 1.
2.
Normal operation proceeds.
This differs depending on the setting of the SCLK bit in the SDRAMMODEREG register.
When SCLK bit has a value of "1": outputs clock.
When SCLK bit has a value of "0": low level is output.
3.
Maintains the state of the previous Full-speed Mode.
4.
Specify the input data level using a high-resistance pull up or pull down resistor.
Remark 0: low level, 1: high level, Hi-Z: high impedance
18
Data Sheet U14691EJ1V0DS00
µPD30121
(3/4)
Pin Name
After Reset by
the RTC Reset
After Reset by the
Deadman’s Switch
or RSTSW# Signal
In the Suspend
Mode
In the Hibernate
Mode or Shut Down
by the HAL Timer
During a Bus
Hold
−/
Hi-Z
−/
Note 2
−/
Note 2
−/
Note 2
−/
Note 2
Note 1
1/
1
1/
Note 2
1/
Note 2
1/
Note 2
1/
Note 2
Note 1
1/
1
1/
Note 2
1/
Note 2
1/
Note 2
1/
Note 2
DCTS# /
GPIO47
Note 1
−/
Hi-Z
−/
Note 2
−/
Note 2
−/
Note 2
−/
Note 2
KPORT (0:7)
−
−
−
−
−
Hi-Z/
Hi-Z
Hi-Z/
Note 2
Note 2/
Note 2
Hi-Z/
Note 2
Note 3
GPIO (32:43)
AUDIOOUT
0
0
Note 2
0
Note 3
TPX (0:1)
1
1
Note 2
1
Note 3
TPY (0:1)
Hi-Z
Hi-Z
Note 2
Hi-Z
Note 3
ADIN (0:2)
−
−
−
−
−
Note 1
DDIN /
GPIO45
DDOUT /
GPIO44
DRTS# /
GPIO46
Note 1
KSCAN (0:11)
/
AUDIOIN
−
−
−
GPIO (0:3)
Hi-Z
Hi-Z
Note 2
SRAS#/
GPIO4
Hi-Z
Note 5/
0/
Note 2
0/
Hi-Z
Hi-Z/
Note 3
SCAS#/
GPIO5
Hi-Z
Note 5/
Hi-Z
0/
Note 2
0/
Hi-Z
Hi-Z/
Note 3
SYSDIR/
GPIO6
0/
Hi-Z
0/
Hi-Z
0/
Note 2
0/
Hi-Z
Hi-Z/
Note 3
SPOWER/
GPIO7
0/
Hi-Z
1/
Hi-Z
1/
Note 2
1/
Hi-Z
1/
Note 3
GPIO (8:14)
Hi-Z
Hi-Z
Note 2
Hi-Z
−
Note 4
Hi-Z
Note 4
Hi-Z
−
Note 3
Note 3
Notes 1. Software can switch the function pin and the output port.
2. The state of the previous Full-speed Mode is maintained.
3. Normal operation proceeds.
4. During hibernate mode, the pull-up/pull-down setting is retained.
5. When reset by RSTSW# signal: low level output (self refresh)
When reset by deadman's switch: high level output
Remark 0: low level, 1: high level, Hi-Z: high impedance
Data Sheet U14691EJ1V0DS00
19
µPD30121
(4/4)
Pin Name
After Reset by
the RTC Reset
After Reset by the
Deadman’s Switch
or RSTSW# Signal
In the Suspend
Mode
In the Hibernate
Mode or Shut Down
by the HAL Timer
During a Bus
Hold
IRING
−
−
−
−
−
−
−
−
−
−
Hi-Z
Hi-Z
Note 2
Hi-Z
Note 2
Hi-Z
Hi-Z
Note 2
Hi-Z
Note 2
0
0
Note 2
0
Note 2
SDI
−
−
−
−
−
FS
−
−
−
−
−
SDO
0
0
Note 2
0
Note 2
−
−
−
−
−
Hi-Z
Hi-Z
Note 2
Hi-Z
Note 2
0
0
Note 2
0
Note 2
0
0
Note 2
0
Note 2
OPD#
0
0
Note 2
0
Note 2
LEDOUT#
1
Note 3
Note 3
Note 3
Note 3
DBUS32/
Note 4
GPIO48
Hi-Z/
Hi-Z
Hi-Z/
Note 2
Note 2/
Note 2
Hi-Z/
Note 2
Note 2/
Note 2
MIPS16EN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SMODE1/
Note 4
GPIO49
Hi-Z/
Note 5
Hi-Z
Hi-Z/
Note 2
Note 2/
Note 2
Hi-Z/
Note 2
Note 2/
Note 2
SMODE2
−
−
−
−
−
ILCSENSE
OFFHOOK
MUTE
Note 1
Note 1
Note 1
AFERST#
HSPSCLK
Note 1
TELCON
Note 1
HC0
HSPMCLK
Note 1
Notes 1. When initializing, always set BSC bit to 1 in the HSPINT register (0x0C00 0020).
2. The state of the previous Full-speed Mode is maintained.
3. Normal operation proceeds.
4. After the RTC reset is released, this functions as an output port.
5. Specify the input data level using a high-resistance pull up or pull down resistor.
Remark 0: low level, 1: high level, Hi-Z: high impedance
20
Data Sheet U14691EJ1V0DS00
µPD30121
1.3 Recommended Connection and I/O Circuit Types
(1/3)
Pin Name
Internal
Processing
External
Processing
Drive
Capability
I/O Circuit
Type
Recommended
Connection of
Unused Pins
ADD25/SCLK
Slew rate buffer
−
120 pF
A
−
ADD (0:24)
Slew rate buffer
−
120 pF
A
−
DATA (0:15)
−
−
40 pF
A
−
DATA (16:31)/
GPIO (16:31)
−
Note 1
40 pF
A
Connect to VDD or
GND via resistor
LCDCS#
Slew rate buffer
−
40 pF
A
Leave open
RD#
Slew rate buffer
Note 2
120 pF
A
Leave open
WR#
Slew rate buffer
Note 2
120 pF
A
Leave open
−
Note 3
−
A
Connect to GND
ROMCS (2:3)#
Slew rate buffer
Note 4
40 pF
A
Leave open
ROMCS (0:1)#
Slew rate buffer
−
40 pF
A
Leave open
UUCAS#/MRAS3#
Slew rate buffer
Note 2
120 pF
A
Leave open
ULCAS#/MRAS2#
Slew rate buffer
Note 2
120 pF
A
Leave open
MRAS (0:1)#
Slew rate buffer
Note 2
40 pF
A
Leave open
UCAS#
Slew rate buffer
Note 2
120 pF
A
Leave open
LCAS#
Slew rate buffer
Note 2
120 pF
A
Leave open
BUSCLK
Slew rate buffer
−
40 pF
A
Leave open
SHB#
Slew rate buffer
Note 2
40 pF
A
Leave open
IOR#
Slew rate buffer
Note 2
40 pF
A
Leave open
IOW#
Slew rate buffer
Note 2
40 pF
A
Leave open
MEMR#
Slew rate buffer
Note 2
40 pF
A
Leave open
MEMW#
Slew rate buffer
Note 2
40 pF
A
Leave open
Note 5
Note 3
−
A
Connect to VDD
RSTOUT
Slew rate buffer
Pull up
40 pF
A
Leave open
IOCS16#
Note 5
Note 3
−
A
Connect to VDD
MEMCS16#
Note 5
Note 3
−
A
Connect to VDD
IOCHRDY
Note 5
Note 3
−
A
Connect to GND
LCDRDY
ZWS#
Notes 1. Pins DATA (16:31)/GPIO (16:31) in the VR4121 function as GPIO (16:31) signals when using the 16-bit
data bus. When using these pins as GPIO (16:31) signals, pull them up or pull down so as not to input
an intermediate-level signal.
2. When the bus hold function is used, external pull-up is recommended for the VR4121.
3. Do not input an intermediate-level signal.
4. When used as the RAS signal of extended DRAM, external pull-up is recommended for the VR4121.
5. When the MPOWER pin outputs the low-level, intermediate-level input is enabled.
Remarks 1. No specification (−) in the External Processing column indicates that the external processing is
unnecessary.
2. No specification (−) in the Recommended Connection of Unused Pins column indicates that the pin
is always connected.
Data Sheet U14691EJ1V0DS00
21
µPD30121
(2/3)
Pin Name
Internal
Processing
External
Processing
Drive
Capability
I/O Circuit
Type
Recommended
Connection of
Unused Pins
HLDRQ#
Note
Pull up
−
A
Directly connect to VDD
HLDACK#
Slew rate buffer
−
40 pF
A
Leave open
CKE
−
−
120 pF
A
Leave open
RTCX1
−
Resonator
−
−
−
RTCX2
−
Resonator
−
−
Leave open
CLKX1
−
Resonator
−
−
−
CLKX2
−
Resonator
−
−
Leave open
−
Resonator
−
A
Directly connect to VDD
BATTINH/
BATTINT#
Schmitt input
−
−
B
Directly connect to VDD
MPOWER
−
−
40 pF
A
Leave open
POWERON
−
−
40 pF
A
Leave open
POWER
Schmitt input
−
−
B
−
RSTSW#
Schmitt input
−
−
B
−
RTCRST#
FIRCLK
Schmitt input
−
−
B
−
RxD
−
−
−
A
Connect to GND
TxD/CLKSEL2
−
Pull up/
Pull down
40 pF
A
−
RTS#/CLKSEL1
−
Pull up/
Pull down
40 pF
A
−
CTS#
−
−
−
A
Connect to VDD
Schmitt input
Pull up
−
B
Connect to VDD or
GND
DTR#/CLKSEL0
−
Pull up/
Pull down
40 pF
A
−
DSR#
−
−
−
A
Connect to VDD
IRDIN
−
Pull up
−
A
Connect to VDD or
GND
IRDOUT#
−
−
40 pF
A
Leave open
FIRDIN#/SEL
−
Pull up/
Pull down
40 pF
A
Connect to VDD via
resistor
DDIN/GPIO45
−
−
40 pF
A
Connect to VDD or
GND via resistor
DDOUT/GPIO44
−
−
40 pF
A
Leave open
DRTS#/GPIO46
−
−
40 pF
A
Leave open
DCTS#/GPIO47
−
−
40 pF
A
Connect to VDD or
GND via resistor
DCD#/GPIO15
Note Intermediate-level input is enabled when the MPOWER pin is set for low-level output.
Remarks 1. No specification (−) in the External Processing column indicates that the external processing is
unnecessary.
2. No specification (−) in the Recommended Connection of Unused Pins column indicates that the pin
is always connected.
22
Data Sheet U14691EJ1V0DS00
µPD30121
(3/3)
Pin Name
Internal
Processing
External
Processing
Drive
Capability
I/O Circuit
Type
Recommended
Connection of
Unused Pin
Schmitt input,
Pull down
−
−
B
Leave open
KSCAN (0:11)/
GPIO (32:43)
−
−
40 pF
A
Leave open
AUDIOOUT
−
Note 1
−
F
Leave open
TPX (0:1)
−
−
120 pF or more
C
Leave open
TPY1
−
−
120 pF or more
D
Leave open
TPY0
−
−
120 pF or more
C
Leave open
ADIN (0:2)
−
−
−
E
Leave open
AUDIOIN
−
−
−
E
Leave open
GPIO (0:3)
Schmitt input, Note 2
Note 2
40 pF
B
Connect to VDD or
GND via resistor
SRAS#/GPIO4
Schmitt input, Note 2
Note 2
40 pF
B
Connect to VDD or GND
SCAS#/GPIO5
Schmitt input, Note 2
Note 2
40 pF
B
Connect to VDD or GND
SYSDIR/GPIO6
Schmitt input, Note 2
Note 2
40 pF
B
Leave open
SPOWER/GPIO7
Schmitt input, Note 2
Note 2
40 pF
B
Connect to VDD or GND
GPIO (8:14)
Schmitt input, Note 2
Note 2
40 pF
B
Connect to VDD or
GND via resistor
KPORT (0:7)
Schmitt input
Pull down
−
B
Connect to GND
ILCSENSE
−
Pull down
−
A
Connect to GND
OFFHOOK
−
−
40 pF
A
Leave open
MUTE
−
−
40 pF
A
Leave open
AFERST#
−
−
40 pF
A
Leave open
SDI
−
Pull up/Pull down
−
A
Connect to GND
FS
−
Pull up/Pull down
−
A
Connect to GND
SDO
−
−
40 pF
A
Leave open
HSPSCLK
−
Note 3
−
A
Connect to GND
TELCON
−
−
40 pF
A
Leave open
HC0
−
−
40 pF
A
Leave open
HSPMCLK
−
−
40 pF
A
Leave open
OPD#
−
−
40 pF
A
Leave open
LEDOUT#
−
−
40 pF
A
Leave open
DBUS32/GPIO48
−
Pull up/Pull down
40 pF
A
−
MIPS16EN
−
Pull up/Pull down
40 pF
A
−
SMODE1/GPIO49
−
Pull up/Pull down
−
A
−
SMODE2
−
Pull up/Pull down
−
A
−
IRING
Notes 1.
Connect an operation amplifier which has high-impedance input characteristics, since the output level
of AUDIOOUT pin varies according to the external impedance.
2.
If internal pull-up or pull-down resistors are used in GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5,
SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14) pins switch between pull up, pull down, and open by
software.
If an internal pull-up or pull-down resistor is not used, then provide an external pull-up or pull-down
resistor.
3.
Input a synchronous clock from CODEC.
Data Sheet U14691EJ1V0DS00
23
µPD30121
Remarks 1. No specification (−) in the External Processing column indicates that the external processing is
unnecessary.
2. No specification (−) in the Recommended Connection of Unused Pins column indicates that the pin
is always connected.
1.4 Pin I/O Circuits
Type A
Type D
VDD
Data
VDD
Data
P-ch
P-ch
IN/OUT
IN/OUT
Output
disable
Output
disable
N-ch
N-ch
P-ch
+
−
Input
enable
N-ch
Vref
Type B
VDD
Pullup
enable
P-ch
VDD
Data
Input
enable
N-ch
P-ch
IN/OUT
Type E
Open drain
Output
disable
P-ch
N-ch
+
IN
N-ch
−
Vref
Type F
Pulldown
enable
N-ch
Analog
output
voltage
Type C
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
P-ch
+
−
N-ch
Vref
24
Data Sheet U14691EJ1V0DS00
OUT
µPD30121
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Supply voltage
Input voltage
Symbol
Rating
Unit
VDD2
2.5 V (VDDP, VDDPD, VDD2)
−0.5 to +3.3
V
VDD3
3.3 V (CVDD, DVDD, AVDD, PIUVDD, VDD3)
−0.5 to +4.0
V
VDD3 ≥ 3.7 V
−0.5 to +4.0
V
VDD3 < 3.7 V
−0.5 to VDD3 + 0.3
V
−65 to +150
°C
VI
Storage temperature
Condition
Tstg
Cautions 1. Do not short-circuit two or more output pins simultaneously.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The specifications and conditions shown in DC Characteristics and AC Characteristics are
the ranges for normal operation and quality assurance of the product.
3. VI can be −1.5 V if the input pulse is less than 10 ns.
Data Sheet U14691EJ1V0DS00
25
µPD30121
Operating Conditions
(1) 131 MHz model
Parameter
Symbol
Supply voltage
Condition
MIN.
MAX.
Unit
VDD2
2.5 V (VDDP, VDDPD, VDD2)
2.3
2.7
V
VDD3
3.3 V (CVDD, DVDD, AVDD, PIUVDD, VDD3)
3.0
3.45
V
−10
+70
°C
Ambient temperature
TA
Note 1
VDDS
3.0
V
Note 2
VDDH1
2.5
V
Note 3
VDDH2
3.0
V
Oscillation start voltage
Oscillation hold voltage
Oscillation hold voltage
Notes 1. This is a voltage at which oscillation is always started after power application, and is applied to
oscillators of 32.768 kHz and 18.432 MHz.
2. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 32.768 kHz.
3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 18.432 MHz.
(2) 168 MHz model
Parameter
Symbol
Supply voltage
Ambient temperature
Condition
MIN.
MAX.
Note 1
2.7
Unit
VDD2
2.5 V (VDDP, VDDPD, VDD2)
2.6
VDD3
3.3 V (CVDD, DVDD, AVDD, PIUVDD, VDD3)
3.0
3.45
V
−10
+70
°C
TA
V
Oscillation start voltage
Note 2
VDDS
3.0
V
Oscillation start voltage
Note 3
VDDH1
2.5
V
Oscillation start voltage
Note 4
VDDH2
3.0
V
Notes 1. If VDD2 exceeds 2.7 V, be sure to keep the time for which the voltage is exceeded to less than 10 % of
the total operating time of the VR4121, and the maximum value of VDD2 to less than 2.8 V.
2. This is a voltage at which oscillation is always started after power application, and is applied to
oscillators of 32.768 kHz and 18.432 MHz.
3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 32.768 kHz.
4. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 18.432 MHz.
Capacitance (TA = 25°°C, VDD = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Condition
fC = 1 MHz
Unmeasured pins returned to 0 V.
MIN.
MAX.
Unit
10
pF
10
pF
Caution Precision tests have not been performed. Only guaranteed as design characteristics.
26
Data Sheet U14691EJ1V0DS00
µPD30121
DC Characteristics
(1) 131 MHz model (TA = −10 to +70°°C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V)
(1/2)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
VOH1
IOH = −2 mA
0.8VDD3
V
Output voltage, high
VOH2
IOH = −12 mA
0.8VDD3
V
Output voltage, low
VOL1
IOL = 2 mA
0.4
IOL = 20 µA
0.1
IOL = 12 mA
0.4
IOL = 20 µA
0.1
Output voltage, high
Note 1
Note 1
Output voltage, low
VOL2
Note 2
Clock input voltage, high
Note 2
Clock input voltage, low
Note 3
Input voltage, high
Note 3
Input voltage, low
Note 4
Input voltage, high
Note 4
Input voltage, low
Note 4, 5
Hysteresis voltage
V
V
VIH1
0.8 VDD3
VDD3 + 0.3
V
VIL1
−0.3
0.3 VDD3
V
VIH2
2.0
VDD3 + 0.3
V
VIL2
−0.3
0.3VDD3
V
VIH3
0.75VDD3
VDD3 + 0.3
V
VIL3
−0.3
0.6
V
VH
0.17VDD3
V
ILI
VDD3 = 3.45 V, VI = VDD3, 0 V
±5
µA
ILIH
VDD3 = 3.45 V, VI = VDD3
72
µA
Input leakage current, low
ILIL
VDD3 = 3.45 V, VI = 0 V
−72
µA
Output leakage current
ILO
VDD3 = 3.45 V, VI = VDD3, 0 V
±5
µA
Input leakage current
Note 6
Note 7
Input leakage current, high
Note 8
Notes 1. Applied to TPX (0:1), TPY (0:1). A panel resistance of 250 Ω is presumed.
2. Applies to FIRCLK and HSPSCLK pins.
3. Except RTCX1, CLKX1, FIRCLK, HSPSCLK, TPX (0:1), TPY (0:1), ADIN (0:2), AUDIOIN, POWER,
RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6, SPOWER/GPIO7,
GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins.
4. Applied to POWER, RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6,
SPOWER/GPIO7, GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins.
5. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input
signal is not recognized when the signal goes from low to high and the maximum voltage at which the
low level is not recognized when the signal goes from high to low.
6. Except KPORT (0:7) (input pins with pull-down resistor), TPX (0:1), and TPY (0:1) pins.
7. Applied to KPORT (0:7) pin (input pins with pull-down resistor), GPIO (0:3), SRAS#/GPIO4,
SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO (8:14) pins when the internal pull-down
resistor is used.
8. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO
(8:14) pins when the internal pull-up resistor is used.
Data Sheet U14691EJ1V0DS00
27
µPD30121
(2/2)
Parameter
Power supply current
Symbol
Note 2
IDD2
Condition
MIN.
TYP.
Note 1
MAX.
Unit
In Fullspeed mode
140
340
mA
In Standby mode
50
100
mA
In Suspend mode
15
30
mA
In Hibernate mode, VDD2 = 0.0 V,
0
0
µA
30
60
mA
In Standby mode, external load 0 pF
10
30
mA
In Suspend mode, external load 0 pF
3
9
mA
100
500
µA
when LED unit is off.
Note 3
IDD3
In Fullspeed mode, ADD (0:24),
ADD25/SCLK, CKE, RD#, WR#, TPX
(0:1), TPY (0:1) = 120 pF,
other pins = 40 pF
In Hibernate mode, external load 0 pF,
when LED unit is off.
Notes 1. Unless otherwise specified, these are reference values at TA = 25°C, VDD2 = 2.5 V, VDD3 = 3.3 V.
2. Total current flowing to the VDDP, VDDPD, and VDD2 pins.
3. Total current flowing to the CVDD, DVDD, AVDD, PIUVDD, and VDD3 pins.
Remark
28
IDD2 and IDD3 do not reach the maximum value at the same time in the Fullspeed mode.
Data Sheet U14691EJ1V0DS00
µPD30121
(2) 168 MHz model (TA = −10 to +70°°C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V)
(1/2)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
VOH1
IOH = −2 mA
0.8VDD3
V
Output voltage, high
VOH2
IOH = −12 mA
0.8VDD3
V
Output voltage, low
VOL1
IOL = 2 mA
0.4
IOL = 20 µA
0.1
IOL = 12 mA
0.4
IOL = 20 µA
0.1
Output voltage, high
Note 1
Note 1
Output voltage, low
VOL2
Note 2
Clock input voltage, high
Note 2
Clock input voltage, low
Note 3
Input voltage, high
Note 3
Input voltage, low
Note 4
Input voltage, high
Note 4
Input voltage, low
Note 4, 5
Hysteresis voltage
V
V
VIH1
0.8 VDD3
VDD3 + 0.3
V
VIL1
−0.3
0.3 VDD3
V
VIH2
2.0
VDD3 + 0.3
V
VIL2
−0.3
0.3VDD3
V
VIH3
0.75VDD3
VDD3 + 0.3
V
VIL3
−0.3
0.6
V
VH
0.17VDD3
V
ILI
VDD3 = 3.45 V, VI = VDD3, 0 V
±5
µA
ILIH
VDD3 = 3.45 V, VI = VDD3
72
µA
Input leakage current, low
ILIL
VDD3 = 3.45 V, VI = 0 V
−72
µA
Output leakage current
ILO
VDD3 = 3.45 V, VI = VDD3, 0 V
±5
µA
Input leakage current
Note 6
Note 7
Input leakage current, high
Note 8
Notes 1. Applied to TPX (0:1), TPY (0:1). A panel resistance of 250 Ω is presumed.
2. Applies to FIRCLK and HSPSCLK pins.
3. Except RTCX1, CLKX1, FIRCLK, HSPSCLK, TPX (0:1), TPY (0:1), ADIN (0:2), AUDIOIN, POWER,
RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6, SPOWER/GPIO7,
GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins.
4. Applied to POWER, RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6,
SPOWER/GPIO7, GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins.
5. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input
signal is not recognized when the signal goes from low to high and the maximum voltage at which the
low level is not recognized when the signal goes from high to low.
6. Except KPORT (0:7) (input pins with pull-down resistor), TPX (0:1), and TPY (0:1) pins.
7. Applied to KPORT (0:7) pin (input pins with pull-down resistor), GPIO (0:3), SRAS#/GPIO4,
SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO (8:14) pins when the internal pull-down
resistor is used.
8. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO
(8:14) pins when the internal pull-up resistor is used.
Data Sheet U14691EJ1V0DS00
29
µPD30121
(2/2)
Parameter
Power supply current
Symbol
Note 2
IDD2
Condition
MIN.
TYP.
Note 1
MAX.
Unit
In Fullspeed mode
180
370
mA
In Standby mode
50
100
mA
In Suspend mode
15
30
mA
In Hibernate mode, VDD2 = 0.0 V,
0
0
µA
30
60
mA
In Standby mode, external load 0 pF
10
30
mA
In Suspend mode, external load 0 pF
3
9
mA
100
500
µA
when LED unit is off.
Note 3
IDD3
In Fullspeed mode, ADD (0:24),
ADD25/SCLK, CKE, RD#, WR#, TPX
(0:1), TPY (0:1) = 120 pF,
other pins = 40 pF
In Hibernate mode, external load 0 pF,
when LED unit is off.
Notes 1. Unless otherwise specified, these are reference values at TA = 25°C, VDD2 = 2.6 V, VDD3 = 3.3 V.
2. Total current flowing to the VDDP, VDDPD, and VDD2 pins.
3. Total current flowing to the CVDD, DVDD, AVDD, PIUVDD, and VDD3 pins.
Remark
30
IDD2 and IDD3 do not reach the maximum value at the same time in the Fullspeed mode.
Data Sheet U14691EJ1V0DS00
µPD30121
Data Retention Characteristics (TA = 25°°C)
Parameter
Note 1
Data retention voltage
Note 2
Data retention input voltage, high
Symbol
Condition
MIN.
MAX.
Unit
VDDDR3
Hibernate mode, 3.3 V power supply
2.5
3.45
V
VIHDR
0.9VDDDR3
V
Notes 1. The data retention voltage is the voltage at which the operation of the Elapsed Time timer and the data
retention of the registers of the following peripheral units are guaranteed, and is not applied to the
internal data of the CPU core.
BCU: BCURFCNTREG, BCUCNTREG3, SDRAMMODEREG, SROMMODEREG, SDRAMCNTREG
PUM: PMUCNTREG (15:8), PMUCNT2REG, PMUWAITREG, PMUDIVREG
RTC: ETIMELREG, ETIMEMREG, ETIMEHREG, ECMPLREG, ECMPMREG, ECMPHREG,
RTCL1LREG,
RTCL1HREG,
RTCL1CNTLREG,
RTCL1CNTHREG,
RTCL2LREG,
RTCL2HREG, RTCL2CNTLREG, RTCL2CNTHREG, RTCINTREG (2:0)
GIU: GIUPODATL, GIUPODATH, GIUUSEUPNL, GIUTERMUPNL
KIU: KIUGPEN, PORTREG
LED: LEDHTSREG, LEDLTSREG, LEDHLTCLREG, LEDHLTCHREG, LEDCNTREG
2. Applied to RTCRST# pin.
Remark The values in parentheses are the targeted values.
Data Sheet U14691EJ1V0DS00
31
µPD30121
AC Characteristics (131 MHz model: TA = −10 to +70°°C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V
168 MHz model: TA = −10 to +70°°C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V)
AC test input waveform
(a) CTS#, DATA (0:15), DATA (16:31)/GPIO (16:31), DBUS32/GPIO48, DCTS#/GPIO47, DDIN/GPIO45, DSR#,
DTR#/CLKSEL0, FS, FIRDIN#/SEL, HLDRQ#, ILCSENSE, IOCHRDY, IOCS16#, IRDIN, LCDRDY,
MEMCS16#, RxD, RTS#/CLKSEL1, SDI, SMODE1/GPIO49, SMODE2, TxD/CLKSEL2, ZWS#
VDD
2.0 V
2.0 V
Test points
0.3 V
0.3 V
0V
(b) BATTINH/BATTINT#, DCD#/GPIO15, GPIO (0:3), GPIO (8:14), IRING, KPORT (0:7), POWER, RSTSW#,
RTCRST#, SCAS#/GPIO5, SPOWER/GPIO7, SRAS#/GPIO4, SYSDIR/GPIO6
VDD
0.75VDD
0.75VDD
Test points
0.2 V
0.2 V
0V
AC test output measuring points
(c) ADD (0:24), ADD25/SCLK, AFERST#, BUSCLK, CKE, DATA (0:15), DATA (16:31)/GPIO (16:31),
DBUS32/GPIO48, DCTS#/GPIO47, DDIN/GPIO45, DDOUT/GPIO44, DRTS#/GPIO46, DTR#/CLKSEL0,
FIRDIN#/SEL, GPIO (0:3), GPIO (8:14), HC0, HLDACK#, HSPMCLK, IOR#, IOW#, IRDOUT#, KSCAN
(0:11)/GPIO (32:43), LCAS#, LCDCS#, LEDOUT#, MEMR#, MEMW#, MPOWER, MRAS (0:1)#, MUTE,
OFFHOOK, OPD#, POWERON, RD#, ROMCS (0:3)#, RSTOUT, RTS#/CLKSEL1, SCAS#/GPIO5, SDO,
SHB#, SMODE1/GPIO49, SPOWER/GPIO7, SRAS#/GPIO4, SYSDIR/GPIO6, TELCON, TPX (0:1), TPY
(0:1), TxD/CLKSEL2, UCAS#, ULCAS#/MRAS2#, UUCAS#/MRAS3#, WR#
VDD
0.5VDD
Test points
0V
32
Data Sheet U14691EJ1V0DS00
0.5VDD
µPD30121
Load condition
(a) ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1)
ADD (0:24), ADD25/SCLK,
CKE, RD#, WR#,
TPX (0:1), TPY (0:1)
DUT
CL = 120 pF
(b) Other output pins
Output pin (other than those shown in (a))
DUT
CL = 40 pF
Data Sheet U14691EJ1V0DS00
33
µPD30121
(1) Clock parameter (1/2)
Parameter
HSPSCLK high-level width
Symbol
Condition
MIN.
TYP.
MAX.
Unit
tWHSH
When HSP unit is used
40
HSPSCLK low-level width
tWHSL
When HSP unit is used
40
HSPSCLK clock frequency
fHSCYC
When HSP unit is used
HSPSCLK clock cycle
tCYHS
When HSP unit is used
HSPSCLK clock rise time
tHSR
When HSP unit is used
HSPSCLK clock fall time
tSHF
When HSP unit is used
10
ns
HSPMCLK high-level width
tMPH
When HSP unit is used
tCYHM ×
0.45
tCYHM ×
0.55
ns
HSPMCLK low-level width
tMPL
When HSP unit is used
tCYHM ×
0.45
tCYHM ×
0.55
ns
HSPMCLK clock frequency
fMCYC
When HSP unit is used
0.585
18.432
MHz
HSPMCLK clock cycle
tCYHM
When HSP unit is used
54.253
1790.365
ns
FIRCLK clock frequency
FIRCLK clock duty
Note 1
SCLK high-level width
Note 1
SCLK low-level width
Note 2
SCLK jitter
ns
ns
ns
ns
fFIRCYC1
In FIR 4 Mbps
47.99520
48
48.00480
MHz
In FIR 1.152/0.576 Mbps
47.93800
48
48.02976
MHz
tFIRDUTY
10
tCH
3.5
tCL
3.5
90
fPCYC
%
ns
ns
3.5
%
Note 3
RFU
MHz
Note 4
168.5
MHz
CLKSEL (2:0) = 111
Note 4
BUSCLK low-level width
10
fFIRCYC2
CLKSEL (2:0) = 110
BUSCLK high-level width
MHz
108.5
tJitter
CPU core operating frequency
fMCYC
CLKSEL (2:0) = 101
147.5
MHz
CLKSEL (2:0) = 100
131.1
MHz
CLKSEL (2:0) = 011
118.0
MHz
CLKSEL (2:0) = 010
98.3
MHz
CLKSEL (2:0) = 001
90.7
MHz
CLKSEL (2:0) = 000
78.6
MHz
tBCLKH1
Note 5
45
ns
tBCLKH2
Note 6
10
ns
tBCLKL1
Note 5
45
ns
tBCLKL2
Note 6
10
ns
Notes 1. Applied to ADD25/SCLK pin.
2. Precision tests have not been performed. Only guaranteed as design characteristics.
3. Do not set CLKSEL (2:0) = 111.
4. The settings CLKSEL (2:0) = 110 and 101 are only guaranteed for the 168 MHz model. Do not apply
these settings to the 131 MHz model.
5. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 0.
6. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 1.
Remark CLKSEL (2:0): Value set to the TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins after reset.
34
Data Sheet U14691EJ1V0DS00
µPD30121
(1) Clock parameter (2/2)
tCYHS
tWHSH
tWHSL
HSPSCLK
(input)
tHSR
tSHF
tCYHM
tMPH
tMPL
tCH
tCL
tBCLKH1
tBCLKH2
tBCLKL1
tBCLKL2
HSPMCLK
(output)
SCLK
(output)
BUSCLK
(output)
Data Sheet U14691EJ1V0DS00
35
µPD30121
(2) Reset parameter
Parameter
Reset input low-level width
Symbol
tWRSL
Condition
MIN.
RTCRST#
MAX.
Unit
µs
305
tWRSL
RTCRST#
(input)
Remark For the RTCRST# characteristics at power application, refer to VR4121 User’s Manual.
(3) Initialization parameter
Parameter
Symbol
Data sampling time
(from RTCRST# ↑)
tSS
Output delay time (from RTCRST# ↑)
tOD
Condition
DBUS32/GPIO48
MIPS16EN
SMODE1/GPIO49
SMODE2
(input)
Unit
µs
µs
tOD
tSS
,
Don t
care
Hi-Z
Input
Output
Hi-Z
Hi-Z
Sampling
Remark Set the input data level by using a pull-up or pull-down resistor with high resistance.
36
MAX.
61.04
61.04
RTCRST#
(input)
TxD/CLKSEL2
RTS#/CLKSEL1
DTR#/CLKSEL0
(I/O)
MIN.
Data Sheet U14691EJ1V0DS00
µPD30121
(4) GPIO interface parameter (1/2)
Parameter
Input level width
GPIO input rise time
GPIO input fall time
Output level width
Symbol
Condition
MIN.
MAX.
Unit
tINP1
Note 1
91.5
µs
tINP2
Note 2
361.5
ns
tINP3
Note 3
180.6
ns
tGPINR1
Note 4
200
ns
tGPINR2
Note 5
10
ns
tGPINF1
Note 4
200
ns
tGPINF2
Note 5
10
ns
tOUTP
Note 6
30
ns
Notes 1. Applied to GPIO (0:3) pins.
2. Applied to GPIO (9:14) and DCD#/GPIO15 pins.
3. Applied to SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO8, and DATA
(16:31)/GPIO (16:31) pins.
4. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14),
and DCD#/GPIO15 pins.
5. Applied to DATA (16:31)/GPIO (16:31) pins.
6. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14),
DATA (16:31)/GPIO (16:31), KSCAN (0:11)/GPIO (32:43), DDOUT/GPIO44, DDIN/GPIO45, DRTS#/
GPIO46, DCTS#/GPIO47, DBUS32/GPIO48, and SMODE1/GPIO49 pins.
Caution These parameters are applied when the SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6,
SPOWER/GPIO7, DCD#/GPIO15, DATA (16:31)/GPIO (16:31), KSCAN (0:11)/GPIO (32:43), DDOUT/
GPIO44, DDIN/GPIO45, DRTS#/GPIO46, DCTS#/GPIO47, DBUS32/GPIO48, or SMODE1/GPIO49 pin
is used as the GPIO signal.
Data Sheet U14691EJ1V0DS00
37
µPD30121
(4) GPIO interface parameter (2/2)
(a) Input level width
tINP1 Note 1
tINP2 Note 2
tINP3 Note 3
Notes 1. GPIO (0:3) pins
2. GPIO (9:14), DCD#/GPIO15 pins
3. SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO8, DATA (16:31)/GPIO
(16:31) pins
(b) GPIO input rise/fall time
tGPINF1 Note 1
tGPINF2 Note 2
tGPINR1 Note 1
tGPINR2 Note 2
Notes 1. GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DCD#/
GPIO15 pins
2. DATA (16:31)/GPIO (16:31) pins
(c) Output level width
tOUTPNote
Note GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14),
DATA (16:31)/GPIO (16:31), KSCAN (0:11)/GPIO (32:43), DDOUT/GPIO44, DDIN/GPIO45,
DRTS#/GPIO46, DCTS#/GPIO47, DBUS32/GPIO48, SMODE1/GPIO49 pins
38
Data Sheet U14691EJ1V0DS00
µPD30121
(5) EDO-type DRAM read parameter (1/2)
The target DRAM is the µPD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60,
42S65165G5-A50, or 42S65165G5-A60.
Parameter
Symbol
Condition
MIN.
MAX.
Unit
MRAS (0:3)# pulse width
tRASP
70
ns
MRAS (0:3)# hold time (from UCAS#/LCAS# precharge)
tRHCP
45
ns
tRP
43
ns
UCAS#/LCAS# hold time (from MRAS (0:3)#)
tCSH
50
ns
UCAS#/LCAS# pulse width
tHCAS
10
ns
UCAS#/LCAS# precharge time
tCP
10
ns
Read/write cycle time
tHPC
25
ns
MRAS (0:3)# hold time (from UCAS#/LCAS#)
tRSH
25
ns
Row address setup time (to MRAS (0:3)#)
tASR
0
ns
UCAS#/LCAS# ↓ delay time from MRAS (0:3)# ↓
tRCD
24
ns
Column address delay time from MRAS (0:3)# ↓
tRAD
22
ns
Column address setup time (to UCAS#/LCAS#)
tASC
0
ns
Column address read time (to MRAS (0:3)#↑)
tRAL
40
ns
Row address hold time (from MRAS (0:3)# ↓)
tRAH
20
ns
Column address hold time 1 (from UCAS#/LCAS# ↓)
tCAH1
10
ns
Column address hold time 2 (from UCAS#/LCAS# ↓)
tCAH2
10
ns
Column address hold time 3 (from UCAS#/LCAS# ↓)
tCAH3
10
ns
Data access time (from UCAS#/LCAS# precharge)
tACP
39
ns
Data access time (from RD# ↓)
tOEA
25
ns
Data input setup time 1 (to UCAS#/LCAS# ↓)
tDS1
0
ns
Data input hold time 1 (from MRAS (0:3)#)
tDH1
5
ns
Data input setup time 2 (to UCAS#/LCAS# ↓)
tDS2
0
ns
Data input hold time 2 (from MRAS (0:3)#)
tDH2
5
ns
Data access time (from MRAS (0:3)# ↓)
tRAC
70
ns
Data access time (from column address)
tAA
30
ns
Data access time (from UCAS#/LCAS# ↓)
tCAC
20
ns
MRAS (0:3)# precharge time
Caution These ratings are applied only when a device operates within the recommended operating
condition range and the operating ambient temperature is kept constant.
If the power supply voltage or operating ambient temperature changes during DRAM access, the
above ratings are not applied.
Data Sheet U14691EJ1V0DS00
39
µPD30121
(5) EDO-type DRAM read parameter (2/2)
tRASP
MRAS (0:3)#Note 1
(output)
tRHCP
tCSH
tHCAS
tRSH
UCAS#/LCAS#Note 2
(output)
tCP
tRCD
tASR
tRP
tCAH3
tHPC
ADD (19:23)
(output)
tRAD
ADD (9:18)
(output)
tASC
tRAL
tCAH1
tRAH
tCAH2
RD#
(output)
tACP
tOEA
DATANote 3
(I/O)
tDS1
Invalid
tDH1
tDS2
tDH2
Invalid
tRAC
tAA
tCAC
Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins
In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins
2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins
In 16-bit mode: Applied to UCAS# and LCAS# pins
3. In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins
In 16-bit mode: Applied to DATA (0:15) pins
Remark The broken lines indicate high impedance.
40
Data Sheet U14691EJ1V0DS00
µPD30121
(6) EDO-type DRAM write parameter (1/2)
The target DRAM is the µPD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60,
42S65165G5-A50, or 42S65165G5-A60.
Parameter
Symbol
Condition
MIN.
MAX.
Unit
MRAS (0:3)# pulse width
tRASP
70
ns
MRAS (0:3)# hold time (from UCAS#/LCAS# precharge)
tRHCP
45
ns
tRP
43
ns
UCAS#/LCAS# hold time (from MRAS (0:3)# ↓)
tCSH
50
ns
UCAS#/LCAS# pulse width
tHCAS
10
ns
UCAS#/LCAS# precharge time
tCP
10
ns
Read/write cycle time
tHPC
25
ns
MRAS (0:3)# hold time (from UCAS#/LCAS#)
tRSH
25
ns
Row address setup time (to MRAS (0:3)# ↓)
tASR
0
ns
UCAS#/LCAS# ↓ delay time from MRAS (0:3)# ↓
tRCD
24
ns
Column address delay time from MRAS (0:3)# ↓
tRAD
22
ns
Column address setup time (to UCAS#/LCAS# ↓)
tASC
0
ns
Column address read time (to MRAS (0:3)# ↑)
tRAL
40
ns
Row address hold time (from MRAS (0:3)# ↓)
tRAH
20
ns
Column address hold time 1 (from UCAS#/LCAS# ↓)
tCAH1
10
ns
Column address hold time 2 (from UCAS#/LCAS# ↓)
tCAH2
10
ns
Column address hold time 3 (from UCAS#/LCAS# ↓)
tCAH3
10
ns
MRAS (0:3)# precharge time
WR# setup time
tWCS
0
ns
WR# hold time (from UCAS#/LCAS# ↓)
tWCH
20
ns
Data output setup time
tD1
0
ns
Data output hold time
tD2
10
ns
Caution These ratings are applied only when a device operates within the recommended operating
condition range and the operating ambient temperature is kept constant.
If the power supply voltage or operating ambient temperature changes during DRAM access, the
above ratings are not applied.
Data Sheet U14691EJ1V0DS00
41
µPD30121
(6) EDO-type DRAM write parameter (2/2)
tRASP
MRAS (0:3)#Note 1
(output)
tRHCP
tCSH
tRSH
tHCAS
UCAS#/LCAS#Note 2
(output)
tASR
tCP
tRCD
tCAH3
tHPC
ADD (19:23)
(output)
tRAD
ADD (9:18)
(output)
tASC
tRAL
tRAH
tCAH2
tCAH1
WR#
(output)
tWCS
tWCH
tD1
DATANote 3
(I/O)
tD2
tD1
tD2
Invalid
Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins
In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins
2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins
In 16-bit mode: Applied to UCAS# and LCAS# pins
3. In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins
In 16-bit mode: Applied to DATA (0:15) pins
42
Data Sheet U14691EJ1V0DS00
tRP
µPD30121
(7) DRAM refresh parameter
The target DRAM is the µPD42S161615L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60,
42S65165G5-A50, or 42S65165G5-A60.
(a) CAS-before-RAS refresh parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Read/write cycle time
tRC
104
ns
MRAS (0:3)# pulse width
tRAS
60
ns
MRAS (0:3)# precharge time
tRP
30
ns
UCAS#/LCAS# setup time (to MRAS (0:3)# ↓)
tCSR
5
ns
UCAS#/LCAS# hold time (from MRAS (0:3)# ↓)
tCHR
10
ns
MRAS (0:3)# precharge time from
UCAS#/LCAS# ↑
tCRP
5
ns
UCAS#/LCAS# precharge time
tCPN
10
ns
tRC
tRAS
MRAS (0:3)#Note 1
(output)
tRP
tCRP
UCAS#/LCAS#Note 2
(output)
tCSR
tCHR
tCPN
WR# H
(output)
Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins
In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins
2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins
In 16-bit mode: Applied to UCAS# and LCAS# pins
Data Sheet U14691EJ1V0DS00
43
µPD30121
(b) CAS-before-RAS self-refresh parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
tRASS
100
µs
MRAS (0:3)# precharge time
tRPS
110
ns
UCAS#/LCAS# hold time
tCHS
−50
ns
MRAS (0:3)# pulse width
Note
Note The CAS-before-RAS self-refresh parameter is valid when tRASS exceeds 100 µs.
tRASS
tRPS
MRAS (0:3)#Note 1
(output)
tCHS
UCAS#/LCAS#Note 2
(output)
Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins
In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins
2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins
In 16-bit mode: Applied to UCAS# and LCAS# pins
44
Data Sheet U14691EJ1V0DS00
µPD30121
(8) Normal ROM parameter (1/2)
Parameter
Symbol
Data access time (from address)
Note
Condition
MIN.
Unit
T × N − 19
tACC
Data access time (from ROMCS (0:3)# ↓)
MAX.
ns
tCE
T × N − 19
ns
tOE
T × (N − 1) − 29
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Note
Note
Data access time (from RD#↓)
Note The value of N is set by using the WROMA (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WROMA2
Bit
WROMA1
Bit
WROMA0
Bit
N
(TClock)
1
1
1
RFU
0
0
0
9
1
1
0
35
0
0
1
8
1
0
1
33
0
1
0
7
1
0
0
30
0
1
1
6
0
1
1
33
1
0
0
5
0
1
0
30
1
0
1
4
0
0
1
33
1
1
0
3
0
0
0
38
1
1
1
2
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
Data Sheet U14691EJ1V0DS00
45
µPD30121
(8) Normal ROM parameter (2/2)
When WROMA (0:2) bits = 111
ADD (19:23),
ADD (0:8)
(output)
ADD (9:18)
(output)
tACC
ROMCS (0:3)#
(output)
tCE
RD#
(output)
tOE
DATA Note
(I/O)
Invalid
Invalid
tDS
tDH
Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins
In 16-bit mode: Applied to DATA (0:15) pins
Remark The broken lines indicate high impedance.
46
Data Sheet U14691EJ1V0DS00
µPD30121
(9) Page ROM parameter (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
tACC1
T × N − 19
tACC2
T × M − 18
ns
tCE
T × N − 19
ns
Data access time (from RD#↓)
tOE
T × (N − 1) − 29
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Data access time (from address)
Note
Data access time (from ROMCS (0:3)# ↓)
Note
Note
ns
Note The value of N is set by using the WROMA (0:2) bits of the BCUSPEEDREG register.
The value of M is set by using the WPROM (0:1) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL 2 CLKSEL 1 CLKSEL 0
Signal
Signal
Signal
T (ns)
WROMA 2 WROMA 1 WROMA 0
N
Bit
Bit
Bit
(TClock)
WPROM WPROM
M
1 Bit
0 Bit
(TClock)
1
1
1
RFU
0
0
0
9
0
0
3
1
1
0
35
0
0
1
8
0
1
2
1
0
1
33
0
1
0
7
1
0
1
1
0
0
30
0
1
1
6
1
1

0
1
1
33
1
0
0
5
0
1
0
30
1
0
1
4
0
0
1
33
1
1
0
3
0
0
0
38
1
1
1
2
Remarks 1. Do not set CLKSEL (2:0)
signal = 111.
2. Do not set CLKSEL (2:0)
signal = 110, 101 with
131 MHz model.
Data Sheet U14691EJ1V0DS00
47
µPD30121
(9) Page ROM parameter (2/2)
ADD (1:3)
(output)
ADD (4:23),
ADD0
(output)
tACC2
tACC1
ROMCS (0:3)#
(output)
tCE
RD#
(output)
tOE
Note
DATA
(I/O)
Invalid
Invalid
tDS
tDH
tDS
tDH
Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins
In 16-bit mode: Applied to DATA (0:15) pins
Remark The broken lines indicate high impedance.
48
Data Sheet U14691EJ1V0DS00
µPD30121
(10) Flash memory mode write parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Write cycle time
tAVAV
150
Address setup time (to WR# ↑)
tAVWH
75
ns
Address setup time (to ROMCS (0:3)# ↓)
tAVEL
0
ns
ROMCS (0:3)# setup time (to WR#↓)
tELWL
10
ns
WR# low-level width
tWLWH
75
ns
ROMCS (0:3)# hold time (from WR# ↑)
tWHEH
10
ns
Address hold time (from WR# ↑)
tWHAX
10
ns
WR# high-level width
tWHWL
75
ns
Address setup time (to WR# ↓)
tAVWL
25
ns
Data output setup time (to WR# ↑)
tDVWH
75
ns
Data output hold time (from WR# ↑)
tWHDX
10
ns
ADD (19:23),
ADD (0:8)
(output)
ns
tAVAV
ADD (9:18)
(output)
tAVWH
ROMCS (0:3)#
(output)
tAVEL
tWLWH
WR#
(output)
DATA Note
(I/O)
tWHEH
tELWL
tAVWL
tWHWL
tWHAX
Invalid
tDVWH
tWHDX
Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins
In 16-bit mode: Applied to DATA (0:15) pins
Data Sheet U14691EJ1V0DS00
49
µPD30121
(11) Flash memory mode read parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data output delay time from address
tAVQV
180
ns
Data output delay time from ROMCS (0:3)#
tELQV
180
ns
Address setup time (to ROMCS (0:3)# ↓)
tAVEL
0
ns
Data output delay time from RD# ↓
tGLQV
80
ns
Address setup time (to RD# ↓)
tAVGL
0
ns
ROMCS (0:3)# hold time (from RD# ↑)
tGHEH
10
ns
Address hold time (from RD# ↑)
tGHAX
10
ns
RD# high-level width
tGHGL
75
ns
Data input setup time
tDS
0
ns
tDH
5
ns
tELGL
10
ns
Data input hold time
ROMCS (0:3)# setup time (to RD# ↓)
ADD (19:20),
ADD (0:8)
(output)
ADD (9:18)
(output)
tGHAX
ROMCS (0:3)#
(output)
tAVEL
tGHEH
tELGL
RD#
(output)
tGHGL
tAVGL
DATA Note
(I/O)
Invalid
Invalid
tDS
tGLQV
tELQV
tALQV
Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins
In 16-bit mode: Applied to DATA (0:15) pins
Remark The broken lines indicate high impedance.
50
Data Sheet U14691EJ1V0DS00
tDH
µPD30121
(12) System bus parameter (IOCHRDY) (1/3)
Parameter
Symbol
BUSCLK high-level width
BUSCLK low-level width
MIN.
MAX.
Unit
tBCLKH1
Note 1
45
ns
tBCLKH2
Note 2
10
ns
tBCLKL1
Note 1
45
ns
tBCLKL2
Note 2
Address setup time (to BUSCLK)
Notes 3, 4
Address setup time (to command signal ↓)
Note 3
Command signal setup time (to BUSCLK)
Command signal low-level width
Condition
Notes 3, 4
Note 3
Address hold time (from command signal ↑)
Notes 3, 4
Command signal recovery time
Note 4
IOCHRDY sampling time
10
ns
tAVCK
15
ns
tAVCL
T × N − 29
ns
tCLCK
15
ns
tCLCH
2 × T × N − 29
ns
tCHAV
25
ns
tCHCL
T × (N + 1) − 29
ns
tCLR
0
T × N − 44
ns
2 × T × N + 29
ns
tRHCH
T×N
Note 3
tCHRL
0
ns
Note 3
tDVCL
0
ns
tCHDV
25
ns
MEMCS16#/IOCS16# sampling start time
tAVSV1
2 × T × N − 44
ns
MEMCS16#/IOCS16# hold time (from command
tCHSV
0
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Notes 3, 4
Command signal ↑ delay time from IOCHRDY ↑
IOCHRDY hold time (from command signal ↑)
Data output setup time (to command signal ↓)
Note 3
Data output hold time (from command signal ↑)
Note 4
Note 3
signal ↓)
Notes 1. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 0.
2. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 1.
3. With the VR4121, the MEMW#, MEMR#, IOW#, and IOR# signals are called the command signals for
the system bus interface.
4. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WISAA2 Bit
WISAA1 Bit
WISAA0 Bit
N (TClock)
1
1
1
RFU
0
0
0
8
1
1
0
35
0
0
1
7
1
0
1
33
0
1
0
6
1
0
0
30
1
5
0
1
1
33
Note
4
0
Note
1
Note
1
1
Note
0
Note
0
0
Note
1
0
1
0
30
0
0
1
33
1
1
0

0
0
0
38
1
1
1

Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
3
Note If the WISAA (0:2) bits are set to 100 or
high when BSEL bit of BCUCNTREG3
register is 0, the AC characteristics of tAVCK
and tCLCK are not guaranteed.
Data Sheet U14691EJ1V0DS00
51
µPD30121
(12) System bus parameter (IOCHRDY) (2/3)
When WISAA (0:2) bits = 010, BSEL bit = 0
tBCLKH1 tBCLKL1
BUSCLKNote 1
(output)
BUSCLKNote 1
(output)
BUSCLKNote 1
(output)
BUSCLKNote 1
(output)
ADD (19:25),
ADD (0:8)
(output)
tAVCKNote 2
ADD (9:18)
(output)
tAVCL
SHB#
(output)
tCHAV
tCLCKNote 2
tCLCH
MEMR#/MEMW#,
IOR#/IOW#
(output)
tCHCL
tCLR
IOCHRDY
(input)
tCHRL
tRHCH
ZWS#
(input)
tAVSV1
MEMCS16#,
IOCS16#
(input)
DATA
(output)
tCHSV
tDVCL
tCHDV
Invalid
tDS
DATA
(input)
Invalid
tDH
Invalid
Notes 1. This indicates that there are four possible relationships between BUSCLK signal and other system
bus interface signals.
2. This indicates the minimum setup time to the BUSCLK signal rising or falling edge.
Remark The broken lines indicate high impedance.
52
Data Sheet U14691EJ1V0DS00
µPD30121
(12) System bus parameter (IOCHRDY) (3/3)
When WISAA (0:2) bits = 010, BSEL bit = 1
tBCLKH2 tBCLKL2
BUSCLK
(output)
ADD (19:25),
ADD (0:8)
(output)
tAVCKNote
ADD (9:18)
(output)
tAVCL
SHB#
(output)
tCLCKNote
MEMR#/MEMW#,
IOR#/IOW#
(output)
tCHAV
tCLCH
tCHCL
tCLR
IOCHRDY
(input)
tCHRL
tRHCH
ZWS#
(input)
tAVSV1
MEMCS16#,
IOCS16#
(input)
DATA
(output)
tCHSV
tDVCL
tCHDV
Invalid
tDS
DATA
(input)
Invalid
tDH
Invalid
Note This indicates the minimum setup time to the BUSCLK signal rising edge.
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
53
µPD30121
(13) System bus parameter (ZWS#) (1/2)
Parameter
Symbol
Address setup time (to BUSCLK)
Address setup time (to command signal ↓)
Notes 1, 2
Note 1
Command signal setup time (to BUSCLK)
Command signal low-level width
Notes 1, 2
Address hold time (from command signal ↑)
Note 1
Notes 1, 2
Command signal recovery time
Condition
MIN.
tAVCK
15
MAX.
ns
tAVCL
T × N − 29
ns
tCLCK
15
ns
tCLCH
T × N − 19
ns
tCHAV
25
ns
tCHCL
T × (N + 1) − 29
ZWS# ↓ delay time from command signal ↓
Notes 1, 2
Note 1
Data output setup time (to command signal ↓)
Note 1
Data output hold time (from command signal ↑)
Note 1
ns
T × (N − 1) − 20
tCLZL
ZWS# hold time (from command signal ↑)
Unit
ns
tCHZH
0
ns
tDVCL
0
ns
tCHDV
25
ns
MEMCS16#/IOCS16# sampling start time
tAVSV2
2 × T × (N – 1)
– 44
ns
MEMCS16#/IOCS16# hold time (from command
Note 1
signal ↑)
tCHSV
0
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Note 2
Notes 1. With the VR4121, the MEMW#, MEMR#, IOW#, and IOR# signals are called the command signals for
the system bus interface.
2. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WISAA2 Bit
WISAA1 Bit
WISAA0 Bit
N (TClock)
1
1
1
RFU
0
0
0
8
1
1
0
35
0
0
1
7
1
0
1
33
0
1
0
6
1
0
0
30
1
5
0
1
1
33
0
Note
1
Note
0
Note
Note
4
Note
3
0
0
1
0
30
0
0
1
33
1
1
0

0
0
0
38
1
1
1

Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
1
0
1
Note If the WISAA (0:2) bits are set to 100 or
high, the AC characteristics of tCLCK and
tAVCK are not guaranteed.
= 110, 101 with 131 MHz model.
54
1
Note
Data Sheet U14691EJ1V0DS00
µPD30121
(13) System bus parameter (ZWS#) (2/2)
When WISAA (0:2) bits = 101, BSEL bit = 0
BUSCLKNote 1
(output)
BUSCLKNote 1
(output)
BUSCLKNote 1
(output)
BUSCLKNote 1
(output)
tAVCKNote 2
ADD (19:25),
ADD (0:8)
(output)
ADD (9:18)
(output)
tAVCL
SHB#
(output)
tCHAV
tCLCKNote 2
MEMR#/MEMW#,
IOR#/IOW#
(output)
tCLCH
IOCHRDY
(input)
tCHCL
tCLZL
tCHZH
ZWS#
(input)
tAVSV2
tCHSV
MEMCS16#,
IOCS16#
(input)
tCHDV
tDVCL
DATA
(output)
Invalid
tDS
DATA
(input)
tDH
Invalid
Invalid
Notes 1. This indicates that there are four possible relationships between BUSCLK signal and other system
bus interface signals.
2. This indicates the minimum setup time to the BUSCLK signal rising or falling edge.
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
55
µPD30121
(14) High-speed system bus parameter (IOCHRDY) (1/2)
Parameter
Symbol
Address setup time (to command signal ↓)
Notes 1, 2
Condition
MIN.
MAX.
Unit
tAVCL
T × N − 29
ns
tCLCH
T × (N + M) − 29
ns
tCHAV
25
ns
Command signal recovery time
tCHCL
T × (N + 1) − 29
ns
IOCHRDY sampling start time
tCLR
0
ns
Command signal ↑ delay time from IOCHRDY ↑
tRHCH
T×M
IOCHRDY hold time (from command signal ↑)
tCHRL
0
ns
Command signal low-level width
Notes 1, 2
Address hold time (from command signal ↑)
Note 1
Notes 1, 2
Notes 1, 2
Note 1
Data output setup time (to command signal ↓)
T × (N + M) + 29
ns
tDVCL
−15
ns
tCHDV
25
ns
MEMCS16#/IOCS16# sampling start time
tAVSV1
2 × T × N – 44
ns
MEMCS16#/IOCS16# hold time (from command
Note 1
signal ↑)
tCHSV
0
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Note 1
Data output hold time (from command signal ↑)
Note 1
Note 2
Notes 1. With the VR4121, the MEMW# and MEMR# signals are called the command signals for the high-speed
system bus interface.
2. The values of N and M are set by using the WLCD/M (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WLCD/M2
Bit
WLCD/M1
Bit
WLCD/M0
Bit
N
(TClock)
M
(TClock)
1
1
1
RFU
0
0
0
8
8
1
1
0
35
0
0
1
7
7
1
0
1
33
0
1
0
6
6
1
0
0
30
0
1
1
5
5
0
1
1
33
1
0
0
4
4
0
1
0
30
1
0
1
3
3
0
0
1
33
1
1
0
2
2
0
0
0
38
1
1
1
1
2
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
56
Data Sheet U14691EJ1V0DS00
µPD30121
(14) High-speed system bus parameter (IOCHRDY) (2/2)
When WISAA (2:0) bits = 111
ADD (19:25),
ADD (0:8)
(output)
ADD (9:18)
(output)
SHB#
(output)
LCDCS#
(output)
tCHAV
tAVCL
MEMR#/MEMW#
(output)
tCLCH
tCHCL
tCLR
IOCHRDY
(input)
tRHCH
tCHRL
ZWS#
(input)
tAVSV1
tCHSV
MEMCS16#,
IOCS16#
(input)
tDVCL
DATA
(output)
tCHDV
Invalid
tDS
DATA
(input)
Invalid
tDH
Invalid
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
57
µPD30121
(15) High-speed system bus parameter (ZWS#) (1/2)
Parameter
Symbol
Address setup time (to command signal ↓)
Notes 1, 2
Command signal low-level width
Notes 1, 2
Address hold time (from command signal ↑)
Note 1
Notes 1, 2
Command signal recovery time
Condition
MIN.
tAVCL
T × N − 29
MAX.
Unit
ns
tCLCH
T × N − 19
ns
tCHAV
25
ns
tCHCL
T × (N + 1) − 29
ZWS# ↓ delay time from command signal ↓
Notes 1, 2
ns
T × (N − 1) − 20
tCLZL
ns
ZWS# signal hold time (from command signal ↑)
tCHZH
0
ns
Data output setup time (to command signal ↓)
tDVCL
−15
ns
Note 1
Note 1
Data output hold time (from command signal ↑)
Note 1
tCHDV
25
ns
MEMCS16#/IOCS16# sampling start time
tAVSV2
2 × T × (N – 1)
– 44
ns
MEMCS16#/IOCS16# hold time (from command
Note 1
signal ↑)
tCHSV
0
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Note 2
Notes 1. With the VR4121, the MEMW# and MEMR# signals are called the command signals for the high-speed
system bus interface.
2. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WISAA2 Bit
WISAA1 Bit
WISAA0 Bit
N
(TClock)
1
1
1
RFU
0
0
0
8
1
1
0
35
0
0
1
7
1
0
1
33
0
1
0
6
1
0
0
30
0
1
1
5
0
1
1
33
1
0
0
4
0
1
0
30
1
0
1
3
0
0
1
33
1
1
0
2
0
0
0
38
1
1
1
1
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
58
Data Sheet U14691EJ1V0DS00
µPD30121
(15) High-speed system bus parameter (ZWS#) (2/2)
When WISAA (0:2) bits = 111
ADD (19:25),
ADD (0:8)
(output)
ADD (9:18)
(output)
SHB#
(output)
LCDCS#
(output)
tCHAV
tAVCL
MEMR#/MEMW#
(output)
tCLCH
tCHCL
IOCHRDY
(input)
tCLZL
ZWS#
(input)
tCHZH
tAVSV2
tCHSV
MEMCS16#,
IOCS16#
(input)
tCHDV
tDVCL
DATA
(output)
Invalid
tDS
DATA
(input)
Invalid
tDH
Invalid
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
59
µPD30121
(16) LCD interface parameter (1/2)
Parameter
Symbol
Address setup time (to command signal ↓)
Note 1
Condition
tAS
Address hold time (from command signal ↑)
Note 1
Note 1
Command signal recovery time
LCDRDY sampling start time
Command signal delay time from LCDRDY ↑
Notes 1, 2
LCDRDY hold time (from command signal ↑)
Note 1
Data output setup time (to command signal ↑)
Notes 1, 2
Data output hold time (from command signal ↑)
Note 1
Data input setup time (to command signal ↑)
Note 1
Data input hold time (from command signal ↑)
Note 1
MIN.
MAX.
Unit
15
ns
tAH
0
ns
tRY
30
ns
tCLR
0
tRHCH
T×N
ns
T × (N + 2) + 29
ns
tRYZ
0
ns
tDVCH
T × (N + 2)
ns
tCHDV
25
ns
tDS
0
ns
tDH
5
ns
Notes 1. With the VR4121, the RD# and WR# signals are called the command signals for the LCD interface.
2. The values of N is set by using the WLCD/M (0:1) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WLCD/M1
Bit
WLCD/M0
Bit
N
(TClock)
1
1
1
RFU
0
0
8
1
1
0
35
0
1
6
1
0
1
33
1
0
4
1
0
0
30
1
1
2
0
1
1
33
0
1
0
30
0
0
1
33
0
0
0
38
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
60
Data Sheet U14691EJ1V0DS00
µPD30121
(16) LCD interface parameter (2/2)
ADD (19:20),
ADD (0:8)
(output)
ADD (9:18)
(output)
SHB#
(output)
LCDCS#
(output)
tAH
tAS
RD#/WR#
(output)
tRY
tCLR
tRHCH
tRYZ
LCDRDY
(input)
tDVCH
DATA
(output)
tCHDV
Invalid
tDS tDH
DATA
(input)
Invalid
Invalid
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
61
µPD30121
(17) Bus hold parameter (1/2)
Parameter
Symbol
Note
Condition
MIN.
MAX.
Unit
HLDRQ# input pulse width
tFHP
In Fullspeed/Standby mode
5T
ns
Data floating delay time
tFOFF
In Fullspeed/Standby mode
0
ns
Data valid delay time
tFON
In Fullspeed/Standby mode
0
ns
HLDRQ# input pulse width
tSHP
In Suspend mode
12T
ns
Data floating delay time
tSOFF
In Suspend mode
0
ns
Data valid delay time
tSON
In Suspend mode
0
ns
MRAS (0:3)# precharge time
tRPS
In Suspend mode
110
ns
UCAS#/LCAS# setup time
tCSR
In Suspend mode
5
ns
Note
Note The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
1
1
1
RFU
1
1
0
35
1
0
1
33
1
0
0
30
0
1
1
33
0
1
0
30
0
0
1
33
0
0
0
38
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
62
Data Sheet U14691EJ1V0DS00
µPD30121
(17) Bus hold parameter (2/2)
(a) Bus hold in Fullspeed/Standby mode
tFHP
HLDRQ#
(input)
HLDACK#
(output)
tFOFF
tFON
Note 1
Note 2
BUSCLK
(output)
Notes 1. UUCAS#/MRAS3#, ULCAS#/MRAS2#, MRAS (0:1)#, UCAS#, LCAS# pins
2. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD (0:24), ADD25/SCLK, and DATA (0:15)
pins, and DATA (16:31)/GPIO (16:31) pin in 32-bit mode
Remark The broken lines indicate high impedance.
(b) Bus hold in Suspend mode
tSHP
HLDRQ#
(input)
HLDACK#
(output)
tRPS
tSOFF
tSON
Note 1
tRPS
tCSR
Note 2
Note 3
BUSCLK
(output)
H
Notes 1. In 32-bit mode: MRAS (0:1)# pins
In 16-bit mode: UUCAS#/MRAS3#, ULCAS#/MRAS2#, MRAS (0:1)# pins
2. In 32-bit mode: UUCAS#/MRAS3#, ULCAS#/MRAS2#, UCAS#, LCAS# pins
In 16-bit mode: UCAS#, LCAS# pins
3. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD (0:24), ADD25/SCLK, and DATA (0:15)
pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
63
µPD30121
(18) Keyboard Interface parameter (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
KSCAN (0:11) high-level width
tSCAN
30 (K + 2) – 1
30.16 (K + 2) + 1
µs
Idle time (KSCAN (n+1) ↑ from KSCANn ↓)
tKWAIT
30 (L + 1) – 1
30.16 (L + 1) + 1
µs
tKI
30M – 1
30.16M + 1
µs
Key input setup time (to KSCANn ↑)
tKS
30 (N + 1) – 1
µs
Key input hold time (from KSCANn ↑)
tKH
0
µs
Key scan interval time
Notes 1. K: Sum of the values set to the T1CNT (0:4) bits and T2CNT (0:4) bits of the KIUWKS register
2. L: Value set to the T3CNT (0:4) bits of the KIUWKS register
3. M: Value set to KIUWKI register
4. N: Value set to the T1CNT (0:4) bits of the KIUWKS register
5. n = 0 to 11
(a) Keyboard scan parameter 1
tSCAN
KSCANn
(output)
Hi-Z
Hi-Z
tKWAIT
Hi-Z
KSCAN (n + 1)
(output)
Remark n = 0 to 10
(b) Keyboard scan parameter 2
KSCAN0 Hi-Z
(output)
Hi-Z
KSCAN1
(output)
Hi-Z
KSCAN2
(output)
KSCAN11
(output)
64
tKWAIT
Hi-Z
tKWAIT
tKWAIT + tKI
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Sheet U14691EJ1V0DS00
µPD30121
(18) Keyboard Interface parameter (2/2)
(c) Keyboard port parameter
KSCANn
(output)
Hi-Z
Hi-Z
tKS
tKH
KPORT (0:7)
(input)
Remark n = 0 to 11
Data Sheet U14691EJ1V0DS00
65
µPD30121
(19) Serial interface parameter (1/2)
Parameter
Symbol
Note
TxD output pulse width
RxD input pulse width
Condition
tTXD
Note
Note
IRDOUT# high-level output pulse width
IRDIN input pulse width
MIN.
MAX.
Unit
N–1
N+1
µs
tRXD
(9/16) × N
tIRDOUT
(3/16) × N – 1
tIRDIN
1
µs
(3/16) × N + 1
µs
µs
Note N: Data transfer rate per bit, which is determined by the divisor of the baud-rate generator that is set with
the SIUDLL and SIUDLM registers.
66
Baud Rate (bps)
SIUDLM, SIUDLL Resister
N (µs)
50
23,040
20,000
75
15,360
13,333
110
10,473
9,091
134.5
8,565
7,435
150
7,680
6,667
300
3,840
3,333
600
1,920
1,667
1,200
920
833
1,800
640
556
2,000
573
500
2,400
480
417
3,600
320
278
4,800
240
208
7,200
160
139
9,600
120
104
19,200
60
52.1
38,400
30
26.0
56,000
21
17.9
128,000
9
7.81
144,000
8
6.94
192,000
6
5.21
230,400
5
4.34
288,000
4
3.47
384,000
3
2.60
576,000
2
1.74
1,152,000
1
0.868
Data Sheet U14691EJ1V0DS00
µPD30121
(19) Serial interface parameter (2/2)
TxD
(output)
tTXD
RxD
(input)
tRXD
IRDOUT#
(output)
tIRDOUT
IRDIN
(input)
tIRDIN
Data Sheet U14691EJ1V0DS00
67
µPD30121
(20) Debug serial interface parameter
Parameter
Note
DDOUT output pulse width
Note
DDIN input pulse width
Symbol
Condition
MIN.
MAX.
Unit
tDDOUT
N–1
N+1
µs
tDDIN
(9/16) × N
µs
Note N: Transfer rate of baud rate per bit set to the BPR0 bits of the BPRM0REG register.
N (µs)
BPR0 (2:0) Bits
Baud Rate (bps)
111
115,200
8.68
110
57,600
17.36
101
38,400
26.04
100
19,200
52.03
011
9,600
104.16
010
4,800
208.33
001
2,400
416.66
000
1,200
833.33
DDIN
(input)
tDDIN
DDOUT
(output)
tDDOUT
(21) HSP interface parameter
Parameter
Note 1
SDO output delay time
Note 2
SDI setup time
Note 2
SDI hold time
Note 2
FS setup time
Note 2
FS hold time
Symbol
Condition
MIN.
tSDOD
tSDIS
Unit
15
ns
25
ns
tSDIH
0
ns
tFSIS
20
ns
tFSIH
0
ns
Notes 1. The reference clock of this parameter is the rising edge of HSPSCLK signal.
2. The reference clock of this parameter is the falling edge of HSPSCLK signal.
68
MAX.
Data Sheet U14691EJ1V0DS00
µPD30121
(22) SDRAM interface parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCLK clock cycle
tSCLK
13.7
ns
SCLK high-level width
tSCLKH
3.5
ns
SCLK low-level width
tSCLKL
3.5
ns
Data output delay time (from SCLK ↑ )
tDSM
1.1
10.7
ns
Address output delay time (from SCLK ↓ )
tDSA
−5.8
17.6
ns
WR# output delay time (from SCLK ↑ )
tDSW
1.1
24.5
Data input setup time
tSDS
Note
6.2
ns
Data input hold time
tSDH
Note
2.9
ns
ns
Note DATA (0:15) pins and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
tSCLKH
tSCLKL
tSCLK
SCLK (output)
tDSM
Note 1
tDSA
ADD (9:24), SCAS#,
SRAS# (output)
tDSW
WR# (output)
tSDS
tSDH
DATANote 2 (input)
Notes 1. MRAS (0:1)#, ROMCS (2:3)#, UUCAS#/MRAS3#, ULCAS#/MRAS2#, UCAS#, LCAS#, CKE, and
DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
2. DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
Remark The broken lines indicate high impedance.
Data Sheet U14691EJ1V0DS00
69
µPD30121
A/D Converter Characteristics (131 MHz model: TA = –10 to +70°°C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V
168 MHz model: TA = –10 to +70°°C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V)
Parameter
Symbol
Condition
Resolution
MIN.
TYP.
MAX.
Unit
10
Zero-scale error
Notes 1, 2
ZSE
Notes 1, 2
Full-scale error
Notes 1, 2
Integral linearity error
Differential linearity error
Notes 1, 2
Notes 1, 3
Analog input voltage
0
bit
±4.0
LSB
RSE
0
±5.0
LSB
INL
0
±3.0
LSB
DNL
0
±3.0
VIAN
–0.3
LSB
AVDD + 0.3
V
Notes 1. Applied to TPX (0:1), TPY (0:1), ADIN (0:2), and AUDIOIN pins.
2. Quantization error is excluded.
3. AVDD is a voltage on the AVDD pin that is VDD dedicated to the A/D converter.
D/A Converter Characteristics (131 MHz model: TA = –10 to +70°°C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V
168 MHz model: TA = –10 to +70°°C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V)
Parameter
Symbol
Condition
Resolution
MIN.
TYP.
MAX.
Unit
10
Notes 1, 2
Integral linearity error
Differential linearity error
Notes 1, 2
bit
INL
0
±3.0
LSB
DNL
0
±3.0
LSB
Notes 1. Applied to AUDIOOUT pin.
2. Quantization error is excluded.
Load Coefficient (Delay Time per Load Capacitance)
Parameter
Symbol
Condition
Rating
MIN.
Load coefficient
CLD
Unit
MAX.
5
ns/20 pF
Caution Because NEC confirmed the characteristics by simulation at the design phase, screening on
shipment is omitted.
70
Data Sheet U14691EJ1V0DS00
µPD30121
3. PACKAGE DRAWING
224-PIN PLASTIC FBGA (16x16)
A
W
S B
B
B
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
C D
V U T R P NM L K J HG F E D C B A
P
Index mark
Q
S A
W
J
Y1
R
I
S
H
S
ITEM
K
F
S
L
E
φM
M
G
S A B
MILLIMETERS
A
16.00±0.10
B
15.4
C
15.4
D
16.00±0.10
E
1.20
F
0.8 (T.P.)
G
0.35±0.1
H
0.36
I
0.96
J
1.31±0.15
K
0.10
L
φ 0.50 +0.05
−0.10
M
0.08
P
C1.0
Q
R0.3
R
25°
W
0.20
Y1
0.20
S224S1-80-3C-2
Data Sheet U14691EJ1V0DS00
71
µPD30121
4. RECOMMENDED SOLERING CONDITIONS
The µPD30121 should be soldered and mounted under the following recommended conditions.
For details of recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 4-1. Surface Mounting Type Soldering Conditions
µPD30121F1-131-GA1: 224-pin plastic FBGA (16 × 16)
µPD30121F1-168-GA1: 224-pin plastic FBGA (16 × 16)
Soldering
Method
Infrared reflow
Soldering Conditions
Package peak temperature: 230°C, Time: 30 seconds max. (at 210°C or
Note
higher), Count: 2 times max., Exposure limit: 3 days (after that, prebake at
Recommended
Condition Symbol
IR30-103-2
125°C for 10 to 72 hours.)
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or
Note
higher), Count: 2 times max. , Exposure limit: 3 days (after that, prebake at
VP15-103-2
125°C for 10 to 72 hours.)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
72
Data Sheet U14691EJ1V0DS00
µPD30121
[MEMO]
Data Sheet U14691EJ1V0DS00
73
µPD30121
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
74
Data Sheet U14691EJ1V0DS00
µPD30121
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U14691EJ1V0DS00
75
µPD30121
Reference document
Note
Electrical Characteristics for Microcomputer (IEI-601)
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
VR4120, VR4121, and VR Series are trademarks of NEC Corporation.
MIPS is a registered trademark of MIPS Technologies, Inc. in the United States.
The technology used for the HSP (Modem Interface Unit) incorporated in this product is the intellectual porperty
of the PC-TEL, Incorporated. The use of this interface in product development therefore requires the prior
approval of PC-TEL, Incorporated.
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
• The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4