NEC UPD75P3216

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P3216
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3216 replaces the µPD753208’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the µPD75P3216 supports programming by users, it is suitable for use in prototype testing for system
development using the µPD753204, 753206, or 753208, and for use in small-lot production.
The functions are explained in detail in the following user’s manual. Be sure to read this manual when
designing your system.
µPD753208 User’s Manual: U10158E
FEATURES
• Compatible with µPD753208
• Memory capacity:
• PROM : 16384 × 8 bits
• RAM
: 512 × 4 bits
• Can operate in same power supply voltage range as the mask version µPD753208
• VDD = 1.8 to 5.5 V
• LCD controller/driver
ORDERING INFORMATION
Part Number
µPD75P3216GT
Package
48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
Caution Mask-option pull-up resistors are not provided in this device.
The information in this document is subject to change without notice.
Document No. U10241EJ1V0DS00 (1st edition)
Date Published January 1997 N
Printed in Japan
The mark
shows major revised points.
'©
1995
1997
µPD75P3216
FUNCTION OUTLINE
Parameter
Function
Instruction execution time
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock)
Internal memory
PROM
16384 × 8 bits
RAM
512 × 4 bits
General-purpose register
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
CMOS input
6
Connecting on-chip pull-up resistors can be specified by software: 5
output
port
CMOS input/output
20
Connecting on-chip pull-up resistors can be specified by software: 20
Also used for segment pins: 8
N-ch open-drain I/O
4
13-V withstand
Total
30
LCD controller/driver
• Segment selection:
• Display mode selection:
4/8/12 segments (can be changed to CMOS input/
output port in 4-time units; max. 8)
Static
1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
Timer
5 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier
generator, timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
2
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)
• Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)
Buzzer output (BUZ)
• 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)
Vectored interrupts
External: 2, Internal: 5
Test input
External: 1, Internal: 1
System clock oscillator
Ceramic or crystal oscillator for system clock oscillation
Standby function
STOP/HALT mode
Power supply voltage
VDD = 1.8 to 5.5 V
Package
48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
µPD75P3216
CONTENTS
1. PIN CONFIGURATION (Top View) .................................................................................................... 4
2. BLOCK DIAGRAM .............................................................................................................................. 5
3. PIN FUNCTIONS ................................................................................................................................. 6
3.1
Port Pins ...................................................................................................................................................... 6
3.2
Non-port Pins .............................................................................................................................................. 7
3.3
Equivalent Circuits for Pins ...................................................................................................................... 8
3.4
Recommended Connection of Unused Pins ........................................................................................ 10
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................ 11
4.1
Difference between Mk I Mode and Mk II Mode ................................................................................... 11
4.2
Setting of Stack Bank Selection (SBS) Register ................................................................................. 12
5. Differences between µPD75P3216 and µPD753204, 753206, and 753208 ................................13
6. MEMORY CONFIGURATION ........................................................................................................... 14
7. INSTRUCTION SET ........................................................................................................................... 16
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................. 25
8.1
Operation Modes for Program Memory Write/Verify ........................................................................... 25
8.2
Program Memory Write Procedure ........................................................................................................ 26
8.3
Program Memory Read Procedure ........................................................................................................ 27
8.4
One-time PROM Screening ..................................................................................................................... 28
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 29
10. CHARACTERISTIC CURVE (REFERENCE VALUE) ...................................................................... 42
11. PACKAGE DRAWINGS .................................................................................................................... 44
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 45
APPENDIX A. µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST ........................................... 46
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 48
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 52
3
µPD75P3216
1. PIN CONFIGURATION (Top View)
• 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
µPD75P3216GT
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
VSS
P50/D4
P51/D5
P52/D6
P53/D7
P60/KR0/D0
P61/KR1/D1
P62/KR2/D2
P63/KR3/D3
VDD
X1
X2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
VPPNote
Note Be sure to connect VPP to VDD directly in normal operation mode.
PIN IDENTIFICATIONS
BIAS
BUZ
4
: LCD Power Supply Bias Control
PCL
: Buzzer Clock
PTO0-PTO2 : Programmable Timer Output 0 to 2
: Programmable Clock
COM0-COM3 : Common Output 0 to 3
RESET
: Reset Input
D0-D7
: Data Bus 0 to 7
S12-S23
: Segment Output 12 to 23
INT0, INT4
: External Vectored Interrupt 0, 4
SB0, SB1
: Serial Bus 0, 1
KR0-KR3
: Key Return 0 to 3
SCK
: Serial Clock
LCDCL
: LCD Clock
SI
: Serial Input
MD0-MD3
: Mode Selection 0 to 3
SO
: Serial Output
P00-P03
: Port0
SYNC
: LCD Synchronization
P10, P13
: Port1
TI0
: Timer Input 0
P20-P23
: Port2
VDD
: Positive Power Supply
P30-P33
: Port3
VLC0-VLC2
: LCD Power Supply 0 to 2
P50-P53
: Port5
VPP
: Programming Power Supply
P60-P63
: Port6
VSS
: Ground
P80-P83
: Port8
X1, X2
: System Clock Oscillation 1, 2
P90-P93
: Port9
µPD75P3216
2. BLOCK DIAGRAM
BUZ/P23
WATCH
TIMER
INTW fLCD
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
SP (8)
PROGRAM
COUNTER
TI0/P13
PTO1/P21
TOUT
PTO2/
PCL/P22
BANK
TOUT
INTT1
8-BIT
TIMER
CASCADED
COUNTER #1 16-BIT
TIMER
8-BIT
COUNTER
TIMER
COUNTER #2
INTT2
SI/SB1/P03
SO/SB0/P02
SCK/P01
SBS
8-BIT
TIMER/EVENT
COUNTER #0
INTT0
4
P00-P03
PORT1
2
P10, P13
PORT2
4
P20-P23
PORT3
4
P30/MD0P33/MD3
PORT5
4
P50/D4P53/D7
PORT6
4
P60/D0P63/D3
PORT8
4
P80-P83
PORT9
4
P90-P93
4
S12-S15
4
S16/P93S19/P90
4
S20/P83S23/P80
4
COM0-COM3
CY
ALU
INTBT
PTO0/P20
PORT0
GENERAL
REG.
PROM
PROGRAM
MEMORY
16384 × 8 BITS
DECODE
AND
CONTROL
CLOCKED
SERIAL
INTERFACE
DATA
MEMORY
(RAM)
512 × 4 BITS
INTCSI TOUT
INT0/P10
INT4/P00
LCD
CONTROLLER/
DRIVER
INTERRUPT
CONTROL
KR0/P60KR3/P63 4
BIT SEQ.
BUFFER (16)
fx/2 N
CLOCK
CLOCK
OUTPUT
DIVIDER
CONTROL
PCL/PTO2/P22
CPU CLOCK Φ
SYSTEM
CLOCK
GENERATOR
fLCD
STANDBY
CONTROL
X1 X2
VLC0
VLC1
VLC2
BIAS
LCDCL/P30
SYNC/P31
Vpp VDD VSS RESET
5
µPD75P3216
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name
I/O
Shared by
Function
8-bit
I/O
×
Status
I/O Circuit
After Reset TypeNote 1
P00
Input
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
<F>-B
P03
I/O
SI/SB1
<M>-C
P10
Input
P13
P20
INT0
TI0
I/O
PTO0
P21
PTO1
P22
PCL/PTO2
P23
BUZ
P30
I/O
LCDCL/MD0
P31
SYNC/MD1
P32
MD2
P33
MD3
P50Note 2
I/O
D4
P51Note 2
D5
P52Note 2
D6
P53Note 2
D7
P60
I/O
KR0/D0
P61
KR1/D1
P62
KR2/D2
P63
KR3/D3
P80
I/O
S23
P81
S22
P82
S21
P83
S20
P90
I/O
S19
P91
S18
P92
S17
P93
S16
This is a 4-bit input port (PORT0).
P01 to P03 are 3-bit pins for which an internal
pull-up resistor can be connected by software.
Input
<B>
<F>-A
This is a 1-bit input port (PORT1).
These are 1-bit pins for which an internal pull-up
resistor can be connected by software.
P10/INT0 can select noise elimination circuit.
×
Input
<B>-C
This is a 4-bit I/O port (PORT2).
These are 4-bit pins for which an internal pull-up
resistor can be connected by software.
×
Input
E-B
This is a programmable 4-bit I/O port (PORT3).
Input and output in single-bit units can be specified.
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
×
Input
E-B
This is an N-ch open-drain 4-bit I/O port (PORT5).
When set to open-drain, voltage is 13 V.
Also functions as data I/O pin (upper 4 bits)
for program memory (PROM) write/verify.
×
This is a programmable 4-bit I/O port (PORT6).
Input and output in single-bit units can be specified.
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
Also functions as data I/O pin (lower 4 bits) for
program memory (PROM) write/verify.
×
High
M-E
impedance
Input
<F>-A
This is a 4-bit I/O port (PORT8).
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
Input
H
This is a programmable 4-bit I/O port (PORT9).
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
Input
H
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.
2. Low level input current leakage increases when input instructions or bit manipulation instructions are
executed.
6
µPD75P3216
3.2 Non-port Pins
Pin Name
TI0
I/O
Input
Shared by
P13
Status
I/O Circuit
After Reset TypeNote 1
Function
External event pulse input to timer/event counter
Input
<B>-C
Timer/event counter output
Input
E-B
Input
<F>-A
PTO0
Output P20
PTO1
P21
PTO2
P22/PCL
PCL
P22/PTO2
Clock output
BUZ
P23
Any frequency output (for buzzer or system clock trimming)
P01
Serial clock I/O
SO/SB0
P02
Serial data output
Serial data bus I/O
<F>-B
SI/SB1
P03
Serial data input
Serial data bus I/O
<M>-C
SCK
I/O
Timer counter output
INT4
Input
P00
Edge detection vectored interrupt input
(detecting both rising and falling edges)
INT0
Input
P10
Edge detection vectored interrupt input
(detected edge is selectable). INT0/P10
can select noise elimination circuit
KR0 to KR3
Input
P60/D0-P63/D3
Falling edge detection testable input
X1
Input
—
X2
—
RESET
Input
MD0 to MD3
Input
D0 to D3
I/O
D4 to D7
—
Noise elimination
circuit/asynch
is selectable
Ceramic/crystal oscillation circuit connection for system
clock. If using an external clock, input to X1 and input
inverted phase to X2.
Input
<B>
Input
<B>-C
Input
<F>-A
—
—
—
<B>
P30 to P33
Mode selection for program memory (PROM) write/verify
Input
<F>-A
P60/KR0-P63/KR3
Data bus pin for program memory (PROM) write/verify.
Input
<F>-A
System reset input
P50 to P53
M-E
VPP
—
—
Programmable power supply voltage for program memory
(PROM) write/verify.
For normal operation, connect directly to VDD.
Apply +12.5 V for PROM write/verify.
—
—
VDD
—
—
Positive power supply
—
—
VSS
—
—
Ground
—
—
S12 to S15
Output
—
Segment signal output
Note 2
G-A
S16 to S19
Output P93 to P90
Segment signal output
Input
H
S20 to S23
P83 to P80
Common signal output
Note 2
G-B
COM0 to COM3 Output
VLC0 to VLC2
—
—
—
Power source for LCD drive
BIAS
Output
—
Output for external split resistor cut
LCDCLNote 4
Output P30/MD0
SYNCNote 4
P31/MD1
Clock output for driving external expansion driver
—
—
Note 3
—
Input
E-B
Clock output for synchronization of external expansion driver
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.
2. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.
S12 to S15: VLC1, COM1 to COM2: VLC2, COM3: VLC0
3. When the split resistor is incorporated
: Low level
When the split resistor is not incorporated : High impedance
4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
7
µPD75P3216
3.3 Equivalent Circuits for Pins
The equivalent circuits for the µPD75P3216’s pins are shown in abbreviated form below.
TYPE A
TYPE D
VDD
VDD
Data
P-ch
OUT
P-ch
IN
Output
disable
N-ch
CMOS standard input buffer
TYPE B
N-ch
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
P-ch
IN
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt trigger input with hysteresis characteristics.
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
P-ch
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
Output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
(Continued)
8
µPD75P3216
(Continued)
TYPE F-B
TYPE H
VDD
P.U.R.
P.U.R.
enable
P-ch
Output
disable
(P)
VDD
SEG
data
IN/OUT
Type G-A
P-ch
IN/OUT
Data
Output
disable
N-ch
Data
Output
disable
(N)
Output
disable
Type E-B
P.U.R. : Pull-Up Resistor
TYPE G-A
TYPE M-C
VDD
VLC0
P.U.R.
VLC1
P-ch
P.U.R.
enable
N-ch
P-ch
IN/OUT
OUT
SEG
data
Data
N-ch
Output
disable
N-ch
VLC2
N-ch
P.U.R. : Pull-Up Resistor
TYPE G-B
TYPE M-E
IN/OUT
VLC0
data
VLC1
output
disable
N-ch
(+13 V)
VDD
P-ch N-ch
input
instruction
P-ch
OUT
P.U.R.Note
COM
data
N-ch P-ch
VLC2
Voltage
control
circuit
(+13 V)
N-ch
Note This pull-up resistor is effective only when an input
instruction is executed (when the pin level is low,
current flows from VDD to the pin).
9
µPD75P3216
3.4 Recommended Connection of Unused Pins
Pin
Recommended Connection
P00/INT4
Connect to Vss or VDD
P01/SCK
Connect to Vss or VDD through a resistor individually
P02/SO/SB0
P03/SI/SB1
Connect to Vss
P10/INT0
Connect to Vss or VDD
P13/TI0
P20/PTO0
Input status : connect to Vss or VDD through a resistor individually
P21/PTO1
Output status: open
P22/PTO2/PCL
P23/BUZ
P30/MD0/LCDCL
P31/MD1/SYNC
P32/MD2
P33/MD3
P50/D4 to P53/D7
Connect to Vss
P60/KR0/D0 to P63/KR3/D3 Input status : connect to Vss or VDD through a resistor individually
Output status: open
S12 to S15
Open
COM0 to COM3
S16/P93 to S19/P90
Input status : connect to Vss or VDD through a resistor individually
S20/P83 to S23/P80
Output status: open
VLC0 to VLC2
Connect to Vss
BIAS
Connect to Vss only when VLC0 to VLC2 are all not used.
In other cases, leave open.
VPP
10
Be sure to connect VDD directly.
µPD75P3216
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the µPD75P3216 enables the program memory to be switched
between Mk I mode and Mk II mode. This function is applicable when using the µPD75P3216 to evaluate the µPD753204,
753206, or 753208.
When the SBS bit 3 is set to 1: sets Mk I mode (supports Mk I mode for µPD753204, 753206, and 753208)
When the SBS bit 3 is set to 0: sets Mk II mode (supports Mk II mode for µPD753204, 753206, and 753208)
4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3216.
Table 4-1. Difference between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC13-0
Program memory (bytes)
16384
Data memory (bits)
512 × 4
Stack
Stack bank
Selectable via memory banks 0, 1
No. of stack bytes
2 bytes
3 bytes
BRA !addr1 instruction
None
Provided
3 machine cycles
4 machine cycles
2 machine cycles
3 machine cycles
When set to Mk I mode:
µPD753204, 753206, and 753208
When set to Mk II mode:
µPD753204, 753206, and 753208
Instruction
CALLA !addr1 instruction
Instruction
CALL !addr instruction
execution time
CALLF !faddr instruction
Supported mask ROMs
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore,
when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine
cycle. Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
11
µPD75P3216
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for
doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 100XBNote at the beginning of the program. When using the Mk II
mode, be sure to initialize it to 000XBNote.
Note Set the desired value for X.
Figure 4-1. Format of Stack Bank Selection Register
Address
F84H
3
2
1
0
SBS3
SBS2
SBS1
SBS0
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
1
1
Setting prohibited
0
Be sure to enter “0” for bit 2.
Mode selection specification
0
Mk II mode
1
Mk I mode
Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When
using instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the
instructions.
2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.
12
µPD75P3216
5. DIFFERENCES BETWEEN µPD75P3216 AND µPD753204, 753206, AND 753208
The µPD75P3216 replaces the internal mask ROM in the µPD753204, 753206, and 753208 with a one-time PROM
and features expanded ROM capacity. The µPD75P3216’s Mk I mode supports the Mk I mode in the µPD753204, 753206,
and 753208 and the µPD75P3216’s Mk II mode supports the Mk II mode in the µPD753204, 753206, and 753208.
Table 5-1 lists differences among the µPD75P3216 and the µPD753204, 753206, and 753208. Be sure to check the
differences among these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For details on the CPU functions and internal hardware, refer to µPD753208 User’s Manual (U10158E).
Table 5-1. Differences between µPD75P3216 and µPD753204, 753206, and 753208
µPD753204
Item
µPD753206
µPD753208
µPD75P3216
Program counter
12 bits
13 bits
Program memory (bytes)
Mask ROM
4096
Mask ROM
6144
Data memory (× 4 bits)
512
Mask options
Pull-up resistor for
port 5
Yes (specifiable)
No (off chip)
Waiting time in
RESET
Yes (selectable from 217/fX and 215/fX)Note
No
(Fixed to 215/fX ms)
Pin 9 to 12
P30 to P33
P30/MD0-P33/MD3
Pin 14 to 17
P50 to P53
P50/D4-P53/D7
Pin 18 to 20
P60/KR0 to P63/KR3
P60/KR0/D0P63/KR3/D3
Pin 25
IC
VPP
Pin configuration
Other
14 bits
Mask ROM
8192
One-time PROM
16384
Noise resistance and noise radiation may differ due to the different circuit sizes and
mask layouts.
Note 217/fX = 21.8 ms (@6.0 MHz), 31.3 ms (@4.19 MHz)
215/fX = 5.46 ms (@6.0 MHz), 7.81 ms (@4.19 MHz)
Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask
ROM versions from the PROM version in a process between prototype development and full
production, be sure to fully evaluate the mask ROM version’s CS (not ES).
13
µPD75P3216
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
0000H
7
6
MBE
RBE
5
0
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
0004H
MBE
RBE
INT0 start address (upper 6 bits)
CALLF
!faddr instruction
entry address
INT0 start address (lower 8 bits)
0006H
0008H
MBE
RBE
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
000CH
MBE
RBE
INTT1/INTT2 start address (upper 6 bits)
INTT1/INTT2 start address (lower 8 bits)
BRCB
!caddr instruction
branch address
Branch addresses for
the following instructions
• BR !addr
• CALL !addr
• BRA !addr1 Note
• CALLA !addr1Note
• MOVT BCDE
• MOVT BCXA
Branch/call
address
by GETI
0020H
Reference table for GETI instruction
007FH
0080H
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
07FFH
0800H
0FFFH
1000H
BRCB
!caddr instruction
branch address
1FFFH
2000H
BRCB
!caddr instruction
branch address
2FFFH
3000H
BRCB
!caddr instruction
branch address
3FFFH
Note Can be used only in Mk II mode.
Remark
For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to
branch to addresses with changes in the PC’s lower 8 bits only.
14
µPD75P3216
Figure 6-2. Data Memory Map
Data memory
Memory bank
000H
(32 × 4)
General-purpose register area
01FH
020H
0
256 × 4
(224 × 4)
Stack area Note
Data area
static RAM
(512 × 4)
0FFH
100H
256 × 4
(236 × 4)
Display data memory (12 × 4)
1EBH
1ECH
1
(12 × 4)
1F7H
1F8H
(8 × 4)
1FFH
Not incorporated
F80H
128 × 4
Peripheral hardware area
15
FFFH
Note Memory bank 0 or 1 can be selected as the stack area.
15
µPD75P3216
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the
instruction’s operand representations (for further description, refer to RA75X Assembler Package User’s Manual
–Language (EEU-1343)). When there are several codes, select and use just one. Codes that consist of upper-case
letters and + or – symbols are key words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer
to µPD753208 User’s Manual (U10158E)). The number of labels that can be entered for fmem and pmem are
restricted.
Representation
Coding Format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL–, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or labelNote
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
0000H to 3FFFH immediate data or label
addr1
0000H to 3FFFH immediate data or label (Mk II mode only)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9
IEXXX
IEBT, IECSI, IET0, IET1, IET2, IE0, IE2, IE4, IEW
RBn
RB0 to RB3
MBn
MB0, MB1, MB15
Note When processing 8-bit data, only even-numbered addresses can be specified.
16
µPD75P3216
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA’
: Expansion register pair (XA’)
BC’
: Expansion register pair (BC’)
DE’
: Expansion register pair (DE’)
HL’
: Expansion register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IEXXX
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(XX)
: Addressed data
XXH
: Hexadecimal data
17
µPD75P3216
(3) Description of symbols used in addressing area
MB = MBE • MBS
*1
MBS = 0, 1, 15
MB = 0
*2
MBE = 0
: MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
*3
MBE = 1
Data memory
addressing
: MB = MBS
MBS = 0, 1, 15
*4
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3FFFH
addr, addr1 = (Current PC) – 15 to (Current PC) – 1
*7
(Current PC) +2 to (Current PC) +16
caddr = 0000H to 0FFFH (PC13, 12 = 00B) or
1000H to 1FFFH (PC13, 12 = 01B) or
*8
2000H to 2FFFH (PC13, 12 = 10B) or
Program memory
addressing
3000H to 3FFFH (PC13, 12 = 11B)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
*11
addr1 = 0000H to 3FFFH (Mk II mode only)
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies
as shown below.
• No skip .................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction .. S = 1
• Skipped instruction is 3-byte instructionNote ........... S = 2
Note
3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1
Caution The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock F. Use the PCC setting to select among four cycle
times.
18
µPD75P3216
Instruction
Group
Transfer
Mnemonic
MOV
XCH
Table
reference
MOVT
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
A, #n4
1
1
A←n4
String-effect A
reg1, #n4
2
2
reg1←n4
XA, #n8
2
2
XA←n8
String-effect A
HL, #n8
2
2
HL←n8
String-effect B
rp2, #n8
2
2
rp2←n8
A, @HL
1
1
A←(HL)
*1
A, @HL+
1
2+S
A←(HL), then L←L+1
*1
L=0
A, @HL–
1
2+S
A←(HL), then L←L–1
*1
L=FH
A, @rpa1
1
1
A←(rpa1)
*2
XA, @HL
2
2
XA←(HL)
*1
@HL, A
1
1
(HL)←A
*1
@HL, XA
2
2
(HL)←XA
*1
A, mem
2
2
A←(mem)
*3
XA, mem
2
2
XA←(mem)
*3
mem, A
2
2
(mem)←A
*3
mem, XA
2
2
(mem)←XA
*3
A, reg
2
2
A←reg
XA, rp’
2
2
XA←rp’
reg1, A
2
2
reg1←A
rp’1, XA
2
2
rp’1←XA
A, @HL
1
1
A↔(HL)
*1
A, @HL+
1
2+S
A↔(HL), then L←L+1
*1
L=0
A, @HL–
1
2+S
A↔(HL), then L←L–1
*1
L=FH
A, @rpa1
1
1
A↔(rpa1)
*2
XA, @HL
2
2
XA↔(HL)
*1
A, mem
2
2
A↔(mem)
*3
XA, mem
2
2
XA↔(mem)
*3
A, reg1
1
1
A↔reg1
XA, rp’
2
2
XA↔rp’
XA, @PCDE
1
3
XA←(PC13-8+DE)ROM
XA, @PCXA
1
3
XA←(PC13-8+XA)ROM
XA, @BCDENote
1
3
XA←(B2-0+BCDE)ROM
*6
XA, @BCXANote
1
3
XA←(B2-0+BCXA)ROM
*6
Note Only the lower 2 bits in the B register are valid.
19
µPD75P3216
Instruction
Group
Bit transfer
Arithmetic
Mnemonic
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
CY, fmem.bit
2
2
CY←(fmem.bit)
*4
CY, [email protected]
2
2
CY←(pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY←(H+mem3-0.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)←CY
*4
[email protected], CY
2
2
(pmem7-2+L3-2.bit(L1-0))←CY
*5
@H+mem.bit, CY
2
2
(H+mem3-0.bit)←CY
*1
A, #n4
1
1+S
A←A+n4
carry
XA, #n8
2
2+S
XA←XA+n8
carry
A, @HL
1
1+S
A←A+(HL)
XA, rp’
2
2+S
XA←XA+rp’
carry
rp’1, XA
2
2+S
rp’1←rp’1+XA
carry
A, @HL
1
1
A, CY←A+(HL)+CY
XA, rp’
2
2
XA, CY←XA+rp’+CY
rp’1, XA
2
2
rp’1, CY←rp’1+XA+CY
A, @HL
1
1+S
A←A–(HL)
XA, rp’
2
2+S
XA←XA–rp’
borrow
rp’1, XA
2
2+S
rp’1←rp’1–XA
borrow
A, @HL
1
1
A, CY←A–(HL)–CY
XA, rp’
2
2
XA, CY←XA–rp’–CY
rp’1, XA
2
2
rp’1, CY←rp’1–XA–CY
A, #n4
2
2
A←A∧n4
A, @HL
1
1
A←A∧(HL)
XA, rp’
2
2
XA←XA∧rp’
rp’1, XA
2
2
rp’1←rp’1∧XA
A, #n4
2
2
A←A∨n4
A, @HL
1
1
A←A∨(HL)
XA, rp’
2
2
XA←XA∨rp’
rp’1, XA
2
2
rp’1←rp’1∨XA
A, #n4
2
2
A←A∨n4
A, @HL
1
1
A←A∨(HL)
XA, rp’
2
2
XA←XA∨rp’
rp’1, XA
2
2
rp’1←rp’1∨XA
*1
carry
*1
*1
borrow
*1
*1
*1
*1
Accumulator
manipulation
RORC
A
1
1
CY←A0, A3←CY, An-1←An
NOT
A
2
2
A←A
Increment/
decrement
INCS
reg
1
1+S
reg←reg+1
reg=0
rp1
1
1+S
rp1←rp1+1
rp1=00H
@HL
2
2+S
(HL)←(HL)+1
*1
(HL)=0
mem
2
2+S
(mem)←(mem)+1
*3
(mem)=0
reg
1
1+S
reg←reg–1
reg=FH
rp’
2
2+S
rp’←rp’–1
rp’=FFH
DECS
20
µPD75P3216
Instruction
Group
Comparison
Carry flag
manipulation
Memory bit
manipulation
Mnemonic
SKE
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
reg, #n4
2
2+S
Skip if reg=n4
@HL, #n4
2
2+S
Skip if(HL)=n4
*1
(HL)=n4
A, @HL
1
1+S
Skip if A=(HL)
*1
A=(HL)
XA, @HL
2
2+S
Skip if XA=(HL)
*1
XA=(HL)
A, reg
2
2+S
Skip if A=reg
A=reg
XA, rp’
2
2+S
Skip if XA=rp’
XA=rp’
SET1
CY
1
1
CY←1
CLR1
CY
1
1
CY←0
SKT
CY
1
1+S
NOT1
CY
1
1
CY←CY
SET1
mem.bit
2
2
(mem.bit)←1
*3
fmem.bit
2
2
(fmem.bit)←1
*4
[email protected]
2
2
(pmem7-2+L3-2.bit(L1-0))←1
*5
@H+mem.bit
2
2
(H+mem3-0.bit)←1
*1
mem.bit
2
2
(mem.bit)←0
*3
fmem.bit
2
2
(fmem.bit)←0
*4
[email protected]
2
2
(pmem7-2+L3-2.bit(L1-0))←0
*5
@H+mem.bit
2
2
(H+mem3-0.bit)←0
*1
mem.bit
2
2+S
Skip if(mem.bit)=1
*3
(mem.bit)=1
fmem.bit
2
2+S
Skip if(fmem.bit)=1
*4
(fmem.bit)=1
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit(L1-0))=1
*5
([email protected])=1
@H+mem.bit
2
2+S
Skip if(H+mem3-0.bit)=1
*1
(@H+mem.bit)=1
mem.bit
2
2+S
Skip if(mem.bit)=0
*3
(mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=0
*4
(fmem.bit)=0
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit(L1-0))=0
*5
([email protected])=0
@H+mem.bit
2
2+S
Skip if(H+mem3-0.bit)=0
*1
(@H+mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=1 and clear
*4
(fmem.bit)=1
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear
*5
([email protected])=1
@H+mem.bit
2
2+S
Skip if(H+mem3-0.bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY←CY∧(fmem.bit)
*4
CY, [email protected]
2
2
CY←CY∧(pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY←CY∧(H+mem3-0.bit)
*1
CY, fmem.bit
2
2
CY←CY∨(fmem.bit)
*4
CY, [email protected]
2
2
CY←CY∨(pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY←CY∨(H+mem3-0.bit)
*1
CY, fmem.bit
2
2
CY←CY∨ (fmem.bit)
*4
CY, [email protected]
2
2
CY←CY∨(pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY←CY∨(H+mem3-0.bit)
*1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
reg=n4
Skip if CY=1
CY=1
21
µPD75P3216
Instruction
Group
Branch
Mnemonic
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
addr
—
—
PC13-0←addr
Use the assembler to select the
most appropriate instruction
among the following.
• BR !addr
• BRCB !caddr
• BR $addr
*6
addr1
—
—
PC13-0←addr1
Use the assembler to select
the most appropriate instruction
among the following.
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
*11
!addr
3
3
PC13-0←addr
*6
$addr
1
2
PC13-0←addr
*7
$addr1
1
2
PC13-0←addr1
PCDE
2
3
PC13-0←PC13-8+DE
PCXA
2
3
PC13-0←PC13-8+XA
BCDE
2
3
PC13-0←BCDE
*6
BCXA
2
3
PC13-0←BCXA
*6
BRANote
!addr1
3
3
PC13-0←addr1
*11
BRCB
!caddr
2
2
PC13-0←PC13, 12+caddr11-0
*8
BRNote
Skip
Condition
Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
22
µPD75P3216
Instruction
Group
Subroutine
stack control
Mnemonic
Operand
No. of Machine
Bytes Cycle
Operation
CALLANote !addr1
3
3
(SP–6)(SP–3)(SP–4)←PC11-0
(SP–5)←0, 0, PC13, 12
(SP–2)←X, X, MBE, RBE
PC13–0←addr1, SP←SP–6
CALLNote
3
3
(SP–4)(SP–1)(SP–2)←PC11-0
(SP–3)←MBE, RBE, PC13, 12
PC13–0←addr, SP←SP–4
4
(SP–6)(SP–3)(SP–4)←PC11-0
(SP–5)←0, 0, PC13, 12
(SP–2)←X, X, MBE, RBE
PC13-0←addr, SP←SP–6
2
(SP–4)(SP–1)(SP–2)←PC11-0
(SP–3)←MBE, RBE, PC13, 12
PC13-0←000+faddr, SP←SP–4
3
(SP–6)(SP–3)(SP–4)←PC11-0
(SP–5)←0, 0, PC13, 12
(SP–2)←X, X, MBE, RBE
PC13-0←000+faddr, SP←SP–6
3
MBE, RBE, PC13, 12←(SP+1)
PC11-0←(SP)(SP+3)(SP+2)
SP←SP+4
!addr
CALLFNote !faddr
RETNote
2
1
Addressing
Area
Skip
Condition
*6
*9
X, X, MBE, RBE←(SP+4)
PC11-0←(SP)(SP+3)(SP+2)
MBE, 0, PC13, 12←(SP+1)
SP←SP+6
RETSNote
1
3+S
MBE, RBE, PC13, 12←(SP+1)
PC11-0←(SP)(SP+3)(SP+2)
SP←SP+4
then skip unconditionally
Unconditional
X, X, MBE, RBE←(SP+4)
PC11-0←(SP)(SP+3)(SP+2)
0, 0, PC13, 12←(SP+1)
SP←SP+6
then skip unconditionally
RETINote
1
3
MBE, RBE, PC13, 12←(SP+1)
PC11-0←(SP)(SP+3)(SP+2)
PSW←(SP+4)(SP+5), SP←SP+6
0, 0, PC13, 12←(SP+1)
PC11-0←(SP)(SP+3)(SP+2)
PSW←(SP+4)(SP+5), SP←SP+6
PUSH
POP
rp
1
1
(SP–1)(SP–2)←rp, SP←SP–2
BS
2
2
(SP–1)←MBS, (SP–2)←RBS, SP←SP–2
rp
1
1
rp←(SP+1)(SP), SP←SP+2
BS
2
2
MBS←(SP+1), RBS←(SP), SP←SP+2
Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
23
µPD75P3216
Instruction
Group
Interrupt
control
Mnemonic
Operand
EI
2
IME(IPS.3)←1
2
2
IEXXX←1
2
2
IME(IPS.3)←0
IEXXX
2
2
IEXXX←0
A, PORTn
2
2
A←PORTn
XA, PORTn
2
2
XA←PORTn+1, PORTn(n=8)
PORTn, A
2
2
PORTn←A
PORTn, XA
2
2
PORTn+1, PORTn←XA(n=8)
HALT
2
2
Set HALT Mode(PCC.2←1)
STOP
2
2
Set STOP Mode(PCC.3←1)
NOP
1
1
No Operation
RBn
2
2
RBS←n (n=0-3)
MBn
2
2
MBS←n (n=0, 1, 15)
GETINote 2, 3 taddr
1
3
• When using TBR instruction
DI
INNote 1
OUTNote 1
CPU control
Special
Operation
2
IEXXX
I/O
No. of Machine
Bytes Cycle
SEL
Addressing
Area
Skip
Condition
(n=0-3, 5, 6, 8, 9)
(n=2-3, 5, 6, 8, 9)
*10
PC13-0←(taddr)5-0+(taddr+1)
---------------------------
------------
• When using TCALL instruction
(SP–4)(SP–1)(SP–2)←PC11-0
(SP+1)←MBE, RBE, PC13, 12
PC13-0←(taddr)5-0+(taddr+1)
SP←SP–4
---------------------------
------------
• When using instruction other than
1
3
TBR or TCALL
referenced
Execute (taddr)(taddr+1) instructions
instruction
• When using TBR instruction
PC13-0←(taddr)5-0+(taddr+1)
-------------------------------4
Determined by
*10
------------
• When using TCALL instruction
(SP–6)(SP–3)(SP–4)←PC11-0
(SP–2)←X, X, MBE, RBE
PC13-0←(taddr)5-0+(taddr+1)
SP←SP–6
-------------------------------3
• When using instruction other than
-----------Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr+1) instructions
instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBE to 15.
2. TBR and TCALL instructions are assembler directives for the GETI instruction’s table definitions.
3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
24
µPD75P3216
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory contained in the µPD75P3216 is a 16384 × 8-bit one-time PROM that can be electrically written
one time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the
X1 pin is used instead of address input as a method for updating addresses.
Pin
Caution
Function
VPP
Pin where program voltage is applied during program
memory write/verify (usually VDD potential)
X1, X2
Clock input pins for address updating during program
memory write/verify. Input the X1 pin’s inverted signal to
the X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/
verify
D0/P60/KR0-D3/P63/KR3 (lower 4 bits)
D4/P50-D7/P53 (upper 4 bits)
8-bit data I/O pins for program memory write/verify
VDD
Pin where power supply voltage is applied. Applies 1.8 to
5.5 V in normal operation mode and +6 V for program
memory write/verify.
Pins not used for program memory write/verify should be connected to Vss.
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P3216 enters the program memory write/
verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation Mode Specification
Operation Mode
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
X
H
H
Program inhibit mode
X: L or H
25
µPD75P3216
8.2 Program Memory Write Procedure
Program memory can be written at high speed using the following procedure.
(1) Pull down unused pins to Vss through resistors. Set the X1 pin low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Select the zero-clear program memory address mode.
(5) Supply 6 V to the VDD and 12.5 V to the VPP pins.
(6) Write data in the 1 ms write mode.
(7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7).
(8) (X : number of write operations from steps (6) and (7)) × 1 ms additional write.
(9) Apply four pulses to the X1 pin to increment the program memory address by one.
(10) Repeat steps (6) to (9) until the end address is reached.
(11) Select the zero-clear program memory address mode.
(12) Return the VDD and VPP pins back to 5 V.
(13) Turn off the power.
The following figure shows steps (2) to (9).
X repetitions
Write
Verify
Additional
write
VPP
VPP
VDD
VDD + 1
VDD VDD
X1
D0/P60/KR0D3/P63/KR3
D4/P50D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
26
Data input
Data
output
Data input
Address
increment
µPD75P3216
8.3 Program Memory Read Procedure
The µPD75P3216 can read program memory contents using the following procedure.
(1) Pull down unused pins to VSS through resistors. Set the X1 pin low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Select the zero-clear program memory address mode.
(5) Supply 6 V to the VDD and 12.5 V to the VPP pins.
(6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one
address.
(7) Select the zero-clear program memory address mode.
(8) Return the VDD and VPP pins back to 5 V.
(9) Turn off the power.
The following figure shows steps (2) to (9).
VPP
VPP
VDD
VDD + 1
VDD VDD
X1
D0/P60/KR0D3/P63/KR3
D4/P50D7/P53
Data output
Data output
MD0/P30
MD1/P31
“L”
MD2/P32
MD3/P33
27
µPD75P3216
8.4 One-time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
that after the required data is written and the PROM is stored under the temperature and time conditions shown below,
the PROM should be verified via a screening.
28
Storage Temperature
Storage Time
125 ˚C
24 hours
µPD75P3216
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Parameter
Symbol
Test Conditions
Rating
Unit
Supply voltage
V DD
–0.3 to +7.0
V
PROM supply voltage
V PP
–0.3 to +13.5
V
Input voltage
V I1
Except port 5
–0.3 to VDD + 0.3
V
V I2
Port 5
–0.3 to +14
V
–0.3 to V DD + 0.3
V
Per pin
–10
mA
Total for all pins
–30
mA
Per pin
30
mA
Total for all pins
220
mA
TA
–40 to +85Note
˚C
T stg
–65 to +150
˚C
Output voltage
VO
Output current, high
IOH
Output current, low
Operating ambient
IOL
N-ch open-drain
temperature
Storage temperature
Note
When LCD is driven in normal mode: TA = –10 to +85 ˚C
Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding
the ratings could cause parmanent damage. The parameters apply independently. The device
should be operated within the limits specified under DC and AC Characteristics.
CAPACITANCE (TA = 25 ˚C, V DD = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz
15
pF
Output capacitance
COUT
Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
CIO
15
pF
29
µPD75P3216
SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Resonator
Recommended Constant
Ceramic
resonator
frequency (fx)
C1
C2
resonator
Oscillation
frequency (fx)
C1
C2
Note 3
Note 2
Unit
MHz
ms
lation voltage range MIN.
6.0
Note 2
MHz
Note 1
Oscillation
VDD = 4.5 to 5.5 V
10
Note 3
X1 input
clock
frequency (fx) Note 1
X2
6.0
4
1.0
External
X1
MAX.
After VDD reaches oscil-
stabilization time
VDD
TYP.
1.0
Oscillator
X2
X1
MIN.
Note 1
stabilization time
VDD
Crystal
Test Conditions
Oscillator
X2
X1
Parameter
X1 input
ms
30
1.0
83.3
6.0
Note 2
500
MHz
ns
high/low level width
(t XH, tXL)
Notes 1.
The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to the AC characteristics.
2.
When the oscillator frequency is 4.19 MHz < fx ≤ 6.0 MHz, setting the processor clock control register
(PCC) to 0011 results in 1 machine cycle being less than the required 0.95 µs. Therefore, set PCC
to a value other than 0011.
3.
The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing
the STOP mode.
Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should be
carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
30
µPD75P3216
DC CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
Output current, low
Input voltage, high
Symbol
IOL
VIH1
VIH2
VIH3
Input voltage, low
Test Conditions
MAX.
Unit
Per pin
15
mA
Total for all pins
150
mA
Ports 2, 3, 8, 9
Ports 0, 1, 6, RESET
Port 5
N-ch open-drain
VI14
X1
VIL1
Ports 2, 3, 5, 8, 9
VIL2
Ports 0, 1, 6, RESET
MIN.
TYP.
2.7 ≤ VDD ≤ 5.5 V
0.7V DD
VDD
V
1.8 ≤ V DD < 2.7 V
0.9V DD
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0.8V DD
VDD
V
1.8 ≤ V DD < 2.7 V
0.9V DD
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0.7V DD
13
V
1.8 ≤ V DD < 2.7 V
0.9V DD
13
V
VDD – 0.1
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.3V DD
V
1.8 ≤ V DD < 2.7 V
0
0.1V DD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.2V DD
V
1.8 ≤ V DD < 2.7 V
0
0.1V DD
V
0
0.1
V
VIL3
X1
Output voltage, high
VOH
SCK, SO, ports 2, 3, 6, 8, 9 IOH = –1 mA
Output voltage, low
VOL1
SCK, SO, ports 2, 3, 5, 6, 8, 9
VDD – 0.5
IOL = 15 mA,
V
0.2
2.0
V
0.4
V
0.2V DD
V
VDD = 4.5 to 5.5 V
IOL = 1.6 mA
VOL2
SB0, SB1
N-ch open-drain pull-up resistor ≥ 1 kΩ
Input leakage
ILIH1
VIN = V DD
Other pins than X1
3
µA
current, high
ILIH2
X1
20
µA
ILIH3
VIN = 13 V
Port 5 (N-ch open-drain)
20
µA
Input leakage
ILIL1
VIN = 0 V
Other pins than port 5 and X1
–3
µA
current, low
ILIL2
X1
–20
µA
ILIL3
Port 5 (N-ch open-drain) When an
–3
µA
–30
µA
input instruction is not executed
Port 5 (N-ch
open-drain)
When an input
VDD = 5.0 V
–10
–27
µA
instruction
VDD = 3.0 V
–3
–8
µA
is executed
Output leakage
ILOH1
VOUT = VDD
SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9
3
µA
current, high
ILOH2
VOUT = 13 V
Port 5 (N-ch open-drain)
20
µA
Output leakage
ILOL
VOUT = 0 V
–3
µA
RL
VIN = 0 V
200
kΩ
current, low
Pull-up resistor
Ports 0, 1, 2, 3, 6, 8, 9
50
100
(Excluding P00 pin)
31
µPD75P3216
DC CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
LCD drive voltage
Symbol
VLCD
Test Conditions
VAC0 = 0
MIN.
VDD
V
T A = –10 to +85 °C
2.2
VDD
V
1.8
VDD
V
4
µA
0
±0.2
V
0
±0.2
V
IVAC
VAC0 = 1, V DD = 2.0 V ± 10%
LCD output voltage
VODC
lo = ±1 µA
deviation
Note 1
VLCD1 = VLCD × 2/3
VODS
lo = ±0.5 µA
VLCD2 = VLCD × 1/3
2.2 V ≤ VLCD ≤ V DD
(segment)
Supply current
Note 2
IDD1
IDD2
Note 1
6.0 MHz
VDD = 5.0 V ± 10%
Note 3
2.6
7.8
mA
Crystal oscillation
VDD = 3.0 V ± 10%
Note 4
0.47
1.4
mA
C1 = C2 = 22 pF
HALT mode
VDD = 5.0 V ± 10%
0.72
2.1
mA
VDD = 3.0 V ± 10%
0.27
0.8
mA
1.9
5.7
mA
0.36
1.1
mA
VDD = 5.0 V ± 10%
0.7
2.0
mA
VDD = 3.0 V ± 10%
0.23
0.7
mA
VDD = 5.0 V ± 10%
0.05
10
µA
VDD = 3.0 V
0.02
5
µA
0.02
3
µA
4.19 MHz
VDD = 5.0 V ± 10%
Note 3
Crystal oscillation
VDD = 3.0 V ± 10%
Note 4
IDD2
C1 = C2 = 22 pF
HALT mode
IDD5
Note 5
IDD1
STOP mode
±10%
Notes 1.
1
VLCD0 = VLCD
(common)
LCD output voltage
Unit
2.7
VAC current
deviation
MAX.
T A = –40 to +85 °C
VAC0 = 1
Note 1
TYP.
TA = 25˚C
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
2.
Not including current flowing in on-chip pull-up resistors.
3.
When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode.
4.
5.
When PCC is set to 0000 and the device is operated in the low-speed mode.
Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1
µA.
32
µPD75P3216
AC CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
CPU clock cycle
time
tCY
Test Conditions
MIN.
VDD = 2.7 to 5.5 V
Note 1
TI0 input frequency
fTI
TI0 input
tTIH, t TIL
VDD = 2.7 to 5.5 V
tINTH, t INTL
Notes 1.
Unit
0.67
64
µs
0.95
64
µs
0
1
MHz
0
275
kHz
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
INT4
10
µs
KR0 to KR3
10
µs
10
µs
INT0
low-level width
RESET low level width
MAX.
0.48
VDD = 2.7 to 5.5 V
high/low-level width
Interrupt input high/
TYP.
tRSL
The cycle time (minimum instruction
tCY vs VDD
execution time) of the CPU clock
64
30
(Φ) is determined by the oscillation
frequency of the connected
6
the processor clock control register
5
(PCC).
The figure at the right
indicates the cycle time tCY versus
supply voltage V DD characteristic.
2.
2t CY or 128/fx is set by setting the
interrupt mode register (IM0).
Cycle Time tCY [ µ s]
resonator (and external clock) and
Guaranteed Operation
Range
4
3
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
33
µPD75P3216
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
tKCY1
tKL1, t KH1
Test Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI
Note 1
setup time
tSIK1
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
tKSI1
VDD = 2.7 to 5.5 V
(from SCK↑)
SO
Note 1
output delay time
tKSO1
from SCK↓
Notes 1.
2.
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
Note 2
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY1/2–50
ns
tKCY1/2–150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
In the 2-wire serial I/O mode, read SB0 or SB1 instead.
RL and C L are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
tKCY2
tKL2, t KH2
Test Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SINote 1 setup time
tSIK2
VDD = 2.7 to 5.5 V
(to SCK↑)
SINote 1 hold time
tKSI2
VDD = 2.7 to 5.5 V
(from SCK↑)
SONote 1 output delay time
from SCK↓
Notes 1.
2.
34
tKSO2
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
Note 2
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
In the 2-wire serial I/O mode, read SB0 or SB1 instead.
RL and C L are the load resistance and load capacitance of the SO output lines.
µPD75P3216
SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
tKCY3
tKL3, t KH3
Test Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SB0, 1 setup time
tSIK3
VDD = 2.7 to 5.5 V
(to SCK↑)
SB0, 1 hold time (from SCK↑)
tKSI3
VDD = 2.7 to 5.5 V
SB0, 1 output delay
tKSO3
RL = 1 kΩ,Note
time from SCK↓
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY3/2–50
ns
tKCY3/2–150
ns
150
ns
500
ns
t KCY3/2
ns
0
250
ns
0
1000
ns
SB0, 1↓ from SCK↑
tKSB
tKCY3
ns
SCK↓ from SB0, 1↑
tSBK
tKCY3
ns
SB0, 1 low-level width
tSBL
tKCY3
ns
SB0, 1 high-level width
tSBH
tKCY3
ns
Note
RL and C L are the load resistance and load capacitance of the SB0 and SB1 output lines.
SBI Mode (SCK...External clock input (slave)): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
tKCY4
tKL4, t KH4
Test Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SB0, 1 setup time
tSIK4
VDD = 2.7 to 5.5 V
(to SCK↑)
SB0, 1 hold time (from SCK↑)
SB0, 1 output delay
tKSI4
tKSO4
time from SCK↓
VDD = 2.7 to 5.5 V
RL = 1 kΩ,
Note
CL = 100 pF
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
t KCY4/2
ns
0
300
ns
0
1000
ns
SB0, 1↓ from SCK↑
tKSB
tKCY4
ns
SCK↓ from SB0, 1↑
tSBK
tKCY4
ns
SB0, 1 low-level width
tSBL
tKCY4
ns
SB0, 1 high-level width
tSBH
tKCY4
ns
Note
RL and C L are the load resistance and load capacitance of the SB0 and SB1 output lines.
35
µPD75P3216
AC Timing Test Point (Excluding X1 Input)
VIH (MIN.)
VIH (MIN.)
VIL (MAX.)
VIL (MAX.)
VOH (MIN.)
VOH (MIN.)
VOL (MAX.)
VOL (MAX.)
Clock Timing
1/fX
tXL
tXH
VDD–0.1 V
0.1 V
X1 Input
TI0 Timing
1/fTI
tTIL
TI0
36
tTIH
µPD75P3216
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SI
tKSI1, 2
Input Data
tKSO1, 2
SO
Output Data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
37
µPD75P3216
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INTP0, 4
KR0 to 3
RESET input timing
tRSL
RESET
38
tKSI3, 4
tKSI3, 4
µPD75P3216
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85 ˚C)
Parameter
Symbol
Release signal set time
Oscillation stabilization
wait time
Notes 1.
Test Conditions
MIN.
tSREL
tWAIT
Note 1
TYP.
MAX.
Unit
µs
0
15
Release by RESET
2 /f X
ms
Release by interrupt
Note 2
ms
The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2.
Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
Wait Time
When fx = 4.19-MHz operation
20
When fx = 6.0-MHz operation
—
0
0
0
2 /fx (approx. 250 ms)
220/fx (approx. 175 ms)
—
0
1
1
217/fx (approx. 31.3 ms)
217/fx (approx. 21.8 ms)
—
1
0
1
215/fx (approx. 7.81 ms)
215/fx (approx. 5.46 ms)
—
1
1
1
213/fx (approx. 1.95 ms)
213/fx (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
39
µPD75P3216
DC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0V)
Parameter
Symbol
Input voltage, high
Input voltage, low
Test Conditions
MIN.
MAX.
Unit
VDD
V
VDD – 0.5
VDD
V
0
0.3 VDD
V
0
0.4
V
10
µA
V IH1
Other than X1, X2 pins
0.7 VDD
V IH2
X1, X2
V IL1
Other than X1, X2 pins
V IL2
X1, X2
Input leakage current
I LI
VIN = VIL or V IH
Output voltage, high
V OH
I OH = – 1 mA
Output voltage, low
V OL
I OL = 1.6 mA
VDD supply current
I DD
VPP supply current
I PP
TYP.
VDD – 1.0
V
MD0 = V IL, MD1 = VIH
0.4
V
30
mA
30
mA
Cautions 1. Keep V PP to within +13.5 V, including overshoot.
2. Apply V DD before VPP and turn it off after V PP.
AC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0 V)
Parameter
Symbol
Note 1
t AS
t AS
2
µs
MD1 setup time (vs. MD0 ↓)
t M1S
t OES
2
µs
Data setup time (vs. MD0 ↓)
t DS
t DS
2
µs
t AH
t AH
2
µs
Data hold time (vs. MD0 ↑)
t DH
t DH
2
MD0 ↑ → data output float
delay time
tDF
tDF
0
VPP setup time (vs. MD3 ↑)
t VPS
t VPS
2
VDD setup time (vs. MD3 ↑)
t VDS
t VCS
2
Initial program pulse width
tPW
tPW
0.95
Additional program pulse width
t OPW
t OPW
0.95
MD0 setup time (vs. MD1 ↑)
t M0S
t CES
2
MD0 ↓ → data output delay time
t DV
t DV
MD0 = MD1 = VIL
MD1 hold time (vs. MD0 ↑)
t M1H
t OEH
t M1H + tM1R ≥ 50 µs
MD1 recovery time (vs. MD0 ↓)
t M1R
tOR
Program counter reset time
t PCR
—
X1 input high-, low-level width
t XH, tXL
—
0.125
X1 input frequency
fX
—
Initial mode set time
t1
—
2
µs
MD3 setup time (vs. MD1 ↑)
t M3S
—
2
µs
MD3 hold time (vs. MD1 ↓)
t M3H
—
2
µs
MD3 setup time (vs. MD0 ↓)
t M3SR
—
2
µs
Address setup time
(vs. MD0 ↓)
Address hold time
(vs. MD0 ↑)
Note 2
Note 2
Test Conditions
MIN.
ms
21.0
ms
µs
µs
2
µs
µs
Address Note 2 → data output
hold time
t HAD
tOH
When program memory is read
0
MD3 hold time (vs. MD0 ↑)
t M3HR
—
When program memory is read
2
MD3 ↓ → data output float
delay time
tDFR
—
When program memory is read
µs
MHz
2
µs
130
ns
µs
2
µs
Symbol of corresponding µ PD27C256A
The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not
connected to a pin.
40
1.05
10
When program memory is read
2.
µs
1.0
µs
t ACC
Notes 1.
ns
µs
4.19
When program memory is read
Unit
µs
130
1
t DAD
Address
delay time
MAX.
2
→ data output
Note 2
TYP.
µPD75P3216
Program Memory Write Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
X1
D0/P60/KR0D3/P63/KR3
D4/P50D7/P53
tXL
Data input
Data output
Data input
tDS
tI
tDS
tDH
tDV
Data input
tDH
tDF
tAH
tAS
MD0/P30
tPW
tM1R
tM0S
tOPW
MD1/P31
tPCR
tM1S
tM1H
MD2/P32
tM3S
tM3H
MD3/P33
Program Memory Read Timing
tVPS
VPP
VPP
VDD
tVDS
VDD+1
VDD
tXH
VDD
X1
tXL
tDAD
tHAD
D0/P60/KR0D3/P63/KR3
D4/P50D7/P53
Data output
Data output
tDV
tI
tDFR
tM3HR
MD0/P30
MD1/P31
tPCR
MD2/P32
tM3SR
MD3/P33
41
µPD75P3216
10. CHARACTERISTIC CURVE (REFERENCE VALUE)
IDD vs VDD (System clock : 6.0 MHz Crystal resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
HALT mode
1.0
Supply Current IDD (mA)
0.5
0.1
0.05
0.01
0.005
X1
X2
Crystal
resonator
6.0 MHz
22 pF
22 pF
VDD
0.001
42
0
1
2
3
4
Supply Voltage VDD (V)
5
6
7
8
µPD75P3216
IDD vs VDD (System clock : 4.19 MHz Crystal resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
1.0
PCC = 0000
HALT mode
Supply Current IDD (mA)
0.5
0.1
0.05
0.01
0.005
X1
X2
Crystal
resonator
4.19 MHz
22 pF
22 pF
VDD
0.001
0
1
2
3
4
5
6
7
8
Supply Voltage VDD (V)
43
µPD75P3216
11. PACKAGE DRAWINGS
48 PIN PLASTIC SHRINK SOP (375 mil)
48
25
3°+7°
–3°
detail of lead end
1
24
A
G
H
I
K
F
J
N
E
C
D
M M
L
B
P48GT-65-375B-1
NOTE
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
44
ITEM
MILLIMETERS
INCHES
A
16.21 MAX.
0.639 MAX.
B
0.63 MAX.
0.025 MAX.
C
0.65 (T.P.)
0.026 (T.P.)
D
0.30 ± 0.10
0.012+0.004
–0.005
E
0.125 ± 0.075
0.005 ± 0.003
F
2.0 MAX.
0.079 MAX.
G
1.7 ± 0.1
0.067 ± 0.004
H
10.0 ± 0.3
0.394 +0.012
–0.013
I
8.0 ± 0.2
0.315 ± 0.008
J
1.0 ± 0.2
0.039+0.009
–0.008
K
0.15+0.10
–0.05
0.006+0.004
–0.002
L
0.5 ± 0.2
0.020+0.008
–0.009
M
0.10
0.004
N
0.10
0.004
µPD75P3216
12. RECOMMENDED SOLDERING CONDITIONS
The µPD75P3216 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
µPD75P3216GT: 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
Soldering
Method
Soldering Conditions
Symbol
Infrared rays
reflow
Peak package's surface temperature: 235 ˚C, Reflow time: 30 seconds or less
(at 210 ˚C or higher), Number of reflow processes: Twice max.
Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours)
<Precaution>
Products other than those supplied in thermal-resistant tray (magazine, taping, and nonthermal-resistant tray) cannot be baked in their packs.
IR35-107-2
VPS
Peak package's surface temperature: 215 ˚C, Reflow time: 40 seconds or less
(at 200 ˚C or higher), Number of reflow processes: Twice max.
Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours)
VP15-107-2
<Precaution>
Products other than those supplied in thermal-resistant tray (magazine, taping, and nonthermal-resistant tray) cannot be baked in their packs.
Wave soldering
Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Number of
WS60-107-1
flow process: 1, Preheating temperature: 120 ˚C or below (Package surface temperature)
Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours)
Partial heating
Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side)
Note
—
The number of days during which the product can be stored at 25 °C, 65 % RH max. after the dry pack
has been opened.
Caution
Use of more than one soldering method should be avoided (except for partial heating).
45
µPD75P3216
APPENDIX A. µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST
µPD753108
Parameter
µPD753208
Program memory
µPD75P3216
Mask ROM
One-time PROM
0000H-1FFFH
0000H-3FFFH
(8192 × 8 bits)
(16384 × 8 bits)
Data memory
000H-1FFH
(512 × 4 bits)
CPU
75XL CPU
Instruction
When main system
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation)
execution
time
clock is selected
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation)
When subsystem
122 µs (@ 32.768-kHz
clock is selected
I/O port
CMOS input
None
operation)
8 (on-chip pull-up resistors can
6 (on-chip pull-up resistors can be specified by software: 5)
be specified by software: 7)
CMOS input/output
20 (on-chip pull-up resistors can be specified by software)
N-ch open drain
4 (on-chip pull-up resistors can be specified by software,
4 (no mask option, withstand
input/output
withstand voltage is 13 V)
voltage is 13 V)
Total
32
LCD controller/driver
30
Segment selection: 16/20/24
Segment selection: 4/8/12 segments
(can be changed to CMOS
(can be changed to CMOS input/output port in 4 time-unit;
input/output port in 4 time-
max. 8)
unit; max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
Timer
On-chip split resistor for LCD driver can be specified by
No on-chip split resistor for
using mask option.
LCD driver
5 channels
5 channels
• 8-bit timer/event
• 8-bit timer counter: 2 channels
counter: 3 channels
(Can be used as 16-bit
(Can be used as 16-bit timer counter, carrier generator,
timer with gate)
timer/event counter, carrier
• 8-bit timer/event counter: 1 channel
generator, timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Basic interval timer/
• Watch timer: 1 channel
watchdog timer: 1 channel
• Watch timer: 1 channel
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz
(Main system clock: @ 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz
(Main system clock: @ 6.0-MHz operation)
Buzzer output (BUZ)
• 2, 4, 32 kHz
(Main system clock: @
4.19-MHz operation or subsystem clock: @ 32.768-kHz
• 2, 4, 32 kHz
(Main system clock: @ 4.19-MHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: @ 6.0-MHz operation)
operation)
• 2.86, 5.72, 45.8 kHz
(Main system clock: @
6.0-MHz operation)
Serial interface
3 modes are available
• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
• 2-wire serial I/O mode
• SBI mode
SCC register
Contained
None
External: 3, internal: 5
External: 2, internal: 5
SOS register
Vectored interrupt
46
µPD75P3216
Parameter
µPD753108
Test input
External: 1, internal: 1
Operation supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 64-pin plastic QFP
(14 × 14 mm)
µPD753208
µPD75P3216
• 48-pin plastic shrink SOP
(375 mil, 0.65-mm pitch)
• 64-pin plastic QFP
(12 × 12 mm)
47
µPD75P3216
APPENDIX B. DEVELOPMENT TOOLS
The following development tools have been provided for system development using the µPD75P3216.
In the 75XL series, relocatable assemblers common to the series can be used in combination with the device files for
each product type.
RA75X relocatable assembler
Host machine
Part No. (name)
OS
PC-9800 Series
Supply medium
TM
MS-DOS
Ver.3.30 to
3.5” 2HD
µS5A13RA75X
5” 2HD
µS5A10RA75X
Ver.6.2Note
Device file
IBM PC/ATTM
Refer to “OS for
3.5” 2HC
µS7B13RA75X
or compatible
IBM PCs”
5” 2HC
µS7B10RA75X
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOSTM
3.5” 2HD
µS5A13DF753208
5” 2HD
µS5A10DF753208
Ver.3.30 to
Ver.6.2Note
IBM PC/AT
Refer to “OS for
3.5” 2HC
µS7B13DF753208
or compatible
IBM PCs”
5” 2HC
µS7B10DF753208
Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described
above.
48
µPD75P3216
PROM Write Tools
Hardware
Software
PG-1500
This is a PROM programmer that can program single-chip microcomputer with PROM in
stand alone mode or under control of host machine when connected with supplied
accessory board and optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.
PA-75P3216GT
This is a PROM programmer adapter for the µPD75P3216GT.
It can be used when connected to a PG-1500.
PG-1500 controller
Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500
on host machine.
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5” 2HD
µS5A13PG1500
5” 2HD
µS5A10PG1500
Ver.3.30 to
Ver.6.2Note
IBM PC/AT
Refer to “OS for
3.5” 2HD
µS7B13PG1500
or compatible
IBM PCs”
5” 2HC
µS7B10PG1500
Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remark
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described
above.
49
µPD75P3216
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3216.
Various system configurations using these in-circuit emulators are listed below.
Hardware
IE-75000-RNote 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging
during development of application systems using the 75X or 75XL Series products.
For development of the µPD753208 subseries, the IE-75000-R is used with optional
emulation board (IE-75300-R-EM) and emulation probe (EP-753208GT-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
The IE-75000-R includes a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging
during development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used in combination with optional emulation board (IE-75300-R-EM) and
emulation probe (EP-753208GT-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems using the µPD75P3216.
It is used in combination with the IE-75000-R or IE-75001-R.
EP-753208GT-R
This is an emulation probe for the µPD75P3216GK.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-REM.
EV-9500GT-48
Software
IE control program
It includes a flexible board (EV-9500GT-48) to facilitate connections with target system.
This program can control the IE-75000-R or IE-75001-R on a host machine when connected
to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5” 2HD
µS5A13IE75X
5” 2HD
µS5A10IE75X
Ver.3.30 to
Ver.6.2Note 2
IBM PC/AT
Refer to “OS for
3.5” 2HC
µS7B13IE75X
or compatible
IBM PCs”
5” 2HC
µS7B10IE75X
Notes 1. This is a maintenance product.
2. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described
above.
2. The generic name for the µPD753204, 753206, 753208, and 75P3216 is the µPD753208 subseries.
50
µPD75P3216
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
Version
PC DOSTM
Ver.5.02 to Ver.6.3
J6.1/VNote to J6.3/VNote
MS-DOS
Ver.5.0 to Ver.6.22
5.0/VNote to 6.2/VNote
IBM DOSTM
J5.02/VNote
Note Only English version is supported.
Caution Ver. 5.0 or later include a task swapping function, but this software is not able to use that function.
51
µPD75P3216
APPENDIX C. RELATED DOCUMENTS
Some of the related documents are preliminary but are not marked as such.
Device related documents
Document Number
Document Name
Japanese
English
µPD753204, 753206, 753208 preliminary product information
U10166J
U10166E
µPD75P3216 data sheet
U10241J
This document
µPD753208 user’s manual
U10158J
U10158E
75XL series selection guide
U10453J
U10453E
Development tool related documents
Document Number
Document Name
Japanese
Hardware
Software
English
IE-75000-R/IE-75001-R user’s manual
EEU-846
EEU-1416
IE-75300-R-EM user’s manual
U11354J
U11354E
EP-753208GT-R user’s manual
U10739J
U10739E
PG-1500 user’s manual
EEU-651
EEU-1335
Operation
EEU-731
EEU-1346
Language
EEU-730
EEU-1363
PC-9800 series
(MS-DOS) base
EEU-704
EEU-1291
IBM PC series
(PC DOS) base
EEU-5008
U10540E
RA75X assembler package user’s manual
PG-1500 controller user’s manual
Other related documents
Document Number
Document Name
Japanese
English
IC package manual
C10943X
Semiconductor device mounting technology manual
C10535J
C10535E
Quality grade on NEC semiconductor devices
C11531J
C11531E
NEC semiconductor device reliability/quality control system
C10983J
C10983E
Static electricity discharge (ESD) test
MEM-539
Semiconductor device quality guarantee guide
MEI-603
Microcomputer related product guide - other manufacturers
U11416J
–
MEI-1202
–
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
documents for designing, etc.
52
µPD75P3216
[MEMO]
53
µPD75P3216
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS devices
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
54
µPD75P3216
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
55
µPD75P3216
[MEMO]
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
56